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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEATURES: DESCRIPTION:
QS5LV919
* * * * * * * * * * * * *
3.3V operation JEDEC compatible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0-Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to MC88LV915, IDT74FCT388915 Positive or negative edge synchronization (PE) Balanced drive outputs 24mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages
The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs. The QS5LV919 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5LV919 is designed for use in high-performance workstations, multiboard computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL LO CK SYNC0 SYNC1 O E/RST
0 0 1 PH A SE DETECTO R LOO P FILTER 1
PE
FEEDBACK
PLL_EN
FREQ _SEL
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /2
Q5
Q4
Q3
Q2
Q1
Q0
2xQ
INDUSTRIAL TEMPERATURE RANGE
1
c 2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JULY 2001
DSC-5820/3
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE/RST
GND
Q5 VDD OE/RST FEEDBACK REF_SEL SYNC0 AVDD PE AGND SYNC1 FREQ_SEL GND Q0
2 3 4 5 6 7 8 9 10 11 12 13 14
27 26 25 24 23 22 21 20 19 18 17 16 15
VDD 2xQ Q/2 GND Q3 VDD Q2 GND LOCK PLL_EN GND Q1 VDD
AGND SYNC1 10 11 FEEDBACK REF_SEL SYNC0 AVDD PE 5 6 7 8 9
4
3
2
1
28
27
26 25 24 23 22 21 20 19 Q/2 GND Q3 VDD Q2 GND LOCK
12
FREQ_SEL
13
GND
14
Q0
15
VDD
16
Q1
17
GND
18
PLL_EN
QSOP TOP VIEW
PLCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Rating DC Input Voltage VIN Maximum Power TSTG QSOP Dissipation (TA = 85C) PLCC Storage Temperature Range Max. -0.5 to +7 -0.5 to +5.5 655 770 -65 to +150 Unit V V mW mW C VDD, AVDD Supply Voltage to Ground
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25C, f = 1MHz, VIN = 0V)
QSOP Parameter CIN Typ. 3 Max. 4 Typ. 4 PLCC Max. 6 Unit pF
2
2xQ
VDD
Q5
Q4
VDD
GND
1
28
Q4
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name SYNC0 SYNC1 REF_SEL FREQ_SEL FEEDBACK Q0 -Q4 Q5 2xQ Q/2 LOCK OE/RST PLL_EN PE VDD AVDD GND AGND I/O I I I I I O O O O O I I I -- -- -- -- Description Reference clock input Reference clock input Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0. VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Clock output. Matched in frequency, but inverted with respect to Q. Clock output. Matched in phase, but frequency is double the Q frequency. Clock output. Matched in phase, but frequency is half the Q frequency. PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Useful for testing purposes. When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the negative edge of SYNC. Power supply for output buffers. Power supply for phase lock loop and other internal circuitries. Ground supply for output buffers. Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = -40C to +85C, AVDD / VDD = 3.3V 0.3V
Symbol FMAX_2XQ FMAX_Q FMAX_Q/2 FMIN_2XQ FMIN_Q FMIN_Q/2 Description Max Frequency, 2xQ Max Frequency, Q0 - Q4, Q5 Max Frequency, Q/2 Min Frequency, 2xQ Min Frequency, Q0 - Q4, Q5 Min Frequency, Q/2 - 55 55 27.5 13.75 20 10 5 - 70 70 35 17.5 20 10 5 - 100 100 50 25 20 10 5 - 133 133 66.5 33.25 20 10 5 - 160 160 80 40 20 10 5 Units MHz MHz MHz MHz MHz MHz
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
SYNC (MHz) Output Used for FREQ_SEL HIGH HIGH HIGH HIGH LOW LOW LOW LOW Feedback Q/2 Q0 -Q4 Q5 2xQ(3) Q/2 Q0 -Q4 Q5 2xQ (allowable range)(1) Min. FMIN_Q/2 FMIN_Q FMIN_Q FMIN_2XQ FMIN_Q/2 /2 FMIN_Q /2 FMIN_Q /2 FMIN_2XQ /2 Max FMAX _Q/2 FMAX _Q FMAX _Q 100 FMAX _Q/2 /2 FMAX _Q /2 FMAX _Q /2 FMAX _2XQ /2 Q/2 SYNC SYNC / 2 - SYNC / 2 SYNC / 4 SYNC SYNC / 2 - SYNC / 2 SYNC / 4 Output Frequency Relationships(2) Q5 - SYNC X 2 - SYNC SYNC - SYNC / 2 - SYNC X 2 - SYNC SYNC - SYNC / 2 Q0 - Q4 SYNC X 2 SYNC - SYNC SYNC / 2 SYNC X 2 SYNC - SYNC SYNC / 2 2XQ SYNC X 4 SYNC X 2 - SYNC X 2 SYNC SYNC X 4 SYNC X 2 - SYNC X 2 SYNC
NOTES: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2XQ. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies. 2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz. 3. The 2xQ is limited to a maximum frequency (FMAX_2XQ) of 100MHz only when used as a feedback.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40C to +85C, AVDD/VDD= 3.3V 0.3V
Symbol VIH VIL VOH VOL VH IOZ IIN IPD Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Hysteresis Output Leakage Current Input Leakage Current Input Pull-Down Current (PE) Conditions Guaranteed Logic HIGH Level Guaranteed Logic LOW Level IOH = -24mA IOH = -100A VDD = Min., IOL = 100A -- VOUT = VDD or GND, VDD = Max. AVDD = Max., VIN = AVDD or GND AVDD = Max., VIN = AVDD Min. 2 -- VDD - 0.6 VDD - 0.2 -- -- -- -- -- -- Typ. -- -- -- -- -- -- 100 -- -- -- Max. -- 0.8 -- -- 0.45 0.2 -- 5 5 100 mV A A A V Unit V V V
VDD = Min., IOL = 24mA
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDD IDDD
NOTE: 1. Relative to the frequency of Q outputs.
Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current (1)
Test Conditions VDD = Max., OE/RST = LOW, SYNC = LOW, All outputs unloaded VDD = Max., VIN = 3V VDD = Max., CL = 0pF
Typ.
Max. 1
Unit mA A mA/MHz
1 0.2
30 0.4
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
Symbol tR, tF FI tPWC DH Description(1) Maximum input rise and fall times, 0.8V to 2V Input Clock Frequency, SYNC0, SYNC1 Input clock pulse, HIGH or LOW(2) Input duty cycle, SYNC0, SYNC1
(2) (1)
Min. -- 2.5 2 25
Max. 3 100 -- 75
Unit ns MHz ns %
NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tSKR tSKF tSKALL tPW tPW tJ tPD tLOCK tPZH tPZL tPHZ tPLZ tR, tF Output Rise/Fall Times, 0.8V 2V 0.3 2 ns Output Disable Time, OE/RST HIGH to LOW(3) 0 14 ns Parameter(1) Output Skew Between Rising Edges, Q0-Q4 (and Q/2 if PE = LOW)(2) Output Skew Between Falling Edges, Q0-Q4 (and Q/2 if PE = HIGH) Output Skew, All Outputs(2, 5) Pulse Width, 2xQ output, >40MHz Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz Cycle-to-Cycle Jitter(4) SYNC Input to Feedback Delay(6) SYNC to Phase Lock Output Enable Time, OE/RST LOW to HIGH(3)
(2)
Min. -- -- -- TCY/2 - 0.4 TCY/2 - 0.4
Max. 300 300 500 TCY/2 + 0.4 TCY/2 + 0.4 0.15 0 10 14
Unit ps ps ps ns ns ns ps ms ns
- 0.15 - 500
-- 0
NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies. 5. Skew measured at selected synchronization edge. 6. tPD measured at device inputs at 0.5VDD, Q output at 80MHz.
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
BOAR D VCC
INDUSTRIAL TEMPERATURE RANGE
ANALOG VCC
DIGITAL VCC
10 F Low Freq. Bypass
0.1 F High Freq. Bypass DIGITAL GND
0.1 F Bypass
ANALOG G ND
BOARD GND A separate Analog power supply is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the QS5LV919 in a norm al digital environment.
Figure 1. Recommended Analog Isolation Scheme for the QS5LV919
NOTES: 1. Figure 1 shows an analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: a. All analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients. b. The 10F low frequency bypass capacitor and the 0.1F high frequency bypass capacitor form a wide bandwidth filter that will minimize the QS5LV919's sensitivity to voltage transients from the system digital VCC supply and ground planes. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the QS5LV919's digital VCC supply. The purpose of the bypass filtering scheme shown in figure 1 is to give the QS5LV919 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 2. The bypass capacitors can be ceramic chip capacitors. There should be a 0.1F bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the QS5LV919 outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass capacitors should also be tied as close to the QS5LV919 package as possible.
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5LV919 provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, `propagation delay' can even be negative! A simplified schematic of the QS5LV919 PLL circuit is shown below.
SIMPLIFIED DIAGRAM OF QS5LV919 FEEDBACK
2xQ
Q
Q
Q /2
INPUT PHASE DETECTO R
VCO
/2
/2
The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5LV919 typically provides within 150ps of phase shift between input and output.
If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output.
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
50 MHz signal
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the 2Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency. Note that with 2Q as feedback, the maximum input frequency is 100MHz for FS = HIGH
25 MHz feedback signal HIGH OE/ RST FEEDBACK LOW 25 MHz input REF_SEL SYNC(0) VCC(AN) PE QS5LV919 Q5 Q4
2Q Q/2 12.5 MHz signal
Q3
Q2
25 MHz "Q" Clock Outputs
50 MHz feedback signal HIGH OE/ RST Q5 Q4 2Q Q/2 12.5 MHz input 25 MHz "Q" Clock Outputs
GND(AN) FQ_SEL Q0 Q1 PLL_EN HIGH
FEED BACK LOW 50 MHz input REF_SEL SYNC(0) VCC(AN) PE GND(AN) FQ_SEL Q0 Q1 QS5LV919
HIGH
Q3
Allowable Input Frequency Range: 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH) 10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
Q2
Figure 2b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2 frequency.
12.5 MHz feedback signal 50 MHz signal
PLL_EN HIGH
HIGH
Allowable Input Frequency Range: 40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH) 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
HIGH OE/ RST Q5 Q4 2Q Q/2
Figure 2a. Wiring Diagram and Frequency Relationships with 2Q Output Feedback
LOW
FEEDBACK REF_SEL SYNC(0) VCC(AN) PE GND(AN) FQ_SEL Q0 HIGH Q1 QS5LV919
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run at 2X the Q frequency.
12.5 MHz input
Q3
Q2
25 MHz "Q" Clock Outputs
PLL_EN HIGH
Allowable Input Frequency Range: 10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH) 5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Figure 2c. Wiring Diagram and Frequency Relationships with Q2 Output Feedback 8
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
CM MU QS5LV919 CLOCK @f PLL 2f CPU
CMMU
CPU CARD
CMMU
SYS TEM CLO CK SO URCE
CM MU
CMMU
CM MU QS5LV919 PLL 2f CPU
CMMU
CPU CARD
CMMU
DISTRIBUTE CLO CK @ f
CM MU
CMMU
CLOCK @ 2f at point of use
QS5LV919 PLL 2f MEMORY CO NTROL
ME MO RY CAR DS CLO CK @ 2f at point of use
Figure 3. Multiprocessing Application Using the QS5LV919 for Frequency Multiplication and Low Board-to-Board skew
QS5LV919 System Level Testing Functionality When the PLL_EN pin is LOW, the PLL is bypassed and the QS5LV919 is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q output is inverted from the selected SYNC input, and the Q outputs are divideby-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divideby-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divideby-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8. These relationships can be seen in the block diagram. A recommended test configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to the test select logic. This functionality is needed since most board-level testers run at 1 MHz or below, and the QS5LV919 cannot lock onto that low of an input frequency. In the test mode described above, any test frequency test can be used.
9
QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
VDD
300 7.0V OUTPUT 100
OUTPUT 300 100
30pF
TEST CIRCUIT 1
TEST CIRCUIT 2
1.0ns
1.0ns
tR 3.0V 2.0V 0.5VDD 0.8V 0V tPW
tF
3.0V 2.0V Vth = 0.5VDD 0.8V 0V
LVTTL INPUT TEST WAVEFORM
EN ABLE
LVTTL OUTPUT WAVEFORM
DISABLE 3V 0.5VDD
CONTROL INPU T tPZL OUTPUT NOR MALLY LOW SWITCH CLO SED 0.3V tPZH SWITCH OUTPUT NOR MALLY HIGH OPEN 0.5VDD tPHZ 0.3V VOH VOL 0.5VDD tPLZ 3.0V 0V
0V
ENABLE AND DISABLE TIMES
TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters.
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
AC TIMING DIAGRAM
SYNC
tPD FEEDBACK tJ Q tSKF Q0-Q4 tSKR Q/2
2xQ t SKA LL Q5
NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC. 2. All parameters are measured at 0.5VDD.
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS XXXX Device Type XX Speed X Package X Process
Blank Q J
Industrial (-40C to +85C) Quarter Size Outline Package Plastic Leaded Chip Carrier
55 70 100 133 160
55MHz Max. Frequency 70MHz Max. Frequency 100MHz Max. Frequency 133MHz Max. Frequency 160MHz Max. Frequency
5LV919 Low Skew CMOS PLL Clock Driver with Integrated Loop Filter
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