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1
CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V
3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
Features
* True Dual-Ported memory cells which allow simultaneous access of the same memory location * 4K/8K/16K/32K x 8 organizations (CY7C0138V/144V/ 006V/007V) * 4K/8K/16K/32K x 9 organizations (CY7C0139V/145V/ 016V/017V) * 0.35-micron CMOS for optimum speed/power * High-speed access: 15[1]/20/25 ns * Low operating power -- Active: ICC = 115 mA (typical) -- Standby: ISB3 = 10 A (typical) * Fully asynchronous operation * Automatic power-down * Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device * On-chip arbitration logic * Semaphores included to permit software handshaking between ports * INT flag for port-to-port communication * Pin select for Master or Slave * Commercial and Industrial Temperature Ranges * Available in 68-pin PLCC (all), 64-pin TQFP (7C006V & 7C144V) * Pin-compatible and functionally equivalent to IDT70V05, 70V06, and 70V07.
Logic Block Diagram
R/WL CEL OEL R/WR CER OER
[2]
8/9
8/9
[2]
I/O0L-I/O7/8L I/O Control I/O Control
I/O0R-I/O7/8R
[3]
12-15
A0L-A11-14L
Address Decode
12-15
True Dual-Ported RAM Array
Address Decode
12-15
12-15
[3]
A0R-A11-14R
[3]
[3]
A0L-A11-14L CEL OEL R/WL SEM L BUSYL INTL
Interrupt Semaphore Arbitration
A0R-A11-14R CER OE R R/WR SEM R BUSY R INT R
[4]
[4]
M/S
Notes: 1. Call for availability 2. I/O0-I/O7 for x8 devices; I/O0-I/O8 for x9 devices. 3. A0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K devices; A0-A14 for 32K devices. 4. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 30, 1999
PRELIMINARY
Functional Description
The CY7C138V/144V/006V/007V and CY7C139V/145V/ 016V/017V are low-power CMOS 4K, 8K, 16K, and 32K x8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multi-
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
processor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. .
Pin Configurations
68-Pin PLCC Top View
I/O 1L I/O 0L NC [6] OE L R/W L SEM L CEL NC NC VCC NC A 11L A 10L A9L A8L A7L A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R 47 46 45 44 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 I/O7R R/W R SEM R CER NC NC GND NC A 11R A10R A 9R A8R NC OER A7R A6R A5R
[5]
9876 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C138V (4K x 8) 52 CY7C139V (4K x 9) 51 50 49 48
Notes: 5. I/O8R on the CY7C139V. 6. I/O8L on the CY7C13V9.
2
PRELIMINARY
Pin Configurations (continued)
68-Pin PLCC Top View
I/O 1L I/O 0L NC OE L R/W L SEM L CEL
[8]
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
NC NC VCC A12L A 11L A 10L A9L
A8L A7L
9876 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I/O7R
[7]
5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C144V (8K x 8) 52 CY7C145V (8K x 9) 51 50 49 48 47 46 45 44
A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 A 9R A8R NC OER R/W R SEM R CER NC NC GND A12R A 11R A10R A7R A6R A7L 51 50 A5R
64-Pin TQFP Top View
SEML R/WL I/O1L I/O0L A12L A11L A10L OEL CEL NC VCC A9L A8L 52 A6L A5L 49
64
63
62 61
60
59
58
57
56 55
54
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R
53
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
CY7C144V (8K x 8)
17
18
19 20
21
22
23
24
25 26
27
28
29
30 31 A7R
R/WR
SEMR
I/O6R
GND
CER NC
A9R
A8R
I/O7R
OER
A12R
Notes: 7. I/O8R on the CY7C145V. 8. I/O8L on the CY7C145V.
3
A11R A10R
A6R A5R
32
16
33
PRELIMINARY
Pin Configurations (continued)
80-Pin TQFP Top View
I/O1L I/O0L SEM L R/W L I/O8L A12L A11L OE L CE L NC A10L VCC A9L A8L A7L 64 NC NC
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
A6L
80
79
78 77
76
75
74
73
72 71
70
69
68
67
66 65
63 62
NC I/O 2L I/O 3L I/O 4L I/O 5L GND I/O 6L I/O 7L V CC NC GND I/O0R I/O1R I/O2R V CC I/O 3R I/O 4R I/O 5R I/O 6R NC
1 2 3 4 5 6 7 8
61
NC NC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC
9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26
CY7C145V (8K x 9)
27
28
29 30
31
32
33
34
35 36
37
38 39 NC NC A5R
I/O7R
R/WR
SEMR
GND
CER
A9R
A8R
A7R
A6R
NC
NC NC
I/O8R
OER
A12R
80-Pin TQFP Top View
NC(A14L [10]) NC(I/O8L [9] )
SEM L
R/W L
I/O1L I/O0L
OE L
A13L
A12L
A11L
CE L NC
A10L
VCC
A11R A10R
A9L
A8L
A7L
A6L
80
79
78 77
76
75
74
73
72 71
70
69
68
67
66 65
64
63 62
NC I/O 2L I/O 3L I/O 4L I/O 5L GND I/O 6L I/O 7L V CC NC GND I/O0R I/O1R I/O2R V CC I/O 3R I/O 4R I/O 5R I/O 6R NC
1 2 3 4 5 6 7 8
61
NC
NC
40
20
41
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC
CY7C007V (32K x 8) CY7C016V (8K x 9)
[1]
9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25
CY7C017V (32K x 9)
26
27
28
29 30
31
32
33
34
35 36
37
38 39 NC A5R
I/O7R
A9R
A8R
A7R
R/WR
SEMR
CER
NC NC(A14L[10])
A13R
GND
A6R
A12R
Notes: 9. I/O for CY7C016V and CY7C017V only. 10. Address line for CY7C007V and CY7C01V7 only.
NC(I/O8R[9])
4
A11R A10R
OER
NC
40
20
41
PRELIMINARY
Pin Configurations (continued)
68-Pin PLCC Top View
NC(I/O8L[9]) OEL NC(A 14L [10]) A13L
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
SEML
R/WL
I/O1L
I/O0L
A12L
A11L A10L
CEL
VCC
A9L
A8L A7L 63 62
68 67
66
65
64
61 60 59 58 57 56 55 54
9
8
7 6
5
4
3
2 1
A6L
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 26
A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
CY7C006V (16K CY7C007V (32K CY7C016V (16K CY7C017V (32K
x 8) x 8) x 9) x 9)
53 52 51 50 49 48 47 46 45 44
NC(I/O8R[9] )
NC(A 14R [10])
SEMR
CER
GND
A9R
A8R A7R 51 50
A13R
A12R
OER R/WR
I/O7R
64-Pin TQFP Top View
SEML R/WL I/O1L I/O0L CEL A13L A12L A11L A10L OEL VCC A9L A8L A7L 52 A6L A5L 49
64
63
62 61
60
59
58
57
56 55
54
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R
53
A11R A10R
A6R A5R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42
A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
CY7C006V (16K x 8)
41 40 39 38 37 36 35 34
17
18
19 20
21
22
23
24
25 26
27
28
29
30 31
R/WR
SEMR
CER A13R
I/O6R
GND
OER
A12R
A11R A10R
A9R
A8R A7R
I/O7R
5
A6R A5R
32
16
33
PRELIMINARY
Selection Guide
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
CY7C138V/144V/006V/007V CY7C138V/144V/006V/007V CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V CY7C139V/145V/016V/017V CY7C139V/145V/016V/017V -15[1] -20 -25 Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL level) Typical Standby Current for ISB3 (A) (Both Ports CMOS level)
Shaded areas contain advance information.
15 125 35 10 A
20 120 35 10 A
25 115 30 10 A
Pin Definitions
Left Port CEL R/WL OEL A0L-A14L I/O0L-I/O 8L SEML INTL BUSYL M/S VCC GND NC Right Port CER R/WR OER A0R-A14R I/O0R-I/O8R SEM R INTR BUSYR Chip Enable Read/Write Enable Output Enable Address (A 0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K devices; A 0-A14 for 32K) Data Bus Input/Output (I/O 0-I/O7 for x8 devices and I/O0-I/O8 for x9) Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V Latch-Up Current .................................................... >200 mA Description
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied .............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................-0.5V to VCC+0.5V DC Input Voltage[11] .................................-0.5V to VCC+0.5V
Note: 11. Pulse width < 20 ns.
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 300 mV 3.3V 300 mV
Shaded areas contain advance information.
6
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V -15[1] Parameter VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage (VCC = 3.3V) Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL & CER VIH, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level) CEL & CER VCC - 0.2V, f=0 Com'l. Indust. Com'l. Indust. Com'l. Indust. Com'l. Indust. 75 105 10 500 80 120 35 50 -10 125 2.0 0.8 10 185 -10 120 140 35 45 75 85 10 10 70 80 Min. 2.4 0.4 2.0 0.8 10 175 195 45 55 110 130 500 500 95 105 -10 115 135 30 40 65 75 10 10 60 70 Typ. Max. Min. 2.4 0.4 2.0 0.8 10 165 185 40 50 95 105 500 500 80 90 -20 Typ. Max. Min. 2.4 0.4 -25 Typ. Max. Unit V V V V A mA mA mA mA mA mA A A mA mA
ISB4
Standby Current (One Port CMOS Com'l. Level) CE L | CER V IH, f = fMAX[12] Indust.
Shaded areas contain advance information.
Capacitance[13]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms
3.3V 3.3V R1 = 590 OUTPUT C = 30 pF R2 = 435 VTH = 1.4V OUTPUT C = 30pF RTH = 250 R1 = 590 OUTPUT C = 5 pF R2 = 435
(a) Normal Load (Load 1)
(b) TheveninEquivalent (Load 1) ALL INPUT PULSES
3.0V GND 10% 3 ns 90% 90% 10% 3 ns
(c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE& tLZWE including scope and jig)
Notes: 12. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 13. Tested initially and after any design or process changes that may affect these parameters.
7
PRELIMINARY
Switching Characteristics Over the Operating Range[14]
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V -15[1] Parameter READ CYCLE tRC tAA tOHA tACE[15] tDOE tLZOE[16, 17, 18] tHZOE[16, 17, 18] tLZCE[16, 17, 18] tHZCE[16, 17, 18] tPU[18] tPD[18] tABE[15] WRITE CYCLE tWC tSCE[15] tAW tHA tSA[15] tPWE tSD tHD tHZWE[17, 18] tLZWE[17, 18] tWDD[19] tDDD[19] BUSY TIMING tBLA tBHA tBLC tBHC tPS tWB tWH Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid
[20]
-20 Min. 20 15 20 3 15 10 20 12 3 10 12 3 10 12 0 15 15 20 20 20 16 16 0 0 16 12 0 10 12 3 30 25 15 15 15 15 40 30 20 20 20 16 5 0 15 5 0 17 3 25 20 20 0 0 20 15 0 0 3 3 3 Max. Min. 25
-25 Max. Unit ns 25 25 13 15 15 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 50 35 20 20 20 17 ns ns ns ns ns ns ns ns ns ns ns
Description Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Byte Enable Access Time
Min. 15 3
Max.
3 3 0
15 12 12 0 0 12 10 0 3
BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-Up for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) 5 0 13
Note: 14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OI/IOH and 30-pF load capacitance. 15. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 17. Test conditions used are Load 3. 18. This parameter is guaranteed but not tested.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 20. Test conditions used are Load 2.
8
PRELIMINARY
Switching Characteristics Over the Operating Range[14] (continued)
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V -15[1] Parameter tBDD[21] tINS tINR tSOP tSWRD tSPS tSAA INTERRUPT TIMING
[20]
-20 Min. Max. 20 20 20 10 5 5 15 20 12 5 5 Min. 15 15 15
-25 Max. 25 20 20 Unit ns ns ns ns ns ns 25 ns
Description BUSY HIGH to Data Valid INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time
Min.
Max.
SEMAPHORE TIMING 10 5 5
Data Retention Mode
The CY7C0138V/144V/006V/007V and CY7C139V/145V/ 016V/017V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC - 0.2V. 2. CE must be kept between V CC - 0.2V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 volts).
Timing
Data Retention Mode VCC 3.0V VCC > 2.0V 3.0V tRC
V IH
CE
VCC to VCC - 0.2V
Parameter ICC DR1
Test Conditions[22] @ VCCDR = 2V
Max. 50
Unit A
Notes: 21. tBDD is a calculated parameter and is the greater of tWDD-tPWE (actual) or tDDD-tSD (actual). 22. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
9
PRELIMINARY
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[23, 24, 25]
tRC ADDRESS tOHA DATA OUT tAA
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
tOHA DATA VALID
PREVIOUS DATA VALID
Read Cycle No .2 (Either Port CE/OE Access)[23, 26, 27]
tACE tHZCE OE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID tDOE tHZOE
CE
Read Cycle No. 3 (Either Port)[23, 25, 26, 27]
tRC ADDRESS tAA tOHA
tLZCE tABE CE tACE tLZCE DATA OUT tHZCE
Notes: 23. R/W is HIGH for read cycles. 24. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads. 25. OE = VIL. 26. Address valid prior to or coincident with CE transition LOW. 27. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
10
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31]
tWC ADDRESS
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
tHZOE [33] OE tAW CE
[32]
tSA R/W tHZWE[33] DATA OUT NOTE 34
tPWE[31]
tHA
tLZWE NOTE 34 tSD tHD
DATA IN
Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 35]
tWC ADDRESS tAW CE
[32]
tSA R/W
tSCE
tHA
tSD DATA IN
tHD
Notes: 28. R/W must be HIGH during all address transitions. 29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM. 30. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 32. To access RAM, CE = VIL, SEM = VIH. 33. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 34. During this period, the I/O pins are in the output state, and input signals must not be applied. 35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
11
PRELIMINARY
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[36]
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
tSAA A 0-A 2 VALID ADRESS tAW SEM tSCE tSD I/O 0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATA IN VALID tPWE tHD tHA tSOP VALID ADRESS tACE
tOHA
DATA OUT VALID
Timing Diagram of Semaphore Contention[37, 38, 39]
A0L -A 2L
MATCH
R/WL SEM L tSPS A 0R -A 2R MATCH
R/WR SEM R
Notes: 36. CE = HIGH for the duration of the above timing (both write and read cycle). 37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 38. Semaphores are reset (available to both ports) at cycle start. 39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
12
PRELIMINARY
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[40]
tWC ADDRESSR R/WR MATCH tPWE
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
tSD DATA IN R tPS ADDRESSL MATCH tBLA BUSYL tDDD DATA OUTL tWDD VALID
tHD
tBHA tBDD
VALID
Write Timing with Busy Input (M/S=LOW)
R/W tWB tPWE
BUSY
tWH
Note: 40. CEL = CER = LOW.
13
PRELIMINARY
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[41] CELValid First:
ADDRESS L,R CEL tPS CER tBLC BUSYR ADDRESS MATCH
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
tBHC
CER Valid First:
ADDRESS L,R CER tPS CE L tBLC BUSY L tBHC ADDRESS MATCH
Busy Timing Diagram No.2 (Address Arbitration)[41] Left Address Valid First
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESSR tBLA BUSY R tBHA ADDRESS MISMATCH
Right Address Valid First:
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSY L tBHA ADDRESS MISMATCH
Note: 41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
14
PRELIMINARY
Switching Waveforms (continued)
Interrupt Timing Diagrams Left Side Sets INTR :
ADDRESSL CE L R/W L INT R tINS [43]
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
tWC WRITE FFF (See Functional Description) tHA [42]
Right Side Clears INT R :
ADDRESSR CE R tINR [43] R/WR OE R INTR
tRC READ FFF (See Functional Description)
Right Side Sets INT L:
tWC ADDRESSR CE R R/W R INT L tINS
[43]
WRITE FFE (See Functional Description) tHA[42]
Left Side Clears INT L:
ADDRESSR CE L tINR[43] R/W L OE L INT L
Notes: 42. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 43. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
tRC READ FFE (See Functional Description)
15
PRELIMINARY
Architecture
The CY7C138V/144V/006V/007V and CY7C139V/145V/ 016V/017V consist of an array of 4K, 8K, 16K, and 32K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for portto-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device.
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
access (contention). If both ports' CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C138V/144V/006V/007V and CY7C139V/145V/ 016V/017V provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Functional Description
Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for noncontention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C138V/9V, 1FFF for the CY7C144V/5V, 3FFF for the CY7C006V/16V, 7FFF for the CY7C007V/17V) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C138V/9V, 1FFE for the CY7C144V/5V, 3FFE for the CY7C006V/16V, 7FFE for the CY7C007V/17V) is the mailbox for the left port. When one port writes to the other port's mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user-defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C138V/144V/006V/007V and CY7139V/145V/016V/017V provide on-chip arbitration to resolve simultaneous memory location
16
PRELIMINARY
Table 1. Non-Contending Read/Write Inputs CE H H X H L L L H L X R/W X H X OE X L H X L X X SEM H L X L H H L Outputs I/O0-I/O8 High Z Data Out High Z Data In Data Out Data In Deselected: Power-Down
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
Operation Read Data in Semaphore Flag I/O Lines Disabled Write into Semaphore Flag Read Write Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X X CEL L X X L OEL X X X L A0L-14L FFF
[46]
Right Port INTL X X L[44] H[45] R/WR X X L X CER X L L X OE R X L X X A0R-14R X FFF[46] 1FFE[46] X INTR L[45] H[44] X X
X X 1FFE[46]
Table 3. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-I/O8 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0-I/O8 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left Port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free Status
Note: 44. If BUSYR = L, then no change. 45. If BUSYL = L, then no change. 46. See Functional Description for specific addresses by device part number.
17
PRELIMINARY
Ordering Information
Package Availability Guide Device CY7C138V CY7C139V CY7C144V CY7C145V CY7C006V CY7C016V CY7C007V CY7C017V Organization 4K x 8 4K x 9 8K x 8 8K x 9 16K x 8 16K x 9 32K x 8 32K x 9
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
68-Pin PLCC X X X X X X X X
64-Pin TQFP
X X
4K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 25 Ordering Code CY7C138V-15JC CY7C138V-20JC CY7C138V-20JI CY7C138V-25JC CY7C138V-25JI
Shaded areas contain advance information.
Package Name J81 J81 J81 J81 J81
Package Type 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Industrial Commercial Industrial
4K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 25 Ordering Code CY7C139V-15JC CY7C139V-20JC CY7C139V-20JI CY7C139V-25JC CY7C139V-25JI
Shaded areas contain advance information.
Package Name J81 J81 J81 J81 J81
Package Type 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Industrial Commercial Industrial
8K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 Ordering Code CY7C144V-15AC CY7C144V-15JC CY7C144V-20AC CY7C144V-20JC CY7C144V-20AI CY7C144V-20JI 25 CY7C144V-25AC CY7C144V-25JC CY7C144V-25AI CY7C144V-25JI
Shaded areas contain advance information.
Package Name A65 J81 A65 J81 A65 J81 A65 J81 A65 J81
Package Type 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Industrial Commercial Industrial
18
PRELIMINARY
Ordering Information (continued)
8K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 25 Ordering Code CY7C145V-15JC CY7C145V-20JC CY7C145V-20JI CY7C145V-25JC CY7C145V-25JI
Shaded areas contain advance information.
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
Package Name J81 J81 J81 J81 J81
Package Type 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Industrial Commercial Industrial
16K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 Ordering Code CY7C006V-15AC CY7C006V-15JC CY7C006V-20AC CY7C006V-20JC CY7C006V-20AI CY7C006V-20JI 25 CY7C006V-25AC CY7C006V-25JC CY7C006V-25AI CY7C006V-25JI
Shaded areas contain advance information.
Package Name A65 J81 A65 J81 A65 J81 A65 J81 A65 J81
Package Type 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Commercial Industrial Commercial Industrial
16K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 25 Ordering Code CY7C016V-15JC CY7C016V-20JC CY7C016V-20JI CY7C016V-25JC CY7C016V-25JI
Shaded areas contain advance information.
Package Name J81 J81 J81 J81 J81
Package Type 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Industrial Commercial Industrial
32K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 25 Ordering Code CY7C007V-15JC CY7C007V-20JC CY7C007V-20JI CY7C007V-25JC CY7C007V-25JI
Shaded areas contain advance information.
Package Name J81 J81 J81 J81 J81
Package Type 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Industrial Commercial Industrial
19
PRELIMINARY
Ordering Information (continued)
32K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) 15[1] 20 25 Ordering Code CY7C017V-15JC CY7C017V-20JC CY7C017V-20JI CY7C017V-25JC CY7C017V-25JI
Shaded areas contain advance information.
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
Package Name J81 J81 J81 J81 J81
Package Type 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier
Operating Range Commercial Commercial Industrial Commercial Industrial
Document #: 38-00677-B
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
20
PRELIMINARY
Package Diagrams (continued)
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C036 Dual Port Design Consideration - Data Sheet Addendum
This design consideration applies to the Internal Power-OnReset (POR) circuit used on the CY7C036 and its derivatives listed below. Power supply ramp--The devices will function properly and meet all data sheet specifications if the power supply ramp rate is greater than 100 ns. If ramp is less than 100 ns, you may see a non-destructive failure in which the device will not respond to changes in address or clock, but the I/Os will respond to the output enable. Applications consideration--If the power supply ramps in less than 100 ns, a small resistor (20-50), a large capacitor, or an RC network can be connected at the output of the power supply to ground. The addition of a resistor will help clean up the power lines, while the capacitor will slow down the ramp rate without the loss of any power. Contact your local Cypress FAE for assistance as needed. Troubleshooting--If a problem occurs with the part, power down the device to ground and then power up again at slower
CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V
ramp rate (greater than 100 ns) in order to confirm that the problem might be due to the POR circuit. If the dual-port functions properly once the ramp rate is slowed to 100 ns or greater, then the POR circuit is at fault. Applicable devices--All speed/package/temperature combinations of the following: * CY7C138V * CY7C139V * CY7C144V * CY7C145V * CY7C006V * CY7C016V * CY7C007V * CY7C017V Cypress design change--Cypress design team has identified the root cause. A permanent circuit change and die revision will be available beginning in October and will be identified by the letter "A" in the part number.
22

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