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| 1M x 4-Bit Dynamic RAM HYB 514400BJ-50/-60 Advanced Information * 1 048 576 words by 4-bit organization * 0 to 70 C operating temperature * Fast Page Mode Operation * Performance: -50 -60 60 15 30 110 40 ns ns ns ns ns tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 95 35 * Single + 5 V ( 10 %) supply with a built-in VBB generator * Low power dissipation max. 660 mW active (-50 version) max. 605 mW active (-60 version) * Standby power dissipation: 11 mW max. standby (TTL) 5.5 mW max. standby (CMOS) * Output unlatched at cycle end allows two-dimensional chip selection * Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability * All inputs and outputs TTL-compatible * 1024 refresh cycles / 16 ms * Plastic Packages: P-SOJ-26/20-2 with 300 mil width Semiconductor Group 1 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM The HYB 514400BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by 4-bit. The HYB 514400BJ/BJL utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514400BJ/BJL to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Ordering Information Type HYB 514400BJ-50 HYB 514400BJ-60 Ordering Code Q67100-Q973 Q67100-Q756 Package P-SOJ-26/20-2 300 mil P-SOJ-26/20-2 300 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) Semiconductor Group 2 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM P-SOJ-26/20-2 I/O1 I/O2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 V SS I/O4 I/O3 CAS OE A0 A1 A2 A3 V CC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 SPP02797 Pin Configuration Pin Names A0 - A9 RAS CAS WE OE I/O1 - I/O4 Address Input Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply (+ 5 V) Ground (0 V) No Connection VCC VSS N.C. Semiconductor Group 3 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM I/O1 I/O2 I/O3 I/O4 Data In Buffer WE CAS & 4 Data Out Buffer 4 OE No.2 Clock Generator 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10 Column Address Buffers (10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating 4 Refresh Counter (10) 1024 x 4 . . . . . . Row Address Buffers (10) 10 Row Decoder . . . 1024 . . . Memory Array 1024 x 1024 x 4 RAS No.1 Clock Generator Substrate Bias Generator V CC V SS SPB02798 Block Diagram Semiconductor Group 4 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................... 0 to 70 C Storage temperature range.................................................................................... - 55 to + 150 C Input/output voltage ....................................................................................................... - 1 to + 7 V Power Supply voltage .................................................................................................... - 1 to + 7 V Data out current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %, tT = 5 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current, any input (0 V < VIN < 7, all other input = 0 V) Output leakage current (DO is disabled, 0 < VOUT < VCC) Average VCC supply current -50 version -60 version Standby VCC supply current (RAS = CAS = WE = VIH) Symbol Limit Values min. max. 0.8 - 0.4 10 10 2.4 - 1.0 2.4 - - 10 - 10 Unit Test Condition 1 1 1 1 1 VIH VIL VOH VOL II(L) IO(L) ICC1 VCC + 0.5 V V V V A A mA 1 2, 3, 4 - - 120 110 2 mA mA 2, 4 ICC2 - ICC3 Average VCC supply current during RAS-only refresh cycles -50 version -60 version Average VCC supply current during fast page ICC4 mode operation -50 version -60 version Standby VCC supply current (RAS = CAS = WE = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode -50 version -60 version - - - - - 120 110 mA 80 70 1 mA mA 1 2, 3, 4 ICC5 ICC6 2, 4 - - 120 110 Semiconductor Group 5 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9) Input capacitance (RAS, CAS, WE, OE) Output capacitance (IO1 to IO4) AC Characteristics 5, 6 TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values -50 -60 min. max. min. max. Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Unit Note Symbol min. Limit Values max. 5 7 7 pF pF pF - - - Unit CI1 CI2 CIO tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 95 35 50 13 0 8 0 10 18 13 13 50 5 3 - - - 10k 10k - - - - 37 25 - - - 50 16 110 40 60 15 0 10 0 15 20 15 15 60 5 3 - - - 10k 10k - - - - 45 30 - - - 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 tRAC tCAC tAA tOEA 6 - - - - 50 13 25 13 - - - - 60 15 30 15 ns ns ns ns 8, 9 8, 9 8, 10 Semiconductor Group 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values -50 Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time Fast Page Mode Cycle Fast page mode cycle time CAS precharge time -60 30 0 0 0 0 0 0 0 0 15 15 - - - - - 15 15 - - - - ns ns ns ns ns ns ns ns ns ns ns 11 11 8 12 12 13 13 14 14 Unit Note min. max. min. max. tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ tDZC tDZO tCDD tODD 25 0 0 0 0 0 0 0 0 13 13 - - - - - 13 13 - - - - tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 10 - - - - - - - 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15 tRWC tRWD tCWD tAWD tOEH 131 68 31 43 13 - - - - - 150 80 35 50 15 - - - - - ns ns ns ns ns 15 15 15 tPC tCP 35 10 - - 40 10 - - ns ns Semiconductor Group 7 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values -50 Access time from CAS precharge RAS pulse width CAS precharge to RAS delay Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time CAS precharge to WE CAS-before-RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS CAS-before-RAS Counter Test Cycle CAS precharge time Test Mode Write command setup time Write command hold time -60 - 35 35 - ns ns 7 Unit Note min. max. min. max. tCPA tRAS tRHCP - 50 30 30 - 200k 60 200k ns tPRWC tCPWD 71 48 - - 80 55 - - ns ns tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns tCPT 35 - 40 - ns tWTS tWTH 10 10 - - 10 10 - - ns ns Semiconductor Group 8 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM Notes: All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with a load equivalent to 2 TTL loads and 100 pF. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.) and tOEZ (MAX.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD (MIN.) and tCPWD > tCPWD (MIN.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 9 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t RAL t CAH t CRP VIL t RAD t ASR VIH Address Row Column Row t ASC t ASR VIL t RAH t RCS t RRH t AA t OEA t RCH VIH WE VIL VIH OE VIL t DZC t DZO t ODD t CDD I/O (Inputs) VIH VIL t CAC t CLZ t OEZ Valid Data OUT Hi Z t OFF I/O (Outputs) V OL VOH Hi Z t RAC "H" or "L" SPT03025 Read Cycle Semiconductor Group 10 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t RAL t CAH t CRP VIL t RAD t ASR VIH Address Row Column Row t ASC t ASR VIL t RAH t WCS t CWL t WP t WCH t RWL VIH WE VIL VIH OE VIL t DS I/O (Inputs) t DH VIH Valid Data IN VIL Hi Z VOH I/O (Outputs) V OL "H" or "L" SPT03026 Write Cycle (Early Write) Semiconductor Group 11 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t CRP VIL t RAD t ASR VIH Address Row Column Row t RAL t CAH t ASR t ASC VIL t RAH t CWL t RWL t WP VIH WE VIL t OEH VIH OE VIL t DZO t DZC I/O (Inputs) t ODD t DS t DH VIH Valid Data VIL t CLZ t OEA VOH t OEZ I/O (Outputs) V OL Hi Z Hi Z "H" or "L" SPT03027 Write Cycle (OE Controlled Write) Semiconductor Group 12 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RWC t RAS VIH RAS VIL t CSH t RSH t RCD VIH CAS t RP t CAS t CRP VIL t ASR VIH Address Row t RAH t ASC Column t CAH t ASR Row VIL t RAD t AWD t CWD t RWD VIH WE t CWL t RWL t WP VIL t RCS t AA t OEA t OEH VIH OE VIL t DZC t DZO t DS t DH Valid Data IN I/O (Inputs) VIH VIL t CAC t CLZ t ODD t OEZ Data OUT VOH I/O (Outputs) V OL t RAC "H" or "L" SPT03028 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 13 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RASP VIH RAS VIL t PC t CAS t CP VIH CAS t RHCP t CAS t RSH t CAS t RP t CRP t RCD VIL t RAH t ASR VIH Address Row Column Column Column Row t ASC t CSH t CAH t ASC t CAH t ASC t CAH t ASR VIL t RAD t RCS VIH WE t RCH t RCS t RCS t RRH t RCH VIL t AA t OEA VIH OE t CPA t AA t OEA t CPA t AA t OEA VIL t DZC t DZO t DZC t DZO t ODD t DZC t DZO t ODD t ODD t CDD I/O (Inputs) VIH VIL t OFF t OEZ t RAC t CAC t CLZ t CAC t CLZ Valid Data OUT "H" or "L" SPT03029 t OFF t OEZ t CAC t CLZ Valid Data OUT t OFF t OEZ I/O (Outputs) V OL VOH Valid Data OUT Fast Page Mode Read Cycle Semiconductor Group 14 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RASP VIH RAS VIL t PC t CAS t RCD VIH CAS t RP t CAS t CP t RSH t CAS t CRP VIL t RAH t ASR VIH Address Row Column Column Column Row t RAL t CAH t ASC t CAH t ASC t CAH t ASR t ASC VIL t RAD t WCS t CWL t WCH t WP VIH WE t WCS t CWL t WCH t WP t WCS t RWL t CWL t WCH t WP VIL VIH OE VIL t DS I/O (Inputs) t DH Valid Data IN t DS t DH Valid Data IN Hi Z t DS t DH Valid Data IN VIH VIL VOH I/O (Outputs) V OL "H" or "L" SPT03030 Fast Page Mode Early Write Cycle Semiconductor Group 15 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RAS VIH RAS VIL t CSH t RP t CP t RCD VIH CAS t PRWC t CAS t CAS t RSH t CRP t CAS VIL t ASR VIH Address Row Column Column Column Row t RAD t RAH t ASC t CAH t CAH t ASC t ASC t RAL t CAH t ASR VIL t RWD t CWD t RCS VIH WE t CWL t CPWD t CWD t CWL t CPWD t CWD t RWL t CWL VIL t AA t AWD t OEA t OEH t WP t AWD t OEA t OEH t WP t AWD t OEA t WP t OEH VIH OE VIL t DZC t DZO VIH I/O (Inputs) V IL t CAC t RAC VOH I/O (Outputs) V OL t CLZ t CLZ t ODD t DZC Data IN t CLZ t CPA t CPA t ODD Data IN t DZC t ODD Data IN t DH t DS t OEZ Data OUT t DH t AA t DS t CAC t AA t OEZ Data OUT t DH t DS t OEZ Data OUT "H" or "L" SPT03031 Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 16 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RAS VIH RAS t RP VIL t CRP t RPC VIH CAS VIL VIH Address t ASR t RAH t ASR Row Row VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03032 RAS-Only Refresh Cycle Semiconductor Group 17 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RP VIH RAS t RAS t RP VIL t RPC t CP t CSR VIH CAS t CHR t RPC t CRP VIL t WRH t WRP VIH WE VIL VIH OE VIL t ODD I/O (Inputs) VIH VIL t CDD t OEZ I/O (Outputs) V OL VOH t OFF Hi Z "H" or "L" SPT03033 CAS-Before-RAS Refresh Cycle Semiconductor Group 18 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RP t RAS VIH RAS t RC t RP t RAS VIL t RCD VIH CAS t RSH t CHR t CRP VIL t RAD t ASC t RAH t ASR VIH Address Row Column Row t WRP t CAH t WRH t ASR VIL VIH WE t RCS t RRH VIL t AA t OEA VIH OE VIL t DZC t DZO t CDD t ODD I/O (Inputs) VIH VIL t CLZ t RAC t CAC t OEZ Valid Data OUT Hi Z t OFF VOH I/O (Outputs) V OL "H" or "L" SPT03034 Hidden Refresh Cycle (Read) Semiconductor Group 19 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RAS VIH RAS t RC t RP t RAS t RP VIL t RCD VIH CAS t RSH t CHR t CRP VIL t RAD t ASC t RAH t ASR VIH Address Row Column Row t CAH t ASR VIL t WCS t WCH t WP t WRP t WRH VIH WE VIL t DS t DH I/O (Input) VIN Valid Data VIL Hi Z VOH I/O (Output) V OL "H" or "L" SPT03035 Hidden Refresh Cycle (Early Write) Semiconductor Group 20 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM Read Cycle VIH RAS t RAS t RP VIL t CHR t CSR VIH CAS t RSH t CP t CAS t RAL t CAH t ASC t ASR Row VIL VIH Address Column VIL VIH WE t WRP t AA t CAC t OEA t RRH VIL VIH OE t WRH t RCS t RCH VIL t DZC VIH I/O (Inputs) V IL t DZO t CLZ I/O (Outputs) V t CDD t ODD t OFF t OEZ Data OUT VOH OL t WCS t WRP t RWL t CWL t WCH t WRH t DH Write Cycle VIH WE VIL VIH OE VIL t DS VIH I/O (Inputs) V IL VOH I/O (Outputs) V OL Data IN Hi Z "H" or "L" SPT03036 CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 21 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM t RC t RP VIH RAS t RAS t RP VIL t RPC t CP t CSR VIH CAS t RPC t CHR t CRP VIL t ASR VIH A0 - A9 Row Address VIL t WTH t WTS VIH WE VIL VIH OE VIL t ODD VIH t CDD t OEZ I/O1 - I/O4 (Inputs) V IL I/O1 - I/O4 (Outputs) V OL VOH t OFF Hi Z "H" or "L" SPT03037 Test Mode Entry Semiconductor Group 22 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM Test Mode As the HYB 514400BJ is organized internally as 512k x 8-bits, a test mode cycle using 8:1 compression can be used to improve test time. Note that in the 1M x 4 version the test time is reduced by 1/2 for a linear test pattern. In a test mode "write" the data from each I/O1 pin is written into eight bits simultaneously (all "1" or all "0").The I/O2 - I/O4 inputs are not used for writing in test mode. In test mode "read" each I/O output is used for indicating the test mode result. If the internal eight bits are equal, the I/O would indicate a "1". If they were not equal, the I/O would indicate a "0". Note that in test mode read" I/O1-I/O3 are always driven to "ones", i.e. all outputs will be "1" for a test mode "pass". The WCBR cycle (WE, CAS-before-RAS) puts the device into test mode. To exit from test mode, a "CAS-before-RAS refresh", "RAS-only refresh" or "Hidden refresh" can be used. Addresses A10R, A10C and A0C are don`t care during test mode. Semiconductor Group 23 1998-10-01 HYB 514400BJ-50/-60 1M x 4 DRAM Package Outlines Plastic Package, P-SOJ-26/20-2 (SMD) (Plastic small outline J-leaded) 0.8 min 2.75 3.75 -0.5 0.2 +0.1 0.25 B 0.18 B GPJ09100 B 7.75 -0.25 0.6 1.27 0.51-0.1 0.85 max 0.2 20x 15.24 0.1 0.25 A 0.3 6.80.3 8.63 -0.25 26 22 18 14 1 1 5 9 13 17.27 -0.25 A 30 o1 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 24 1.4 Index Marking Dimensions in mm 1998-10-01 |
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