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LT1169 Dual Low Noise, Picoampere Bias Current, JFET Input Op Amp
FEATURES
s s s s s s s s s s
DESCRIPTIO
Input Bias Current, Warmed Up: 20pA Max 100% Tested Low Voltage Noise: 8nV/Hz Max S8 and N8 Package Standard Pinout Very Low Input Capacitance: 1.5pF Voltage Gain: 1.2 Million Min Offset Voltage: 2mV Max Input Resistance: 1013 Gain-Bandwidth Product: 5.3MHz Typ Guaranteed Specifications with 5V Supplies Guaranteed Matching Specifications
APPLICATI
s s s s
S
s s
Photocurrent Amplifiers Hydrophone Amplifiers High Sensitivity Piezoelectric Accelerometers Low Voltage and Current Noise Instrumentation Amplifier Front Ends Two and Three Op Amp Instrumentation Amplifiers Active Filters
The LT1169 achieves a new standard of excellence in noise performance for a dual JFET op amp. For the first time low voltage noise (6nV/Hz) is simultaneously offered with extremely low current noise (1fA/Hz), providing the lowest total noise for high impedance transducer applications. Unlike most JFET op amps, the very low input bias current (5pA Typ) is maintained over the entire common mode range which results in an extremely high input resistance (1013). When combined with a very low input capacitance (1.5pF) an extremely high input impedance results, making the LT1169 the first choice for amplifying low level signals from high impedance transducers. The low input capacitance also assures high gain linearity when buffering AC signals from high impedance transducers. The LT1169 is unconditionally stable for gains of 1 or more, even with 1000pF capacitive loads. Other key features are 0.6mV VOS and a voltage gain over 4 million. Each individual amplifier is 100% tested for voltage noise, slew rate (4.2V/s), and gain-bandwidth product (5.3MHz). The LT1169 is offered in the S8 and N8 packages. A full set of matching specifications are provided for precision instrumentation amplifier front ends. Specifications at 5V supply operation are also provided. For an even lower voltage noise please see the LT1113 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
Low Noise Light Sensor with DC Servo
C1 2pF
TOTAL 1kHz VOLTAGE NOISE DENSITY (nV/ Hz)
10k
D2 1N914 CD D1 1N914 2N3904 HAMAMATSU S1336-5BK (908) 231-0960 V- R5 10k R4 1k
R3 1k
7
1/2 LT1169 5
4 -V R2C2 > C1R1 CD = PARASITIC PHOTODIODE CAPACITANCE VOUT = 100mV/WATT FOR 200nm WAVE LENGTH 330mV/WATT FOR 633nm WAVE LENGTH
-
+
+
3
-
2
R1 1M 1 C2 0.022F +V 8 VOUT
1k
1/2 LT1169
100
6
R2 100k
10
1 100
LT1169 * TA01
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1kHz Output Voltage Noise Density vs Source Resistance
- +
RSOURCE VN
UO
UO
VN SOURCE RESISTANCE ONLY 1k TA = 25C VS = 15V
10k 100k 1M 10M 100M 1G SOURCE RESISTANCE ()
VN = (VOP AMP)2 + 4kTRS + 2qIBRS2
LT1169 * TA02
1
LT1169 ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW OUT A 1 -IN A 2 +IN A 3 V
-
Supply Voltage - 55C to 105C ............................................... 20V 105C to 125C ............................................... 16V Differential Input Voltage ...................................... 40V Input Voltage (Equal to Supply Voltage) ............... 20V Output Short-Circuit Duration......................... Indefinite Operating Temperature Range ............... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec) ................ 300C
8
A B
V+
ORDER PART NUMBER LT1169CN8 LT1169CS8 S8 PART MARKING 1169
7 OUT B 6 -IN B 5 +IN B
4
N8 PACKAGE 8-LEAD PDIP
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 80C/W (N8) TJMAX = 160C, JA = 190C/W (S8)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS VS = 15V, VCM = 0V, TA = 25C, unless otherwise noted.
SYMBOL VOS IOS IB en PARAMETER Input Offset Voltage VS = 5V Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density in RIN Input Noise Current Density Input Resistance Differential Mode Common Mode Input Capacitance VS = 5V Input Voltage Range (Note 4) Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Slew Rate Gain-Bandwidth Product Channel Separation IS VOS IB
+
CONDITIONS (Note 1)
MIN
TYP 0.60 0.65 2.5 0.7 4.0 1.5 2.4 17 6 1 1014 1013 1.5 2.0
MAX 2.0 2.2 15 4 20 5
UNITS mV mV pA pA pA pA VP-P nV/Hz nV/Hz fA/Hz pF pF V V dB dB V/mV V/mV V V V/s MHz dB
Warmed Up (Note 2) TJ = 25C (Note 5) Warmed Up (Note 2) TJ = 25C (Note 5) 0.1Hz to 10Hz fO = 10Hz fO = 1000Hz fO = 10Hz, fO = 1kHz (Note 3)
8
VCM = -10V to 13V
CIN VCM CMRR PSRR AVOL VOUT SR GBW
13.0 -10.5 VCM = -10V to 13V VS = 4.5V to 20V VO = 12V, RL = 10k VO = 10V, RL = 1k RL = 10k RL = 1k RL 2k (Note 6) fO = 100kHz fO = 10Hz, VO = 10V, RL = 1k VS = 5V 82 83 1000 500 13.0 12.0 2.4 3.3
13.5 -11.0 95 98 4500 3000 13.8 13.0 4.2 5.3 126 5.3 5.3 0.8 3 6.50 6.45 3.5 20
Supply Current per Amplifier Offset Voltage Match Noninverting Bias Current Match Common Mode Rejection Match Power Supply Rejection Match Warmed Up (Note 2) (Note 8) (Note 8) 78 80
CMRR PSRR
94 95
2
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mA mA mV pA dB dB
W
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U
WW
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LT1169
ELECTRICAL CHARACTERISTICS
SYMBOL VOS VOS Temp IOS IB VCM CMRR PSRR A VOL V OUT SR GBW IS VOS IB
+
VS = 15V, VCM = 0V, 0C TA 70C, (Note 9), unless otherwise noted.
MIN
q q q q q q q
PARAMETER Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Input Bias Current Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Slew Rate Gain-Bandwidth Product Supply Current per Amplifier
CONDITIONS (Note 1) VS = 5V (Note 5)
TYP 0.7 0.8 20 10 180
MAX 3.2 3.4 50 50 400
UNITS mV mV V/C pA pA V V dB dB V/mV V/mV V V V/s MHz
12.9 -10.0 79 81 800 400 12.5 11.5 1.9 3
13.4 -10.8 94 97 3400 2400 13.5 12.7 4 4.2 5.3 5.3 1.5 5.5 6.55 6.50 5 50
VCM = -10V to 12.9V VS = 4.5V to 20V VO = 12V, RL = 10k VO = 10V, RL = 1k R L = 10k R L = 1k R L 2k (Note 6) f O = 100kHz VS = 5V
q q q q q q q q q q q q
mA mA mV pA dB dB
Offset Voltage Match Noninverting Bias Current Match Common Mode Rejection Match Power Supply Rejection Match (Note 8) (Note 8)
CMRR PSRR
q q
74 77
93 93
VS = 15V, VCM = 0V, - 40C TA 85C, (Note 7), unless otherwise noted.
SYMBOL VOS VOS Temp IOS IB VCM CMRR PSRR A VOL V OUT SR GBW IS PARAMETER Input Offset Voltage VS = 5V Average Input Offset Voltage Drift Input Offset Current Input Bias Current Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Slew Rate Gain-Bandwidth Product Supply Current per Amplifier VS = 5V VCM = -10V to 12.6V VS = 4.5V to 20V VO = 12V, RL = 10k VO = 10V, RL = 1k RL = 10k RL = 1k RL 2k fO = 100kHz CONDITIONS (Note 1)
q q q q q q q q q q q q q q q q q
MIN
TYP 0.8 0.9 20 30 320
MAX 3.8 4.0 50 200 1200
UNITS mV mV V/C pA pA V V dB dB V/mV V/mV V V V/s MHz
12.6 -10.0 78 79 750 300 12.5 11.3 1.8 2.7
13.0 -10.5 93 96 3000 2000 12.5 12.0 3.8 4 5.30 5.25 6.55 6.50
mA mA
3
LT1169
ELECTRICAL CHARACTERISTICS VS = 15V, VCM = 0V, - 40C TA 85C, (Note 7), unless otherwise noted.
SYMBOL VOS IB+ CMRR PSRR PARAMETER Offset Voltage Match Noninverting Bias Current Match Common Mode Rejection Match Power Supply Rejection Match (Note 8) (Note 8) CONDITIONS (Note 1)
q q q q
MIN
TYP 1.8 10
MAX 6 180
UNITS mV pA dB dB
73 75
93 92
The q denotes specifications which apply over the full operating temperature range. Note 1: Typical parameters are defined as the 60% yield of parameter distributions of individual amplifiers, i.e., out of 100 LT1169s (200 op amps) typically 120 op amps will be better than the indicated specification. Note 2: IB and IOS readings are extrapolated to a warmed-up temperature from 25C measurements and 45C characterization data. Note 3: Current noise is calculated from the formula: in = (2qIB)1/2 where q = 1.6 x 10 -19 coulomb. The noise of source resistors up to 200M swamps the contribution of current noise. Note 4: Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of 2.8mV. Note 5: This parameter is not 100% tested.
Note 6: Slew rate is measured in AV = -1; input signal is 7.5V, output measured at 2.5V. Note 7: The LT1169 is designed, characterized and expected to meet these extended temperature limits, but is not tested at - 40C and 85C. Guaranteed I grade parts are available; consult factory. Note 8: CMRR and PSRR are defined as follows: (1) CMRR and PSRR are measured in V/V on the individual amplifiers. (2) The difference is calculated between the matching sides in V/V. (3) The result is converted to dB. Note 9: The LT1169 is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed-up chip temperature can be 10C to 50C higher than the ambient temperature.
TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Voltage Noise
50 TA = 25C VS = 15V 510 OP AMPS TESTED
VOLTAGE NOISE (1V/DIV)
40
30
RMS VOLTAGE NOISE (nV/Hz)
PERCENT OF UNITS (%)
0
2
4 6 TIME (SEC)
4
UW
8 10
LT1169 * TPC01
1kHz Input Noise Voltage Distribution
100
Voltage Noise vs Frequency
TA = 25C VS = 15V
10 TYPICAL 1/f CORNER 60Hz
20
10
0 4.2 4.6 5.0 5.4 5.8 6.2 6.6 7.0 7.4 7.8 8.2 INPUT VOLTAGE NOISE (nV/Hz)
LT1169 * TPC02
1 1
10
100 1k FREQUENCY (Hz)
10k
LT1169 * TPC03
LT1169
TYPICAL PERFOR A CE CHARACTERISTICS
Voltage Noise vs Chip Temperature
10 30n 10n 3n 1n 300p 100p 30p 10p 3p 1p 0.3p 100 125 0 25 75 100 50 TEMPERATURE (C) 125 OFFSET CURRENT BIAS CURRENT
INPUT BIAS AND OFFSET CURRENTS (pA)
INPUT BIAS AND OFFSET CURRENTS (A)
VOLTAGE NOISE (AT 1kHz) (nV/Hz)
VS = 15V 9 8 7 6 5 4 3 2 -75 -50 -25 0 25 50 75 TEMPERATURE (C)
Common Mode Limit vs Temperature
V+ 0
COMMON MODE REJECTION RATIO (dB)
-0.5
POWER SUPPLY REJECTION RATIO (dB)
COMMON MODE LIMIT (V) REFERRED TO POWER SUPPLY
-1.0 -1.5 -2.0
V + = 5V TO 20V
3.0 2.5 2.0 1.5 V - = - 5V TO - 20V
V - +1.0 -60
-20
60 100 20 TEMPERATURE (C)
Voltage Gain vs Frequency
180 TA = 25C VS = 15V 140
VOLTAGE GAIN (V/V)
VOLTAGE GAIN (dB)
VOLTAGE GAIN (dB)
100
60
20
-20 0.01
1
10k 100 FREQUENCY (Hz)
UW
LT1169 * TPC04
Input Bias and Offset Currents vs Chip Temperature
10
Input Bias and Offset Currents Over the Common Mode Range
8 6 4 2 0 -2 -4 -6 -8 -10 -15 10 -10 0 5 -5 COMMON MODE RANGE (V) 15 BIAS CURRENT OFFSET CURRENT TA = 25C VS = 15V
VS = 15V VCM = -10 TO 13V
LT1169 * TPC05*
LT1169 * TPC06
Common Mode Rejection Ratio vs Frequency
120 100 80 60 40 20 0 TA = 25C VS = 15V
Power Supply Rejection Ratio vs Frequency
120 TA = 25C 100 +PSRR 80 -PSRR 60 40 20 0
140
1k
10k
100k 1M FREQUENCY (Hz)
10M
LT1169 * TPC08
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
LT1169 * TPC07
LT1169 * TPC09
Voltage Gain vs Chip Temperature
10 9 8 7 6 5 4 3 2 1 RL = 1k RL =10k VS = 15V VO = 10V, RL = 1k VO = 12V, RL = 10k
50 40 30 20
Gain and Phase Shift vs Frequency
TA = 25C VS = 15V CL = 10pF 60 80
PHASE SHIFT (DEG)
100 120 PHASE 140 GAIN 160 180 100
LT1169 * TPC12
10 0 -10
1M
100M
0 -75 -50 -25 0 25 50 75 CHIP TEMPERATURE (C)
100 125
LT1169 * TPC11
0.1
1 10 FREQUENCY (MHz)
LT1169 * TPC10
5
LT1169
TYPICAL PERFOR A CE CHARACTERISTICS
Small-Signal Transient Response Large-Signal Transient Response
6
SUPPLY CURRENT PER AMPLIFIER (mA)
20mV/DIV
5V/DIV
AV = 1 CL = 10pF VS = 15V, 5V
2s/DIV
Output Voltage Swing vs Load Current
V + - 0.8 -1.0 OUTPUT VOLTAGE SWING (V) -1.2 - 1.4 -1.6 1.4 1.2 1.0 0.8 0.6 -55C 25C VS = 5V TO 20V 25C -55C 125C
SLEW RATE (V/s)
OVERSHOOT (%)
125C V - +0.4 -10 -8 -6 -4 -2 0 2 4 6 8 10 ISINK ISOURCE OUTPUT CURRENT (mA)
LT1169 * TPC16
Distribution of Offset Voltage Drift with Temperature
50
CHANGE IN OFFSET VOLTAGE (V)
VS = 15V 188 OP AMPS
CHANNEL SEPARATION (dB)
40
PERCENT OF UNITS
30
20
10
0 -50 -40 -30 -20 -10 0 10 20 30 OFFSET VOLTAGE DRIFT WITH TEMPERATURE (V/C)
LT1169 * TPC19
6
UW
LT1169 * TPC13
Supply Current vs Supply Voltage
25C -55C 5 125C
AV = 1 CL = 10pF VS = 15V
5s/DIV
LT1169 * TPC14
4
0
10 15 5 SUPPLY VOLTAGE (V)
20
LT1169 * TPC15
Capacitive Load Handling
50 VS = 15V TA = 25C RL 10k VO = 100mVP-P AV = +10, RF = 10k, CF = 20pF
6 5
Slew Rate and Gain-Bandwidth Product vs Temperature
GAIN-BANDWIDTH PRODUCT (fO = 100kHz)(MHz)
12 10 SLEW RATE 4 GAIN-BANDWIDTH 3 2 1 6 4 2 0 100 125
LT1169 * TPC18
40
8
30
20 AV = 1 10 AV = 10 0 0.1 1 100 1000 10 CAPACITIVE LOAD (pF) 10000
0 25 50 75 -75 -50 -25 0 TEMPERATURE (C)
LT1169 * TPC17
Warm-Up Drift
1000 TA = 25C VS = 15V N8 PACKAGE
140 120 100 80 60 40 20
Channel Separation vs Frequency
800
LIMITED BY THERMAL INTERACTION
600
400
LIMITED BY PIN-TO-PIN CAPACITANCE TA = 25C VS = 15V RL = 1k VO = 10VP-P 10 100 100k 10k 1k FREQUENCY (Hz) 1M 10M
200
0
0
5 2 3 4 1 TIME AFTER POWER ON (MIN)
6
0
LT1169 * TPC20
LT1169 * TPC21
LT1169
TYPICAL PERFOR A CE CHARACTERISTICS
THD and Noise vs Frequency for Noninverting Gain
TOTAL HARMONIC DISTORTION + NOISE (%) ZL = 2k 15pF VO = 20VP-P AV = 1, 10, 100 MEASUREMENT BANDWIDTH = 10Hz TO 80kHz AV = 100 TOTAL HARMONIC DISTORTION + NOISE (%) 1 1 ZL = 2k15pF VO = 20VP-P AV = -1, -10, -100 MEASUREMENT BANDWIDTH = 10Hz TO 80kHz AV = -100 0.01 AV = -10 0.001 AV = -1 NOISE FLOOR 0.0001 20 100 1k FREQUENCY (Hz) 10k 20k
LT1169 * TPC23
0.1
0.01
0.001
0.0001 20
100
THD and Noise vs Output Amplitude for Inverting Gain
TOTAL HARMONIC DISTORTION + NOISE (%)
ZL = 2k 15pF fO = 1kHz AV = -1, -10, -100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz AV = -100 AV = -10 0.001 AV = -1 NOISE FLOOR 0.0001 0.3 1 10 OUTPUT SWING (VP-P) 30
LT1169 * TPC24
INTERMODULATION DISTORTION (AT 1kHz)(%)
TOTAL HARMONIC DISTORTION + NOISE (%)
1
0.1
0.01
APPLICATI
S I FOR ATIO
LT1169 vs the Competition With improved noise performance, the LT1169 dual in the plastic DIP directly replaces such JFET op amps as the OPA2111, OPA2604, OP215, and the AD822. The combination of low current and voltage noise of the LT1169 allows it to surpass most dual and single JFET op amps. The LT1169 can replace many of the lowest noise bipolar amps that are used in amplifying low level signals from high impedance transducers. The best bipolar op amps will eventually lose out to the LT1169 when transducer impedance increases due to higher current noise.
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THD and Noise vs Frequency for Inverting Gain
0.1
AV = 10
AV = 1
NOISE FLOOR 1k FREQUENCY (Hz) 10k 20k
LT1169 * TPC22
THD and Noise vs Output Amplitude for Noninverting Gain
1 ZL = 2k15pF fO = 1kHz AV = 1, 10, 100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz AV = 100 0.01 AV = 10 0.001 AV = 1 NOISE FLOOR 0.0001 0.3 1 10 OUTPUT SWING (VP-P) 30
LT1169 * TPC25
CCIF IMD Test (Equal Amplitude Tones at 13kHz, 14kHz)*
1 TA = 25C VS = 15V RL = 2k 0.1
0.1
0.01
AV = 10
0.001
0.0001 0.02
0.1 1 OUTPUT SWING (VP-P)
10
30
LT1169 * TPC26
* SEE LT1115 DATA SHEET FOR DEFINITION OF CCIF TESTING
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The extremely high input impedance (1013) assures that the input bias current is almost constant over the entire common mode range. Figure 1 shows how the LT1169 stands up to the competition. Unlike the competition, as the input voltage is swept across the entire common mode range the input bias current of the LT1169 hardly changes. As a result the current noise does not degrade. This makes the LT1169 the best choice in applications where an amplifier has to buffer signals from a high impedance transducer.
7
LT1169
APPLICATI
100 80
S I FOR ATIO
CURRENT NOISE = 2qIB
INPUT BIAS CURRENT (pA)
60 40 20 0 -20 -40 -60 -80 AD822 OP215 LT1169
-100 -15
10 -10 0 5 -5 COMMON MODE RANGE (V)
15
LT1169 * F01
Figure 1. Comparison of LT1169, OP215, and AD822 Input Bias Current vs Common Mode Range
Amplifying Signals from High Impedance Transducers The low voltage and current noise offered by the LT1169 makes it useful in a wide range of applications, especially where high impedance, capacitive transducers are used such as hydrophones, precision accelerometers, and photodiodes. The total output noise in such a system is the gain times the RMS sum of the op amp's input referred voltage noise, the thermal noise of the transducer, and the op amp's input bias current noise times the transducer impedance. Figure 2 shows total input voltage noise versus source resistance. In a low source resistance (< 5k) application the op amp voltage noise will dominate
10k
CS
LT1124*
RS VO CS
INPUT NOISE VOLTAGE (nV/Hz)
1k
LT1169*
100
RS
LT1124 LT1169 10 LT1169 LT1124 RESISTOR NOISE ONLY 1k 10k 100k 1M 10M 100M SOURCE RESISTANCE () 1G
1 100
LT1169 * F02
SOURCE RESISTANCE = 2RS = R * PLUS RESISTOR PLUS RESISTOR 1000pF CAPACITOR Vn = AV Vn2(OP AMP) + 4kTR + 2qIBR2
Figure 2. Comparison of LT1169 and LT1124 Total Output 1kHz Voltage Noise vs Source Resistance
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the total noise. This means the LT1169 is superior to most dual JFET op amps. Only the lowest noise bipolar op amps have the advantage at low source resistances. As the source resistance increases from 5k to 50k, the LT1169 will match the best bipolar op amps for noise performance, since the thermal noise of the transducer (4kTR) begins to dominate the total noise. A further increase in source resistance, above 50k, is where the op amp's current noise component (2qIBR2) will eventually dominate the total noise. At these high source resistances, the LT1169 will out perform the lowest noise bipolar op amps due to the inherently low current noise of FET input op amps. Clearly, the LT1169 will extend the range of high impedance transducers that can be used for high signalto-noise ratios. This makes the LT1169 the best choice for high impedance, capacitive transducers. Optimization Techniques for Charge Amplifiers The high input impedance JFET front end makes the LT1169 suitable in applications where very high charge sensitivity is required. Figure 3 illustrates the LT1169 in its inverting and noninverting modes of operation. A charge amplifier is shown in the inverting mode example; the gain depends on the principal of charge conservation at the input of the LT1169. The charge across the transducer capacitance CS is transferred to the feedback capacitor CF resulting in a change in voltage dV, which is equal to dQ/CF. The gain therefore is 1 + CF/CS. For unity-gain, the CF should equal the transducer capacitance plus the input capacitance of the LT1169 and RF should equal RS. In the noninverting mode example, the transducer current is converted to a change in voltage by the transducer capacitance, CS. This voltage is then buffered by the LT1169 with a gain of 1 + R1/R2. A DC path is provided by RS, which is either the transducer impedance or an external resistor. Since RS is usually several orders of magnitude greater than the parallel combination of R1 and R2, RB is added to balance the DC offset caused by the noninverting input bias current and RS. The input bias currents, although small at room temperature, can create significant errors over increasing temperature, especially with transducer resistances of up to 1000M or more. The optimum value for RB is determined by equating the thermal noise (4kTRS) to the current noise (2qIB) times RS2. Solving for RS results in RB = RS = 2VT/IB. A parallel
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+
-
LT1169
APPLICATI
S I FOR ATIO
RF CF
CS
RS
OUTPUT
R1
TRANSDUCER RB
CB = CF CS RB = RF RS CB dQ dV Q = CV; =I=C dt dt
CS
RS
TRANSDUCER
Figure 3. Inverting and Noninverting Gain Configurations Input: 5.2 Sine Wave LT1169 Output OPA2111 Output
LT1169 * F04a
LT1169 * F04b
Figure 4. Voltage Follower with Input Exceeding the Common Mode Range (VS = 5V)
capacitor CB, is used to cancel the phase shift caused by the op amp input capacitance and RB. Reduced Power Supply Operation To take full advantage of a wide input common-mode range, the LT1169 was designed to eliminate phase reversal. Referring to the photographs in Figure 4, the LT1169 is shown operating in the follower mode (AV = 1) at 5V supplies with the input swinging 5.2V. The output of the LT1169 clips cleanly and recovers with no phase reversal, unlike the competition as shown by the last photograph. This has the benefit of preventing lockup in servo systems and minimizing distortion components. The effect of input and output overdrive on one amplifier has no effect on the other, as each amplifier is biased independently. Advantages of Matched Dual Op Amps In many applications the performance of a system depends on the matching between two operational amplifiers rather than the individual characteristics of the two op
amps. Two or three op amp instrumentation amplifiers, tracking voltage references and low drift active filters are some of the circuits requiring matching between two op amps. The well-known triple op amp configuration in Figure 5 illustrates these concepts. Output offset is a function of the difference between the two halves of the LT1169. This error cancellation principle holds for a considerable number of input referred parameters in addition to offset voltage and bias current. Input bias current will be the average of the two noninverting input currents (IB+). The difference between these two currents (I B+) is the offset current of the instrumentation amplifier. Common-mode and power supply rejections will be dependent only on the match between the two amplifiers (assuming perfect resistor matching). The concepts of common mode and power supply rejection ratio match (CMRR and PSRR) are best demonstrated with a numerical example:
+
-
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R2 CB RB OUTPUT CB C S RB = RS RS > R1 OR R2
LT1169 * F03
LT1169 * F04c
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+ -
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9
LT1169
APPLICATI
15V IN- 3 1/2 LT1169 IC1 2 - 4 -15V
S I FOR ATIO
R4 1k R1 1k R2 200 R6 10k C1 30pF
+
8 1
GAIN = 100 BANDWIDTH = 330kHz INPUT REFERRED NOISE = 8.7nV/ z AT 1kHz H WIDEBAND NOISE DC TO 330kHz = 5.3VRMS CL 0.01F
Figure 5. Three Op Amp Instrumentation Amplifier
Assume CMRRA = 50V/V or 86dB, and CMRRB = 39V/V or 88dB, then CMRR = 11V/V or 99dB; if CMRRB = - 39V/V which is still 88dB, then CMRR = 89V/V or 81dB By specifying and guaranteeing all of these matching parameters, the LT1169 can significantly improve the performance of matching-dependent circuits. Typical performance of the instrumentation amplifier: Input offset voltage = 0.8mV Input bias current = 4pA
Figure 6
TYPICAL APPLICATIONS N
Unity-Gain Buffer with Extended Load Capacitance Drive Capability
R2 1k C1
I1 PD1
Light Balance Detection Circuit
R1 1M C1 3pF TO 5pF
1/2 LT1169 VIN
VOUT CL
LT1169 * TA03
I2 PD2
C1 = CL 0.1F OUTPUT SHORT CIRCUIT CURRENT ( 30mA) WILL LIMIT THE RATE AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS dV (I = C dt )
VOUT = 1M x (I1 - I2) PD1,PD2 = HAMAMATSU S1336-5BK WHEN EQUAL LIGHT ENTERS PHOTODIODES, VOUT < 3mV.
10
+
-
R1 33
+
RS
CS
-
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+
-
+
IN+
5
1/2 LT1169 IC1
7
R7 10k
+
-
6
R3 1k
R5 1k
3
-
2
1/2 LT1169 IC2
1
LT1169 * F05
U
Input offset current = 3pA Input resistance = 1013 Input noise = 3.4VP-P High Speed Operation The low noise performance of the LT1169 was achieved by enlarging the input JFET differential pair to maximize the first stage gain. Enlarging the JFET geometry also increases the parasitic gate capacitance, which if left unchecked, can result in increased overshoot and ringing. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance and capacitance (RS,CS), and the amplifier input capacitance (CIN = 1.5pF). In closed-loop gain configurations with RS and RF in the M range (Figure 6), this pole can create excess phase shift and even oscillation. A small capacitor (CF) in parallel with RF eliminates this problem. With RS(CS + CIN) = RFCF, the effect of the feedback pole is completely removed.
CF
OUTPUT CL
W
U
UO
RF
CIN
OUTPUT
LT1169 * F06
1/2 LT1169
VOUT
LT1169 * TA04
LT1169
TYPICAL APPLICATIONS N
Low Noise Hydrophone Amplifier with DC Servo Accelerometer Amplifier with DC Servo
C1 1250pF
R2 C1* 200
CT HYDROPHONE
1/2 LT1169
LT1169 * TA05
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 - 0.325 (7.620 - 8.255)
0.045 - 0.065 (1.143 - 1.651)
0.130 0.005 (3.302 0.127)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076)
(
+0.035 0.325 -0.015 +0.889 8.255 -0.381
)
0.100 0.010 (2.540 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 8 0.189 - 0.197* (4.801 - 5.004) 7 6 5
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
+
DC OUTPUT 2.5mV FOR TA < 70C OUTPUT VOLTAGE NOISE = 128nV/Hz AT 1kHz (GAIN = 20) C1 CT 100pF TO 5000pF; R4C2 > R8CT; *OPTIONAL
3
-
R7 1M
5
R5 1M
5V TO 15V
ACCELEROMETER B & K MODEL 4381 OR EQUIVALENT (800) 442-1030
2
8 1
1/2 LT1169
R4C2 = R5C3 > R1 (1 + R2/R3) C1 OUTPUT = 0.8mV/pC* = 8.0mV/g** 4 DC OUTPUT 1.9mV -5V TO -15V OUTPUT NOISE = 8nV/H AT 1kHz z *PICOCOULOMBS **g = EARTH'S GRAVITATIONAL CONSTANT
LT1169 * TA07
8
0.255 0.015* (6.477 0.381)
1
1
2
+
R6 100k
7
-
R8 100M
6
R4 1M
7
1/2 LT1169
5
-
-5V TO -15V
+
U
+
3
-
R1* 100M
R3 3.9k
5V TO 15V 2 8 1 C2 0.47F OUTPUT
R1 100M R3 2k C2 2F R4 20M R5 20M C3 2F OUTPUT R2 18k
1/2 LT1169 4
U
6
0.400* (10.160) MAX 7 6 5
2
3
4
N8 1197
SO8 0996
3
4
11
LT1169
TYPICAL APPLICATIONS N
10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple)
R2 237k R1 237k VIN C2 100nF R3 249k 15V 2 8 C1 33nF 1
1/2 LT1169
-15V LT1169 * TA08 TYPICAL OFFSET 0.8mV 1% TOLERANCES FOR VIN = 10VP-P, VOUT = -121dB AT f > 330Hz = - 6dB AT f = 16.3Hz LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS
Paralleling Amplifiers to Reduce Voltage Noise
3
+
A1 1/2 LT1169 1
1.6k
2 91
-
3k 10k
3
+
A2 1/2 LT1169 1
15V
2 91
-
3k 15V 5
5
+ -
8 7 1.6k
6
An 1/2 LT1169 4 -15V 3k
91
1. ASSUME VOLTAGE NOISE OF LT1169 AND 51 SOURCE RESISTOR = 6.1nV/Hz 2. GAIN WITH n LT1169s IN PARALLEL = n x 200 3. OUTPUT NOISE = n x 200 x 6.1nV/ z H OUTPUT NOISE 6.1 4. INPUT REFERRED NOISE = = nV/ z H n x 200 n 5. NOISE CURRENT AT INPUT INCREASES n TIMES 2.1V 6. IF n = 5, GAIN = 1000, BANDWIDTH = 110kHz, RMS NOISE, DC TO 1MHz = = 1.0V 5
LT1169 * TA06
RELATED PARTS
PART NUMBER LT1113 LT1462 LT1464 DESCRIPTION Lowest Noise Dual JFET Op Amp Micro Power Dual JFET Op Amp Low Power Dual JFET Op Amp COMMENTS 4.5nV/Hz Voltage Noise 3.0pA IB, 45A ISUPPLY 3.0pA (Max) Input Bias Current
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
+
-
1.6k
6
8 7 OUTPUT
1/2 LT1169 4 -15V
+
+
3
4
C4 330nF
5
-
-
U
R5 154k R4 154k R6 249k 6 C3 10nF 7 VOUT
1/2 LT1169
1169fa LT/TP 0198 REV A 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1994

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