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Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
FEATURES
* 'Trench' technology * Very low on-state resistance * Fast switching * Low thermal resistance * Logic level compatible
PSMN004-55W
QUICK REFERENCE DATA
SYMBOL
d
VDSS = 55 V ID = 100 A RDS(ON) 4.2 m (VGS = 10 V) RDS(ON) 4.5 m (VGS = 5 V)
g
s
RDS(ON) 5 m (VGS = 4.5 V) SOT429 (TO247)
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:* d.c. to d.c. converters * switched mode power supplies The PSMN004-55W is supplied in the SOT429 (TO247) conventional leaded package.
PINNING
PIN 1 2 3 tab gate drain source drain DESCRIPTION
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tj 150 C Tmb = 25 C; VGS = 5 V Tmb = 100 C; VGS = 5 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 15 20 1001 1001 300 300 175 UNIT V V V V A A A W C
1 Maximum continuous current limited by package. October 1999 1 Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 100 A; tp = 100 s; Tj prior to avalanche = 25C; VDD 25 V; RGS = 50 ; VGS = 5 V; refer to fig:15
PSMN004-55W
MIN. -
MAX. 357
UNIT mJ
IAS
-
100
A
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. in free air TYP. MAX. UNIT 45 0.5 K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175C Gate-source leakage current VGS = 10 V; VDS = 0 V; Zero gate voltage drain VDS = 55 V; VGS = 0 V; current Tj = 175C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 100 A; VDD = 44 V; VGS = 5 V MIN. 55 42 1 0.5 TYP. MAX. UNIT 1.5 3.2 3.6 3.8 6.2 0.02 0.05 226 36 106 26 118 848 336 3.5 4.5 7.5 13 1900 1250 2 2.3 4.2 4.5 5 9.5 100 10 500 V V V V V m m m m nA A A nC nC nC ns ns ns ns nH nH nH nF pF pF
IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss
VDD = 30 V; RD = 1.2 ; VGS = 10 V; RG = 5.6 Resistive load Measured tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
October 1999
2
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 20 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 20 V -
PSMN004-55W
TYP. MAX. UNIT 0.78 0.92 150 0.7 100 300 1.2 A A V ns C
October 1999
3
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
PSMN004-55W
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
1
Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2
0.1
0.1 0.05 0.02 P D tp D = tp/T
0.01
single pulse 0.001 1E-06
T 1E-03 1E-02 1E-01 1E+00
1E-05
1E-04
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A) 10 V VGS = 10V
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
100 90 80 70 60 50 40 30 20 10 0 0
Tj = 25 C
2.5 V
2.4 V 2.3 V 2.2 V 2.1 V 2V
0.2
0.4
0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS)
1000
0.02 tp = 10 us 100 us 0.018 0.016 0.014 1 ms 10 ms 100 ms 0.012 0.01 D.C.
Drain-Source On Resistance, RDS(on) (Ohms) 2V 2.1 V 2.2 V 2.3 V 2.4 V 2.5 V Tj = 25 C
100
10
0.008 0.006 0.004 0.002 5V VGS = 10V
1 1 10 Drain-Source Voltage, VDS (V) 100
0 0 10 20 30 40 50 60 Drain Current, ID (A) 70 80 90 100
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID)
October 1999
4
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
PSMN004-55W
Drain current, ID (A) 100 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Gate-source voltage, VGS (V) Tj = 25 C VDS > ID X RDS(ON)
2.25 2 1.75 1.5 1.25 1 0.75
175 C
Threshold Voltage, VGS(TO) (V) maximum
typical minimum
0.5 0.25 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics. ID = f(VGS)
Transconductance, gfs (S) VDS > ID X RDS(ON) Tj = 25 C
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
220 200 180 160 140 120 100 80 60 40 20 0
1.0E-01
Drain current, ID (A)
1.0E-02
175 C
1.0E-03
minimum typical
1.0E-04
maximum
1.0E-05
1.0E-06
0 10 20 30 40 50 60 70 Drain current, ID (A) 80 90 100
0
0.5
1 1.5 2 Gate-source voltage, VGS (V)
2.5
3
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
Normalised On-state Resistance 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C)
100000 Capacitances, Ciss, Coss, Crss (pF)
Ciss 10000 Coss 1000 Crss
100 0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
October 1999
5
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
PSMN004-55W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Gate-source voltage, VGS (V) ID = 100 A Tj = 25 C 1000
Maximum Avalanche Current, IAS (A)
100 VDD = 11 V VDD = 44 V 10 Tj prior to avalanche = 150 C
25 C
0
40
80
120
160 200 240 280 Gate charge, QG (nC)
320
360
400
440
1 0.001
0.01
0.1 Avalanche time, tAV (ms)
1
10
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load
Source-Drain Diode Current, IF (A) 100 90 80 70 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) 175 C Tj = 25 C VGS = 0 V
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
October 1999
6
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
MECHANICAL DATA
Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247
PSMN004-55W
SOT429
E P
A A1 q S
R D Y
L1(1) Q b2 L
1
2 b b1 e e
3 wM c
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 5.3 4.7 A1 1.9 1.7 b 1.2 0.9 b1 2.2 1.8 b2 3.2 2.8 c 0.9 0.6 D 21 20 E 16 15 e 5.45 L 16 15 L1
(1)
P 3.7 3.3
Q 2.6 2.4
q 5.3
R 3.5 3.3
S 7.5 7.1
w 0.4
Y 15.7 15.3
6 4
17 13
4.0 3.6
Note 1. Tinning of terminals are uncontrolled within zone L1. OUTLINE VERSION SOT429 REFERENCES IEC JEDEC TO-247 EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07 99-08-04
Fig.16. SOT429; pin 2 connected to mounting base
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8".
October 1999
7
Rev 1.100
Philips Semiconductors
Product specification
N-channel logic level TrenchMOSTM transistor
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PSMN004-55W
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
October 1999
8
Rev 1.100

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