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PRELIMINARY
Z90110/120/130 CP95TEL1300
PRELIMINARY CUSTOMERPROCUREMENTSPECIFICATION
Z90110/120/130
40-PINLOW-COSTDIGITAL TELEVISIONCONTROLLER
FEATURES
Part Z90110 Z90120 Z90130
n
ROM (KB) 4 6 8
RAM* (Kbyte) 236 236 236
Speed (MHz) 4 4 4
n n
On-Screen Display (OSD) Logic Circuits One 14-Bit and Three 6-Bit Pulse Width Modulator (PWM) Circuits 24 Input/Output Lines Program Memory, Video RAM, and Register File Address Spaces Two On-Chip Counter/Timers
*General-Purpose
n n n n n
40-Pin DIP Package
n
4.5V to 5.5V Operating Range 0C to +70C Temperature Range Low-Power Consumption
n
GENERAL DESCRIPTION
The Z901XX 40-pin Digital Television Controller is a costeffective member of the Z8 (R) single-chip microcontroller family. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z901XX offers mask-programmed ROM, which enables the Z8 microcontroller to be used in a high-volume production application device embedded with a custom program (customer-supplied program) and combines to provide support for mid-range and low-end TV applications. The device features an 8-bit internal data path controlled by a Z8 microcontroller, On-Screen Display (OSD) logic circuits, and Pulse Width Modulators (PWM). On-chip peripherals include two register mapped I/O ports (Ports 2 and Port 3), interrupt control logic (one software, two external and three internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support six rows by 20 columns of characters. The character color is specified by row. One of the eight rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5x7 dot pattern) or high resolution (11x15 dot pattern) characters. A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Three 6-bit PWM ports are used for controlling audio signal levels, and Three 8-bit PWM ports used to vary picture levels. Three basic address spaces, The Program Memory, Video RAM, and Register File, support a wide range of memory configurations. For applications demanding powerful I/O capabilities, the Z901XX's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the Z901XX offers two on-chip counter/timers with a large number of user selectable modes.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD
VSS
CP95TEL1300 (10/95)
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PRELIMINARY
Z90110/120/130 CP95TEL1300
GENERAL DESCRIPTION (Continued)
XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 P60 P61 P62 P63 P64 P65 AFCIN Port 3/ Interrupt 256 Byte Register File PWM 1 14 -bit PWM 1 6 KByte Program ROM Port 2 Z8 CPU Core P27 P26 P25 P24 P23 P22 P21 P20
Port 6 (Control)
Port 0 A8-15
Port 1 AD0-7
PWM 6 to PWM 8 6-bit
PWM 6 PWM 7 PWM 8
PWM 9 to PWM11
PWM 9 PWM 10 PWM 11
120 Byte Character RAM
On Screen Display
3 KByte Character ROM
OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK
Functional Block Diagram
2
PRELIMINARY
Z90110/120/130 CP95TEL1300
PIN CONFIGURATION
PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63 P64 P65 AFCIN OSCIN OSCOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Z90100 (LDTC)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 P27 P26 P25 P24 P23 P22 P21 P20 VBLANK VBLUE VGREEN VRED VSYNC HSYNC
40-Pin Mask-ROM Plastic DIP
3
PRELIMINARY
Z90110/120/130 CP95TEL1300
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol VCC VI VI VO IOH IOH IOL IOL TA TSTG
Parameters Power Supply Voltage* Input Voltage Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low Operating Temperature Storage Temperature
Min -0.3 -0.3 -0.3 -0.3
Max +7 VCC +0.3 VCC +0.3 VCC +8.0 -10 -100 20 200
Units V V V V mA mA mA mA C
Notes
[1] [2,3] 1 pin All total 1 pin All total
-65
+150
Notes: [1] Port 2 open-drain [2] PWM open-drain outputs [3] PWM breakdown is 13.2V (normal operation). Will withstand 16V max. (non-momentary operating). * Voltage on all pins with respect to GND. See Ordering Information
STANDARD TEST CONDITIONS
VDD
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram).
From Output Under Test
RLL
150 pF
RLH
Test Load Diagram
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PRELIMINARY
Z90110/120/130 CP95TEL1300
CAPACITANCE TA=25C; VCC=GND=0V; Freq=1.0 MHz; unmeasured pins to GND.
Parameter Input capacitance Output capacitance I/O capacitance AFCIN input capacitance Max 10 20 25 10 Units pF pF pF pF
DC CHARACTERISTICS TA=0C to +70C; V CC=+4.5V to +5.5V; FOSC=4 MHz
Sym VIL VILC VIH VIHC VHY VPU VOL V00-01 V01-11 VOH IIR IIL IOL ICC ICC1 ICC2 Parameter Input Voltage Low Input XTAL/Osc In Low Input Voltage XTAL/Osc In High Input XTAL/Osc In High Schmitt Hysteresis Maximum Pull-Up Voltage Output Voltage Low AFC Level 01 In AFC Level 11 In Output Voltage High Reset Input Current Input Leakage Tri-State Leakage Supply Current TA=0C to +70C Min Max 0 0.7 VCC 0.8 VCC 0.1 V CC 0.2 VCC 0.07 VCC VCC VCC 12 0.4 0.4 0.5 VCC V CC-0.4 -3.0 -3.0 0.45 VCC 0.75 VCC -80 3.0 3.0 20 6 10 0.16 0.19 1.9 3.12 4.75 -46 0.01 0.02 13.2 3.2 2.0 Typical @ 25C Units 1.48 0.98 3.2 3.0 0.8 V V V V V V V V V V V A A A mA mA A Conditions External Clock Generator Driven External Clock Generator Driven External Clock Generator Driven [1] IOL=1.00 mA IOL=0.75 mA [1]
IOH=-0.75 mA VRL=0V 0V,VCC 0V,VCC All inputs at rail All inputs at rail All inputs at rail
Note: [1] PWM open-drain
5
PRELIMINARY
Z90110/120/130 CP95TEL1300
AC CHARACTERISTICS Timing Diagrams
1 3
XTAL1
3 2
2
External Clock
7
5
Tin
4 6
Counter Timer
IRQn
8
9
Interrupt Request
6
PRELIMINARY
Z90110/120/130 CP95TEL1300
AC CHARACTERISTICS Timing Diagrams (Continued)
Vcc
10
11
Internal /RESET
12
External /RESET
Power-On Reset
HSYNC
13
14
OSC2
On-Screen Display
7
PRELIMINARY
Z90110/120/130 CP95TEL1300
AC CHARACTERISTICS TA=0 C to +70 C; VCC=+4.5V to +5.5V; FOSC=4 MHz
No 1 2 3 4 5 6 7 8a 8b 9 10 11 12 13 14 15 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH TdPOR TdLVIRES TwRES TdHsOI TdHsOh TdWDT Parameter Input Clock Period Clock Input Rise and Fall Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Int Req Input Low Int Request Input High Power On Reset Delay Low Voltage Detect to Internal RESET Condition Reset Minimum Width Hsync Start to Vosc Stop Hsync End to Vosc Start WDT Refresh Time Min 250 70 70 3TpC 8TpC 100 70 3TpC 3TpC 25 200 5TpC 2TpV ns ns Max 1000 15 Unit ns ns ns ns
100
ms ns
3TpV 1TpV 12
ms
Note: Refer to DC Characteristics for details on switching levels.
(c) 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: //www.zilog.com
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