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MK2761A
SET-TOP CLOCK SOURCE
Description
The MK2761A is a low-cost, low-jitter, high-performance clock synthesizer for set-top box applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 27 MHz crystal or clock input to produce multiple output clocks including the processor clock, the UART clock, a selectable audio clock, and four low skew copies of the 27 MHz. The audio clocks are frequency-locked to the 27 MHz using our patented zero ppm error techniques. This allows audio and video to track exactly, thereby eliminating the need for large buffer memory. ICS manufactures a large variety of Set-top Box and multimedia clock synthesizers for all applications. Consult ICS to eliminate crystals and oscillators from your board.
Features
* Packaged in a 16-pin narrow (150 mil) SOIC * Available in Pb (lead) free package * Selectable audio sampling frequencies support 32,
44.1, and 48 kHz in most DACs
* * * *
27 MHz crystal or clock input Processor frequency of 16.67 MHz Fixed clocks of 27 and 3.6864 MHz Zero ppm in audio clocks exactly track video frequency
* 25 mA output drive capability at TTL levels * Advanced, low-power, sub-micron CMOS process * Operating voltage of 5.0 V 10%
Block Diagram
VDD 2
ACS1:0 27.000 MHz crystal or clock X1
2
Clock Synthesis and Control Circuitry
Audio Clock 3.6864 MHz 16.667 MHz
Crystal Ocsillator X2 3 GND
4
27.000 MHz
MDS 2761A C I n t e gra te d C i r c u i t S y s t e m s
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525 Race Stre et, San Jo se, CA 9 5126
Revision 031705 te l (40 8) 2 97-12 01
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MK2761A SET-TOP CLOCK SOURCE
Pin Assignment
ACS1 X2 X1/ICLK VDD GND 16.67 MHz 3.68 MHz ACLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ACS0 27 MHz 27 MHz VDD GND 27 MHz 27 MHz GND
Audio Clock (MHz) DecodingTable
ACS1
0 0 1 1
ACS0
0 1 0 1
ACLK
8.192 11.2896 12.288 5.6448
16-pin (150 mil) SOIC
Pin Descriptions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name ACS1 X2 X1/ICLK VDD GND 16.67M 3.68M ACLK GND 27M 27M GND VDD 27M 27M ACS0 Pin Type Input XO XI Power Power Output Output Output Power Output Output Power Power Output Output Input Pin Description Audio clock Select 1. Selects ACLK on pin 8. See table above. Crystal connection. Connect to 27 MHz crystal. Leave unconnected for clock input. Crystal connection. Connect to 27 MHz crystal or to a 27 MHz input clock. Connect to +5 V. Connect to ground. 16.667 MHz processor clock output. 3.6864 MHz clock output. Audio clock output. Determined by status of ACS1, ACS0. See table above Connect to ground. 27 MHz buffered reference clock output. Duty cycle matches input clock. 27 MHz buffered reference clock output. Duty cycle matches input clock. Connect to ground. Connect to +5 V. 27 MHz buffered reference clock output. Duty cycle matches input clock. 27 MHz buffered reference clock output. Duty cycle matches input clock. Audio clock Select 0. Selects audio clock on pin 8. See table above.
MDS 2761A C In te grated Circuit Systems
2
525 Ra ce Street, San Jose, CA 9512 6
Revision 031705 tel (4 08) 297-1 201
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MK2761A SET-TOP CLOCK SOURCE
External Components
The MK2761A requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1F should be connected between VDD and GND, as close to the MK2761A as possible. A series termination resistor of 33 may be used for each clock output. If a clock input is not used, the 27 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use third overtone), parallel resonant, 50 ppm or better. Crystal capacitors should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-4) x 2. So, for a crystal with 16 pF load capacitance, the crystal caps should be 24 pF each.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2761A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +4.5
Typ.
Max.
+70 +5.5
Units
C V
MDS 2761A C In te grated Circuit Systems
3
525 Ra ce Street, San Jose, CA 9512 6
Revision 031705 tel (4 08) 297-1 201
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MK2761A SET-TOP CLOCK SOURCE
DC Electrical Characteristics
VDD = 5.0 V 10% (unless noted), Temp 0 to +70C
Parameter
Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage, CMOS level Operating Supply Current Short Circuit Current Input Capacitance Frequency Error, ACLK
Symbol
VDD VIH VIL VIH VIL VOH VOL VOH IDD IOS CIN
Conditions
X1/ICLK pin only X1/ICLK pin only
Min.
4.5 3.5 2
Typ.
2.5 2.5
Max.
5.5 1.5 0.8
Units
V V V V V V V V
IOH = -25 mA IOL = 25 mA IOH = -8 mA No load, Note 1 Each output
2.4 0.4 VDD-0.4 45 100 7 0
mA mA pF ppm
Note 1: With ACLK clock at 12.28 MHz.
AC Electrical Characteristics
VDD = 5.0 V 10% (unless noted), Temp 0 to +70C
Parameter
Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Absolute Jitter, short term Skew of 27 MHz Outputs
Symbol
tOR tOF
Conditions
0.8 to 2.0 V 2.0 to 0.8 V At 1.4 V Variation from mean Rising edges at 1.4 V
Min.
Typ.
27
Max. Units
MHz 1.5 1.5 ns ns % ps 500 ps
40 200 -500 0
60
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
120 115 105 58
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 2761A C In te grated Circuit Systems
4
525 Ra ce Street, San Jose, CA 9512 6
Revision 031705 tel (4 08) 297-1 201
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MK2761A SET-TOP CLOCK SOURCE
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches* Min Max
16
E INDEX AREA
H
12 D
A A1 B C D E e H h L
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
*For reference only. Controlling dimensions in mm.
A A1 h x 45 C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
MK2761AS MK2761ASTR MK2761ASLF MK2761ASLFTR
Marking
MK2761AS MK2761AS 2761ASLF 2761ASLF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2761A C In te grated Circuit Systems
5
525 Ra ce Street, San Jose, CA 9512 6
Revision 031705 tel (4 08) 297-1 201
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