View PBL38710_187903.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PBL 387 10/1
Subscriber Line Interface Circuit (SLIC)
Key Features
* Ring SLIC eliminates ring relay and conventional ring-generator
RDR VBAT2
Battery switch Ring Trip Detector
TIPX HPR HPT RINGX VCC
VBAT
C1 C2
* Supports sine wave and trapezoidal ringing * -85 V battery feed for high voltage ring signal * On chip automatic battery switch * Programmable battery feed characteristics * Battery supply voltage as low as -21 V for power efficient line card designs * Low on-hook power dissipation, * 50 mW @-24 V battery * Loop current, ring trip and ground key
Ground Key Detector Line Feed Controller and Longitudinal Signal Suppression
Input Decoder and Control
HB E1 DET
Two-wire Interface
RDC RSG
VEE
AGND BGND
Off-hook Detector
RD VTX
VF Signal Transmission
RSN
Ringing Control
VR
Figure 1. Block diagram.
Description
The PBL 387 10/1 ring SLIC (Subscriber Line Interface Circuit) is a bipolar integrated circuit in 90 V technology which replaces the conventional transformer based analog line interface and ringrelay in FITL, WLL, ISDN-TA and other telecommunications equipment with a modern, compact solid state design. Not only is required PCB area reduced, but less component weight and height result as well. The PBL 387 10/1 has been optimized for low cost and to require only a minimum of external components. The PBL 387 10/1 constant-current feed system, programmable to max 40 mA of line current, can operate with battery supply voltages down to -21 V to reduce line card power dissipation. The SLIC incorporates loop current, ground key and ring trip detection functions. Two-to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter (e.g. SLAC, SiCoFi, Combo II). The programmable line terminating impedance could be complex or real to fit every market. The PBL 387 10/1 package is 28-pin PLCC.
PBL 387 10/1 Maximum Ratings
Parameter Symbol Min Max Unit
Temperature, Humidity Storage temperature range Operating junction temperature range Power supply, -40C TAmb 85C VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND VBat2 with respect to BGND Power dissipation Continuous power dissipation at TAmb 85 C Peak power dissipation at TAmb = 85 C, t < 100 ms, tRep > 1 sec. Ground Voltage between AGND and BGND Digital inputs, outputs (C1, C2, E1, HB, DET) Input voltage Output voltage (DET disabled) Output current (DET enabled) Ring voltage, input (VR) Input voltage
TStg TJ VCC VEE VBat VBat2 PD PDP VG VID VOD IOD VVR
-55 -40 -0.5 -6.5 -85 VBat
+150 +140 6.5 0.5 VEE + 0.5 VEE + 0.5 1.5 4
C C V V V V W W V V V mA V V V V V mA
-0.3 0 0
0.3 VCC VCC 5
VEE
VCC 2 5 10 15 110
TIPX and RINGX terminals, -40C TAmb 85C, VBat = -80V, Active, Disconnect and Stand by states TIPX or RINGX voltage, continuous (referenced to AGND), Note 1 VTA, VRA VBat TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 1 VTA, VRA VBat - 5 TIPX or RINGX, pulse < 1 s, tRep > 10 s, Note 1 VTA, VRA VBat - 25 TIP or RING, pulse < 250 ns, tRep > 10 s, Note 1 VTA, VRA VBat - 35 TIPX or RINGX maximum current supplied
Recommended Operating Conditions
Parameter Symbol Min Max Unit
Ambient temperature VCC with respect to AGND VEE with respect to AGND VBat2 with respect to BGND, Note 2 VBat with respect to BGND
Tamb VCC VEE VBat2 VBat
-40 4.75 -5.25 -58 -80
+85 5.25 -4.75 -24 VBat2
C V V V V
Notes
1. Whith diodes in series with the VBat and VBat2 , see figure 12. 2. -24V 2
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1 Electrical Characteristics
-40 C TAmb 85 C, VCC = +5V 5 %, VEE = -5V 5%, VBat = -80V, VBat2 = -48V, AGND = BGND, RDC1=RDC2 =41.7k,RSG = 0, RD = 33k, RDR = 5.8 k, CHP=10nF, CDC = 1.5 F, ZL =600 , state input control pin HB = 0, unless otherwise specified.
Parameter Ref fig Conditions Min Typ Max Unit
Two-wire port Overload level, VTRO Input impedance, ZTR Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM
2
ZL = 600 , 1% THD Note 1 Note 2 0 < f < 100 Hz active state stand-by state IEEE standard 455-1985 0.2 kHz f 1.0 kHz 1.0 kHz f 3.4 kHz 0.2 kHz f 1.0 kHz 1.0 kHz f 3.4 kHz ELo BLME = 20 * Log V TR 0.2 kHz f 1.0 kHz 1.0 kHz f 3.4 kHz ELo BLFE = 20 * Log V TX 0.2 kHz < f < 3.4 kHz V BMLE = 20 * Log TR ,ERX = 0 VLo
3.1 12 10 8.5 46 46 46 46 63 58 63 58 35
VPeak /wire mArms/wire mArms/wire dB dB dB dB
Longitudinal to metallic balance, BLME
3
Longitudinal to metallic balance, BLFE
3
46 46
63 58
dB dB
Metallic to longitudinal balance, BMLE
4
40
dB
C
TIPX
VTX
Figure 2. Overload level, VTRO, two-wire port 1 << RL, RL= 600 C RT = 600 k, RRX = 300 k
RL
VTRO
ILDC
PBL 387 10/1
RINGX RSN
RT
E RX
RRX
Figure 3. Longitudinal to metallic (BLME) and Longitudinal to four-wire (BLFE) balance 1 << 150 , RLT = RLR = 300 C RT = 600 k, RRX = 300 k
TIPX ELo C RLT V TR RLR RINGX
VTX
PBL 387 10/1
RSN
RT
V TX
RRX
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
3
PBL 387 10/1
Parameter Ref fig Conditions Min Typ Max Unit
Four-wire to longitudinal balance, BFLE
4
0.2 kHz < f < 3.4 kHz E BFLE = 20 * Log RX VLo |ZTR + ZL| |ZTR - ZL| ZTR ZL = nom. 600 0.2 kHz f 0.5 kHz 0.5 kHz f 1.0 kHz 1.0 kHz f 3.4 kHz, Note 9 active, IL = 0 stand-by, IL = 0 active, IL = 0 stand-by, IL = 0 IL = 0, RSG = 0, VBat2 = -52V r = 20 * Log
40
dB
Two-wire return loss, r
25 27 23 -1.5 0.6 -46.5 -47 45.0
TIPX idle voltage, VTi RINGX idle voltage, VRi TIPX-RINGX open loop metallic voltage, VTR Four-wire transmit port (VTX) Overload level, VTXO Output offset voltage, VTX Output impedance, zTX Four-wire receive port (RSN) Receive summing node (RSN) dc voltage Receive summing node (RSN) impedance Receive summing node (RSN) current (IRSN) to metallic loop current (IL) gain, RSN 5
43.0
47.0
dB dB dB V V V V V
Load impedance > 20 k, 1% THD, Note 3 0.2 kHz f 3.4 kHz IRSN = 0 mA 0.2 kHz f 3.4 kHz 0.3 KHz f 3.4 kHz
3.1 -60 <5 0 <10 1000 60 20
VPeak mV V ratio
20
TIPX C VLo RLT V TR RLR RINGX
VTX
PBL 387 10/1
RSN
RT
Figure 4. Metallic to longitudinal and four-wire to longitudinal balance
E RX
RRX
1 << 150 , RLT =RLR = 300 C RT = 600 k, RRX = 300 k
C RL ILDC EL
TIPX
VTX
PBL 387 10/1
RINGX RSN
RT
VTXO
Figure 5. Overload level, VTXO, four-wire transmit port 1 << RL, RL= 600 C
RRX
RT = 600 k, RRX = 300 k
4
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1
Parameter Ref fig Conditions Min Typ Max Unit
Frequency response Two-wire to four-wire, g2-4
6
0.3 kHz < f < 3.4 kHz relative to 0 dBm, 1.0 kHz. ERX = 0 V 0.3 kHz < f < 3.4 kHz relative to 0 dBm, 1.0 kHz. EL = 0 V 0.3 kHz < f < 3.4 kHz relative to 0 dBm, 1.0 kHz. EL = 0 V
-0.2
0.2
dB
Four-wire to two-wire, g4-2
6
-0.2
0.2
dB
Four-wire to four-wire, g4-4
6
-0.2
0.2
dB
Insertion loss Two-wire to four-wire, G2-4
6
0 dBm, 1.0 kHz, Note 4 VTX G2-4 = 20 * Log , ERX = 0 VTR 0 dBm, 1.0 kHz, Notes 4, 5 VTR G4-2 = 20 * Log , EL = 0 ERX Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -55 dBm to -40 dBm Ref. -10 dBm, 1.0 kHz, Note 8 -40 dBm to +3 dBm -55 dBm to -40 dBm C-message weighting Psophometrical weighting Note 6 0 dBm, 1.0 kHz test signal 0.3 kHz < f < 3.4 kHz
-0.2
0.2
dB
Four-wire to two-wire, G4-2
6
-0.2
0.2
dB
Gain tracking Two-wire to four-wire
6
-0.1 -0.2 -0.1 -0.2 10 -80
0.1 0.2 0.1 0.2 12 -78
dB dB dB dB dBrnC dBmp
Four-wire to two-wire
6
Noise Idle channel noise at two-wire (TIPX-RINGX) or four-wire (VTX) output Harmonic distortion Two-wire to four-wire Four-wire to two-wire
-60 -60
dB dB
C
TIPX
VTX
Figure 6. Frequency response, insertion loss, gain tracking. 1 << RL, RL= 600 C RT = 600 k, RRX = 300 k
RL VTR EL ILDC
PBL 387 10/1
RINGX RSN
RT
E RX
VTX
RRX
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
5
PBL 387 10/1
Parameter Ref fig Conditions Min Typ Max Unit
Battery feed characteristics Constant loop current, ILProg
ILProg =
2500 RDC1 + RDC2
, RDC1, RDC2 in k
0.88 ILProg ILProg
1.12 ILProg mA
Stand-by state loop current, IL Ring state loop current limit, ILLim Ring state loop current limit, ILLim Ring injection Input impedance, ZVR Ring node (VR) voltage to tip-ring voltage (VTR) gain Ring signal distortion Loop current detector Loop current detector threshold Ground key detector ILTIPX and IRINGX current difference, ILOn, to trigger the ground key detector Ring trip detector Ring trip detector threshold Digital inputs (C1, C2, HB, E1) Input low voltage, VIL Input high voltage, VIH Input low current, IIL C1, C2, HB E1 Input high current, IIH Detector output (DET) Output low voltage, VOL Output high voltage,VOH Internal pull-up resistor Power dissipation (VBat2 = -48V) P1 P2 P3 P4
IL =
VBat - 2 RL + 2000
: TA = 25C
0.8 IL 70 47 73 50
IL 95 70 95 70 10.5
1.2 IL
mA mA mA mA mA k
VTIP-RING > 0 V, -40 - 0 C VTIP-RING < 0 V, -40 - 0 C VTIP-RING > 0 V, 0 - 85 C VTIP-RING < 0 V, 0 - 85 C
RL = 7 k, 1.1 V VR 1.9 V 20 Hz, DC 20 Hz, Sine ILTh = 360 / RD , RD = 33 k 36.6 38.6 0.5 ILTh 10.5 40.6 2.5 1.15 ILTh 15.5 ratio % mA mA
0.85 ILTh 5.5
IRTh = 360 / RDR , RDR = 5.8 k
0.85 IRTh 0 2.0
IRTh
1.15 IRTh 0.8 VCC
mA V V A A A V V k mW mW mW mW
VIL = 0.4 V -700 -100 VIH = 2.4 V IOL = 2 mA IOH = 100 A 200 0.45 2.7 7.0 15.6 35 60 130 610 27.0 60 100
Open circuit state, C1, C2 = 0, 0 Stand-by state, HB =0 C1, C2 = 1, 1; on-hook Active state, C1, C2 = 0, 1 On-hook, RL = @VBat2 = -24V Off-hook, RL = 300 @VBat2 = -24V
6
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1
Parameter Ref fig Conditions Min Typ Max Unit
Power supply currents VCC current, ICC VEE current, IEE VBat current, IBat VBat2 current, IBat2 VCC current, ICC VEE current, IEE VBat current, IBat VBat2 current, IBat2 VCC current, ICC VEE current, IEE VBat current, IBat VBat2 current, IBat2 Power supply rejection ratios VCC to 2- or 4-wire port VEE to 2- or 4-wire port VBat to 2- or 4-wire port VBat2 to 2- or 4-wire port Temperature guard Junction threshold temperature, TJG Thermal resistance 28-pin PLCC, RJP28plcc
Open circuit state C1, C2 = 0, 0 On-hook Stand-by state C1, C2 = 1, 1 On-hook Active state C1, C2 = 0.1 On-hook VBat = -80V, VBat2 = -24V Active State C1, C2 = 0.1 50Hz < f< 3400Hz, Vn = 100mVRMS
2.0 1.2 0.2 0.1 2.4 1.1 0.4 0.3 5.9 2.3 0.2 3.1 45 45 32 45 160
mA mA mA mA mA mA mA mA mA mA mA mA dB dB dB dB C C/W
Junction to terminals 3, 10, 17, 24 connected together
20
Notes
1. 2. The overload level is specified at the two-wire port with the signal source at the four-wire receive port. The two-wire impedance is programmable by selection of external component values according to: ZTRX = ZT/|G2-4 * RSN| where: ZTRX = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G2-4 = transmit gain, nominally = 1 RSN = receive current gain, nominally = -1000 (current defined as positive when flowing into the receive summing node (RSN), and when flowing from Tip to Ring). The overload level is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G2-4 = 1. Fuse resistors RF impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for RF = 0. The specified insertion loss tolerance does not include errors caused by external components. 6. The two-wire idle noise is specified with the port terminated in 600 (RL) and with the four-wire receive port grounded (ERX = 0). The four-wire idle noise at VTX is specified with the two-wire port terminated in 600 (RL). The noise specification is with respect to a 600 programmed two wire impedance level at VTX. The four-wire receive port is grounded (ERX = 0). The level is specified at the two-wire port. The level is specified at the four-wire receive port and referenced to a 600 programmed two wire impedance level. Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance programming resistance, e.g., by dividing RT into two equal halves and connecting a capacitor from the common point to ground. For RT = 600 k this capacitor would be approximately 30 pF. Increasing CHP to 0.033 F improves low-frequency return loss.
7. 8.
9.
3.
4.
5.
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
7
PBL 387 10/1
2 VBAT2
27 RINGX
1 BGND
3 VBAT
26 TIPX
4 VCC
28 NC*
38 PBL 71 0/1
25 24 23 22 21 20 19
HB 5 NC* 6 VR 7 RSG 8 E1 9 VBAT 10 DET 11
NC* VBAT RDR RD HPR HPT VTX
C2 12
C1 13
RDC 14
AGND 15
RSN 16
VBAT 17
VEE 18
* Pin must be left open Figure 8. Pin configuration 28-pin PLCC, top view.
8
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1 Pin Description
Refer to figure 8.
PLCC Symbol Description
1 2 3 4 5 6 7 8 9 10 11
BGND VBAT2 VBAT VCC HB NC VR RSG E1 VBAT DET
Ground. Should be tied together with AGND. Low battery supply voltage. High battery supply voltage. +5V power supply Enables the High Battery to be present in the stand-by state. The purpose is to be able to offer a high open-loop voltage (battery switch between ring and active state is controlled from the control pins). No internal Connection. Note 1. Voltage Ring. Low voltage (2Vpk) ringsignal (any waveform) is injected here. The internal Saturation Guard programming Resistor, RSG, connects from this terminal to VEE . Refer to section "Battery feed" for detailed information. TTL compatible Enable input. Enables desired detector to be gated to the DET output. Refer to section "Control inputs" for detailed information. This pin is used for heat sinking and is internally connected to VBAT. Detector output. Inputs C1 and C2 together with enable input E1 select one of the three detectors to be connected to the DET output. A logic low at the enabled DET output indicates a triggered detector condition. The DET output is open collector with internal pull-up resistor (approximately 15 k to VCC ). C1 and C2 are TTL compatible inputs controlling the SLIC operating states. Refer to section "Control inputs" for details. Constant current feed is programmed by two resistors connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to GND to isolate the ac signal components. Ground. Should be tied together with BGND. Receive summing node. 1000 times the current (dc and ac) flowing into this pin equals the metallic (transversal) current flowing from RINGX to TIPX. Programming networks for constant current feed, two-wire impedance and receive gain connect to the receive summing node. This pin is used for heat sinking and is internally connected to pin 3. -5V power supply. Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of one. The two-wire impedance programming network connects between VTX and RSN. Tip side of ac/dc separation capacitor CHP. Other end of CHP capacitor connects to pin HPR. Ring side of ac/dc separation capacitor CHP. Other end of CHP connects to pin HPT. Off-hook detector Programming Resistor RD in parallel with filter capacitor CD connect from RD to VEE. Connect to the "ring trip detector" resistor. This pin is used for heat sinking and is internally connected to pin 3. No internal Connection. Note 1.
12 13 14
C2 C1 RDC
15 16
AGND RSN
17 18 19
VBAT VEE VTX
20 21 22 23 24 25 26 27 28
HPT HPR RD RDR VBAT NC TIPX RINGX NC
}
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components. No internal Connection. Note 1.
Note: 1.
Terminals marked NC are not internally connected to the chip but may be used for future functions. Do leave open.
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
9
PBL 387 10/1
For applications where ZT/1000+ 2RF is chosen to be equal to ZL the expression for G4-2 simplifies to: Z 1 G4-2 = - T * ZRX 2
VTX
+
ZL VTR
TIP RF ZTR
TIPX
IL
+
RHP
+
RING EL RF
-
1
+
VTX
Four-Wire to Four-Wire Gain From (1), (2) and (3) with EL = 0: G4-4 = Z VTX ZL + 2RF =- T * VRX ZRX ZT + ZL + 2RF 1000
IL RINGX ZT
-
Hybrid Function
Z RX RSN I L /1000
+
VRX
PBL 387 10/1
Figure 9. Simplified ac transmission circuit.
-
Functional Description and Applications Information Transmission
General A simplified ac model of the transmission circuits is shown in figure 9. Circuit analysis yields: VTR = VTX + IL * 2RF VTX VRX I + =L ZT ZRX 1000 VTR = EL - IL * ZL where: VTX is a ground referenced version of the ac metallic voltage between the TIPX and RINGX terminals. VTR is the ac metallic voltage between tip and ring. EL is the line open circuit ac metallic voltage. is the ac metallic current. IL RF is a fuse resistor. ZL is the line impedance. ZT determines the SLIC TIPX to RINGX impedance at voice frequencies. ZRX controls four- to two-wire gain. VRX is the analog ground referenced receive signal. (1) (2) (3) ZTR = Two-Wire Impedance To calculate ZTR, the impedance presented to the two-wire line by the SLIC, in active state, including the fuse resistor RF , let VRX = 0. From (1) and (2): ZT + 2RF 1000
The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional CODEC/filter combinations. Please, refer to figure 10. Via impedance ZB a current proportional to VRX is injected into the summing node of the combination CODEC/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain a voltage proportional to VRX is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be made to cancel by letting: VTX VRX + = 0 (EL = 0) RTX ZB The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the balance network ZB can be calculated from: V ZB = - RTX * RX = VTX ZT + ZL + 2RF ZRX 1000 RTX * * ZL + 2RF ZT
Thus with ZTR and RF known: ZT = 1000 * (ZTR - 2RF) The SLICs two-wire output impedance in ringing state is typically 2* 40 for a 15 -100 Hz ring-signal. Two-Wire to Four-Wire Gain From (1) and (2) with VRX = 0: G2-4 = VTX = VTR ZT/1000 ZT + 2RF 1000
Four-Wire to Two-Wire Gain From (1), (2) and (3) with EL = 0: V Z ZL G4-2 = TR = T * VRX ZRX ZT + ZL + 2RF 1000
If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. Contact Ericsson Microelectronics for assistance. The PBL 38710/1 SLICs may also be used together with programmable CODEC/filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information.
10
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1
RFB
VTX
RTX VT ZT Z RX ZB
PBL 387 10/1
Combination CODEC/Filter
V RX
RSN
Figure 10. Hybrid funktion.
RF TIP
TIPX
VT + VLo I Lo RHP / 2 VT + VR + VLo 2
HPT CHP HPR RF RING RINGX RHP / 2 VR + VLo
1/
2
+
1/ 2
I Lo
+
V LoRef
1
VLO
R Lo 20K
Capacitors CTC and CRC The capacitors designated CTC and CRC in figure 12, connected between TIPX and ground as well as between RINGX and ground, are recommended as an addition to the overvoltage protection network. Very fast transients, appearing on tip and ring, may pass by the active components in the overvoltage protection network before they have had time to activate and could damage the SLIC. CTC and CRC short such very fast transients to ground. CTC and CRC also work as RFIfilters in conjunction with suitable series impedances (i.e. resistances, inductances). Resistors RF1 and RF2 may be sufficient, but series inductances can be added to form a second order filter. The recommended value for CTC and CRC is 2200 pF. Higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. CTC and CRC contribute to a metallic impedance of 1/(*f*CTC) = 1/(*f*CRC), a TIPX to ground impedance of 1/(2**f*CTC) and a RINGX to ground impedance of 1/(2**f*CRC). AC - DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HPT and HPR provides the separation between circuits sensing tip-ring dc conditions and circuits processing ac signals. A CHP value of 10 nF will position the low end frequency response 3dB break point at 48 Hz (f3dB) according to f3dB= 1/(2**RHP*CHP) where RHP 330 k.
I Lo / 1000
PBL 387 10/1
Figure 11. Longitudinal impedance. Longitudinal Impedance A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range.This is accomplished by comparing the instantaneous two-wire longitudinal voltage to an internal longitudinal reference voltage, VLoRef . VLoRef = VBat2 VT + VR = 2 2 noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. Refer to figure 11. Circuit analysis yields: VLo I = Lo RLo 1000 which reduces to RLoT = RLoR = VLo /ILo =20k/1000 = 20 where: RLo = 20 k RLoT = RLoR = longitudinal resistance/wire VLo = longitudinal voltage at TIPX,RINGX ILo = longitudinal current
Battery Feed
The block diagram in figure 13 shows the PBL 38710/1 battery feed system and figure 14 illustrates the battery feed characteristics in the active state. For a tip to ring dc voltage VTR less than the saturation guard reference voltage ,VSGRef, the SLIC emulates a constant current feed characteristic in the active state. The constant current is independent of the actual battery voltage, VBat2, connected to the SLIC. With the tip to ring DC voltage VTR exceeding VSGRef, the feed characteristic changes to a nearly-constant voltage feed. This is to prevent the tip and ring drive amplifiers from distorting the AC signal as might have otherwise occurred due to insufficent voltage margin between VTR and VBat2. Thus the SLIC
where VT and VR are tip and ring ground referenced voltages without any longitudinal component. As shown below the SLIC appears as 20 per wire to longitudinal disturbances. It should be
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
11
PBL 387 10/1
C HP R FB
HPR
HPT VTX VEE VBAT RSN AGND RDC C1 C2 DET VBAT E1 RSG VR
RD C GG R F1 TIP C TC OVP R F2 RING VB VEE R DR VBAT
R TX VEE VBAT RT R RX
0 0
RD RDR VBAT NC TIPX RINGX
RB
+
+
R DC1 R DC2
C DC
CODEC/ Filter
C RC
NC BGND VBAT2
PBL 387 10/1 VCC VBAT C VCC C VEE VEE R SG RING SIGNAL VEE
VB2
D VB2 D BB
R BAT2 VBAT C BAT2 C BAT VCC
VBAT VCC HB NC
VB VEE
D VB D BE
VBAT R BAT
PBL 387 10/1
SYSTEM CONTROL INTERFACE
RESISTORS: RT RRX RTX RB RDC1 RDC2 RSG RD RDR RF1,RF2 RBAT,RBAT2 RFB 442 k 1% 1/10 W 221 k 1% 1/10 W 20 k 1% 1/10 W 15.8 k 1% 1/10 W 61.9 k 5% 1/10 W 61.9 k 5% 1/10 W 0 5% 1/10 W 39 k 5% 1/10 W 7 k 5% 1/10 W 40 1% 5.1 5% 1/10 W Depending on Codec/filter
CAPACITORS: CTC CRC CHP CGG CBAT CBAT2 CVEE CDC CVCC 2.2 2.2 0.01 220 470 470 100 1.5 100 nF nF F nF nF nF nF F nF 20% 20% 20% 20% 20% 20% 20% 20% 20% 100V 100V 100V 100V 100V 100V 10V 10V 10V
DIODES: DBE DBB DVB DVB2 OVP: TISP PBL2 (Power Innovations) 1N4448 1N4448 1N4448 1N4448
Design spec. ZTR IL G4-2 G2-4 VTRO 600 20 1 0.73 3.1 mA
V
Figure 12. Single-channel subscriber line interface with PBL 378 10/1 and combination CODEC/filter.
TIPX + RL VTR -
I Ldc BGND VTR
-2.5 V RDC
1
RINGX
VBat2 I Ldc VSG Ref +
Comp. VTR > VSG Ref VTR < VSG Ref 1 0
RDC2
-
RSG 0.6
C DC
5 V SG Ref = 12.9 + 4.9 10 17300+RSG 5 V SG = -7.7 - 2.9 10 VSG 17300+RSG
R SG
RDC1
Saturation Guard
V EE
PBL 387 10/1
Figure 13. Battery feed (C2, C1 = 1, 0 active state).
I Ldc 1000
RSN
12
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1
DC characteristics A
B
D
G
IL [mA]
E
C
F
H
VTR [V]
B: C: D:
VSGRef when RSG -> VTR when RSG -> and RL -> VSGRef = 12.9 + 4.9 * 105 RSG + 17300
E:
F: G: H:
Figure 14. Battery feed characteristics (without protection resistors on the line, active state). automatically adjusts the tip to ring dc voltage VTR to the maximum safe value. With the SLIC in the stand-by state (C2,C1=1.1) a resistiv feed characteristic is enabled. To achive a high open loop voltage it is possible to switch the battery feed from VBat2 to VBat When the SLIC is in the ringing state VBat is used in order to achive a ring voltage as high as possible.The battery feed programming is also disconnected. The following text explains the four battery cases in more detail. Case 1: SLIC in the active state VTR < VSGRef In the active state C2=1, C1=0 and VBat2 is used for battery feed. In this operating state tip to ring voltages VTR less than VSGRef, cause the block titled saturation guard (figure 13) to be disabled, i.e. its output is equal to zero. For this case circuit analysis yields: 2.5 * 1000 RDC1 + RDC2 = ILProg where: ILProg =
constant loop current (independent of the loop resistance RL). RDC1 + RDC2 = the programming resistance which sets the constant loop current.
For a tip to ring voltage VTR less than VSGRef the PBL 38710/1 thus emulate a constant current feed with the magnitude of the constant current set by resistors, RDC1, and RDC2. Capacitor CDC at the RDC1 - RDC2 common point removes vf signals from the battery feed control loop. CDC is calculated according to:
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
}
A:
IL = ILProg =
2.5 * 1000 RDC1 + RDC2
VTR = RL * IL =
16.7 + 4.9*105 / (RSG + 17300) RL + (RDC1 +RDC2) / 653
1 2.5 4.9*105 * * 1000 * (16.7 + -V ) RSG + 17300 TR 3.8 RDC1 + RDC2 4.9*105 RSG + 17300 when RL -->
VTR = 16.7 +
VSGRef when RSG --> 0 VTR when RSG --> 0 and RL -->
C DC = T (
1 R DC 1
+
1 ) R DC 2
where T=30 ms. Note that RDC1 =RDC2 yields minimum CDC value. Case 2: SLIC in the active State VTR > VSGRef In the active state C2=1, C1=0 and VBat2 is used for battery feed. The saturation guard reference voltage is user programmable according to:
V SG Re f = 12 , 9 + 4 ,9 10 17300 5
+ R SG
where: RSG = saturation guard reference programming resistor in . VSGRef = saturation guard reference voltage in volts.
13
PBL 387 10/1
Once the dc metallic voltage, VTR, exceeds the saturation guard reference voltage, VSGRef, the saturation guard becomes active and the following expression describes the battery feed characteristic: 16.7 + 4.9*105 / (RSG + 17300) VTR = RL * RL + (RDC1 +RDC2) / 653 where RSG, RL and VTR have the same meaning as described above. At open loop, i.e. RL-> , the saturation guard limits the tip-ring voltage to: VTR = 16.7 + 4.9*105 / (RSG + 17300) Figures 17 through 20 illustrate the PBL 38710/1 loop feed with VBat2 =-48V and VBat2 = -24V. For applications where the tip-to-ring DC voltage, VTR, approaches the VBat2 value. RSG should be adjusted as follows: As a general guideline, adjust RSG in the VTR expression above to yield at maximum loop VTRMax |VBat 2|- 8 resistance. Maintaining VTR below this limit ensures vf transmission through the SLIC without clipping. RSG can be calculated from:
R SG = 4 ,9 10 5 - 17300 ( R DC 1 + R DC 2 ) ( VBat2 - V Marg in) 1 + - 16 , 7 600 R L
Case 3: SLIC in the Stand-by State In the stand-by state C1=1, C2=1and input HB selects the battery to be used for battery feed. With the SLIC operating in the stand-by, power saving state, the tip and ring drive amplifiers are disconnected and a resistive battery feed is engaged. The loop current can be calculated from: IL |VBat| - 2 RL + 2000
where: IL = loop current (A). RL = loop resistance (). VBat = battery supply voltage (VBat or VBat2 depends on input HB) (V). The stand-by short circuit loop current (ILSh ) for VBat2 = -28V (HB=0) is then limited to: ILSh 13.9 mA. HB=1 enables VBat for use in applications that demand a high open loop voltage. Note that the equation above is also valid in the high battery state and that the SLIC will not change to active state by itself when the loop current detector goes low. Switching between stand-by and active state is controlled via inputs C1 and C2. Case 4: SLIC in the Ringing State In the ringing state C2=0, C1=1 and VBat is used for battery feed. To calculate loop current during ringing, see the " PBL 38710/1 Power Dissipation " section. PBL 38710/1 Power Dissipation Two cases: active ( VBat2 is used for battery feed) and ringing (VBat is used for battery feed).
V Bat > V Bat2
300 ) even if the wire resistance is close to 0 . Figure 23 compares line feed power dissipation as a function of loop resistance for three cases: feed resistor dissipation for a conventional 2*400 resistive feed, PBL 38710/1 with 30 mA constant current feed and VBat2 = -48V and PBL 38710/1 with 30 mA constant current feed and VBat2 =-28V. The diagram illustrates the significant PBL 38710/1 power-saving compared to the 2*400 feed. During ringing the highest power dissipation occurs when the line is 0 and maximum number of bells are connected ( 5REN ).For information about the REN specification see the "Ring Voltage" section.The line current is calculated as: |VBat| - 3 IL = ZBell + ZLine + 2RF + ZTR where: = bell impedance. ZBell ZLine = line impedance. RF = fuse and protection resistors. ZTR = tip- ring impedance during ringing (typically 2*40 ). The maximum SLIC power dissipation during ringing is calculated as: PSLIC = PS - POut where (for a sinusodial shaped ringsignal) 2 * VBat * ILMax PS = + PTROpen and POut = ILrms2 * (ZBell + 2RF) Example: calculate the maximum slic power dissipation when VBat = -80V, ZBell =1.4 k(5USREN), ZLine= 0, RF = 40 and ZTR = 2*40 . For these component values ILmax = 47 mA, PS = 2.8 W (PTROpen =390 mW (typ) @ VBat = -80V in ringing state), Pout 1.7 W and PSLIC = 1.1 W which is less than the maximum allowed power dissipation (PD =1.5 W, see data sheet). Temperature Guard A ring to ground short circuit fault condition as well as other improper operating conditions may cause excessive SLIC power dissipation. If junction temperature increases beyond TJG , the junction threshold temperature, the temperature guard will trigger, causing the SLIC to be set to a highimpedance state. In this high impedance state, power dissipation is reduced and
where: VMargin = 8V to allow a maximum overload level, VTRO, of 3.1V. If transmission is required at open loop, i.e. RL -> , the above expression simplifies to:
R SG = 4 ,9 10 5 - 17300
V Bat2 - V Marg in - 16 , 7
In applications where the longest possible two-wire loop length is important, it is possible to increase the maximum loop resistance at minimum allowable loop current by reducing the voltage margin VMargin = |VBat2|-VTRMax from the 8V suggested above. Doing so will, however, reduce the overload level from 3.1 VPeak as shown in figure 21. Figure 22 shows the typical maximum loop resistance at 18 mA as a function of the voltage margin for several values of programmed constant-current feed and VBat 2 = -48 V.
The short circuit SLIC power dissipation is (in active state): PShTot = ILSh* (|VBat2| - ILSh * 2RF) + P3 where VBat2 is the battery voltage connected to the SLIC at pin VBAT2.
ILSh = 2 ,5 1000 R DC1 + R DC 2
is the constant loop current. P3 is on hook active state power dissipation (typ 130mW; VBat2 = -24V ). Note that a short circuited loop is not a normal operational condition. The terminal equipment will add some dc resistance (typically 150 to
14
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1
Ground Key Detector The ground key detector is indicating when the ground key is pressed (active)
ILTIPX TIPX RINGX ILRINGX IRDR + _
Ground Key Det. 2-Wire Interface
IRD
Input Decoder
VCC
C1 C2 E1
Mux
1
DET
+ _ VRef RD VEE
PBL 387 10/1
RDR CDR CD RDR RD
by putting the output pin DET to a logical low level when selected. The ground key detector circuit senses the difference in TIPX and RINGX currents. Should the current difference exceed the threshold value, ILOn , the detector is triggered. As the current difference decreases the detector is reset at current threshold ILOff . ILOn > ILOff , i.e. the detector has hysteresis. The triggered detector results in a logic low at the DET output assuming the ground key detector has been selected via the control input. For ILOn and ILOff numerical values please refer to table "Electrical characteristics".
V EE
Figure 15. Loop current, ring -trip and ground key detectors. the junction temperature will return to a safe value. Once below TJG, the SLIC is returned back to its normal operating mode and will remain in that state, assuming the fault condition has been removed. As long as the temperature guard is triggered, the loop current detector will stay in active state. PBL 38710/1 Long Loop vf Transmission To ensure that the maximum vf signal intended to be received/transmitted by the SLIC will not experience limiting in the TIPX / RINGX drive amplifiers at long loops, the saturation guard must be correctly programmed. The section, "Battery Feed, Case 2" describes how to calculate a value for the saturation guard programming resistor RSG. Loop Current Detector The loop current detector is indicating that the telephone is off hook by putting the DET output to a logical low level when selected.The loop current threshold value, ILTh, at which the loop current detector changes state is programmable by selecting the value of resistor RD. RD connects between pin RD and VEE. Figure 15 shows a block diagram of the loop current detector. The two-wire interface produces a current flowing out of the pin RD: IRD = |ILTIPX - ILRINGX| / 600 = IL / 300 where ILTIPX and ILRINGX are currents flowing into the TIPX and RINGX terminals and IL is the loop current. The voltage generated by IRD across the programming resistor RD is compared to an internal reference by a comparator. A logic low results at the DET output when the loop current exceeds the on-hook to off-hook detect threshold, ILTh. The programming resistor, RD , can be calculated for a desired ILTh from: RD = 360 / ILTh RD is in k for ILTh in mA. When the loop current is less than ILTh the DET output is logic high . The CD filter capacitor is calculated according to CD =T/RD with time constant T=0.5 ms. Note that CD may not be required if DET is software filtered.
DET
1 0
GND RDR OFF hook
trigger level
VEE ON hook
Figure 16. Ring-trip detector behavior. Ring Trip Detector The ring trip detector indicates if the line goes off hook while ringing by putting the DET output to a logical low level. The impedance changes when the telephone goes off hook and the detector detects the change in the line current. The loop current threshold value, ILTh, at which the ring trip detector changes state is programmable by selecting the value of resistor RDR. RDR connects between pin RDR and VEE. Figure 15 shows a block diagram of the ring trip detector. The two-wire interface produces a current flowing out of the pin RDR IRDR = |ILTIPX - ILRINGX| / 600 = IL / 300 where ILTIPX and ILRINGX are currents flowing into the TIPX and RINGX terminals and IL is the loop current. The voltage generated by IRDR across the programming resistor RDR is compared to an internal reference by a comparator. When the loop current exceeds the detector threshold ILTh, then the
DET
Loop Monitoring Functions
The loop current, ground key and ring trip detectors report their status through a common output,
DET
. The detector to
be connected to DET is selected via the control inputs. Please refer to section Control Inputs for a description of the control interface.
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
15
PBL 387 10/1
output is logic low. The programming resistor, RDR , can be calculated for a desired ILThfrom: RDR = 360 / ILTh RDR is in k for ILTh in mA. When the loop current is less than ILTh then the DET output is logic high. For calculation of the loop current during ringing see section " PBL38710/1 Power Dissipation ". The CDR filter capacitor is calculated according to CDR =T/RD R with time constant T=0.5 ms. Note that CDR may not be required if DET is software filtered. See figure 16 for the behavior of the states at the DET pin and voltage at the RDR pin. Stand-by State (C2,C1 = 1.1) Signal transmission is inhibited. In the Stand-by State the line drive amplifiers are disconnected. The loop feed is converted to resistive form. The battery switch input signal HB controls which battery that is being used for battery feed. Both the loop and ground key detectors are activated in this operating state. Input E1 control the selection of one of these detectors to be gated to the DET output. Table 1 summarizes the above description of the control inputs. Enable Input (E1) The TTL compatible input E1 controls the function of the DET output in the active and stand-by states. In open circuit and ringing state the detector to be gated to the DET is automatically chosen by the SLIC when one of these states is selected by input signals C1 and C2. When set to logic level low, in the active or the stand-by state, E1 gates the ground key detector to the DET output. And when E1 is set to logic lewel high the loop current detector is gated to the output. Table 1 summarizes the description of the E1 input.
DET
Battery Switch (HB) The TTL compatible input HB controls the switching, in the stand-by state, between VBat at pin VBAT and VBat2 at pin VBAT2.
V Bat > V Bat2
.(Note that when
Control Inputs
The PBL 38710/1 SLICs have four TTL compatible digital control inputs HB, E1, C2 and C1. A decoder in the SLIC interprets the control input condition and sets up the commanded operating state. Open Circuit State (C2,C1 = 0.0) In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This causes the SLIC to present a high impedance to the line. Power dissipation is at a minimum. No detectors are active. Ringing State (C2,C1 = 0.1) To accomplish a high voltage ring signal the battery feed uses the high voltage,VBat , when the ringing state is chosen. The SLIC will automatically (without any influence of input HB) switch to the high voltage. A low voltage ring signal at pin VR will be amplified and is transferred to the subscriber as a balanced ring signal.For additional information about the ring signal; see the Ring Voltage section.The ring trip detector is indicating off hook with a logic low level at the detector output. Active State (C2,C1 = 1.0) TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop current. Vf signal transmission is normal.Both the loop current and the ground key detectors are activated. Input E1 control the selection of one of these detectors to be gated to the
DET
ringing state is selected by inputs C1 and C2 the SLIC automatically changes to VBat ) When HB is set to logic level low in the stand-by state, the SLIC will use VBat2 for battery feed and if HB is set to logic level high , the SLIC will use the VBat for battery feed . Table 1 summarizes the description of the HB input.
Note 1 State 1 2 3 4 5 6 7 8 HB X X X X 0 0 1 1 E1 X X 0 1 0 1 0 1 C2 0 0 1 1 1 1 1 1 C1 0 1 0 0 1 1 1 1
SLIC operating state Open circuit Ringing Active Active Stand-by Stand-by Stand-by Stand-by
DET
output
Battery Feed Note 2 VBat VBat2 VBat2 VBat2 VBat2 VBat VBat Note 3 Note 3 Note 3 Note 3
Logic level high Ring trip status Ground key status Loop current status Ground key status Loop current status Ground key status Loop current status
Table 1. Slic operating states Notes 1. Input C1 and C2 selects SLIC operating state, input E1 selects detector (except in open circuit- and ringing state) and input HB selects the battery to be used for battery feed in stand-by state. X symbolises "dont care". 2. In the open circuit state the SLIC present a high impedance to the line and no battery is used for battery feed. 3. In stand-by state input HB must be set to select between VBat2 and VBat . In the other states the SLIC automatically selects the appropriate battery. V Bat > V Bat2
output.
16
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1 Ring Voltage
First we define: Crest factor =
$ V
V rms
Table 2 and 3 define the voltage over the bell under different conditions.The bell is modelled according to the USREN (Ringing Equivalence Number) standard. 1 USREN=6930 +8F @ 20 Hz, so one bell has the impedance 7 k at 20 Hz. 5REN is equal to five 1REN loads in parallel, 1386 +40F is approx. 1.4 k at 20 Hz. Load # REN RLine 1 0 3 5 1 3 5 1 3 5 100 100 0 100 100 0 100 100 Crest factor 1.41;sin 1.41;sin 1.41;sin 1.20 1.20 1.20 1.05 1.05 1.05 Load voltage 52.2 47.2 43.5 62.9 57.0 52.6 72.0 65.2 60.2
In Table 3 the required VBat to achive a specific voltage over the bell (40 or 50 V) is presented, the load is fixed at 3 or 5REN with 100 wire resistance. The high voltage ring signal from the SLIC will be balanced about VBat/2.
Note that it is important to always use PTCs in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast transients and therefore will not protect the SLIC.
Overvoltage Protection
The PBL 387 10/1 SLIC must be protected against overvoltages on the telephone line caused by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and RINGX terminals, for maximum allowable continuous and transient voltages that may be applied to the SLIC. Secondary Protection The circuit shown in figure 12 utilizes series resistors together with a programmable overvoltage protector (e. g. PowerInnovations TISP PBL2), serving as a secondary protection. The TISP PBL2 is a dual forwardconducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to negative supply voltage (i.e. the battery voltage,VB). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. CGG shall be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the VBat supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors RF serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross.
Power-up Sequence
The voltage at pin VBAT sets the substrate voltage, which must at all times be kept more negative than the voltage at any other pin to prevent possible latchup. The optimal power up sequence is ground, VBAT and then other supplies and signal leads. However, VCC may be connected before VBAT and if the VBAT supply voltage should be absent, a diod connected between VEE and pin VBAT, see diod DBE in figure 12, ensures the presence of the most negative supply voltage at the VBAT pin. The VBAT and VBAT2 pins should not be applied at a faster rate than corresponds to the time constant formed by 5,1 resistors, RBat and RBat2 in figure 12, in series with the VBAT and the VBAT2 pins and 0,47 mF capacitors, CBat and CBat2 in figure 12, from the VBAT and VBAT2 pins to ground. These RC networks may be shared with several SLICs.
Table 2. The load voltage over the bell as a function of the number of bells, line length and ringsignal shape Table 2 shows the load voltage as a function of line length, number of bells and shape of the ring signal when VBat = -80V and ringsignal=1.4Vrms. Crestfactor 1.41 corresponds to a sinusodial shape of the ringsignal, 1.20 is trapezoid and 1.05 is squarewave. The squarewaves crestfactor is not exactly one because some telephone equipment are not able to detect the steep flanks in a "perfect" squarewave. Load voltage 40 40 50 40 50 Crest factor 1.41;sin 1.20 1.20 1.05 1.05 VBat 3REN 67.2 56.4 70.5 49.4 61.3 [V] 5REN 73.0 61.2 76.1 53.2 66.8
Printed Circuit Board Layout
Care in PCB layout is essential for proper function.The components connecting to the RSN input should be placed in close proximity to that pin, such that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be connected to battery ground (BGND) on the PCB in one point.
Table 3. The required battery voltage to achive a specific voltage over the bell.
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
17
PBL 387 10/1
I L Loop current (mA) 35
A
30
B
VBat2 = -48 V, RSG = 4 k Curve A: RDC1 + RDC2 = 71.4 k Curve B: RDC1 + RDC2 = 83.3 k Curve C: RDC1 + RDC2 = 100 k Curve D: RDC1 + RDC2 = 125 k
25
C
20 15 0 500 1000 1500 R L Loop resistance (ohm) 2000
D
Figure 17. Loop current as a function of loop resistance.
VTR Tip-Ring voltage (V) 40
A
30
B
C
D
VBat2 = -48 V, RSG = 4 k Curve A: IConst = 35 mA Curve B: IConst = 30 mA Curve C: IConst = 25 mA Curve D: IConst = 20 mA
20 10 0 0 500 1000 1500 R L Loop resistance (ohm) 2000
Figure 18. Tip-ring voltage as a function of loop resistance.
IL Loop current (mA)
50 45 40 35
A B C D
VBat2 = -24 V, RSG = Curve A: RDC1 + RDC2 = 50.0 k Curve B: RDC1 + RDC2 = 62.5 k Curve C: RDC1 + RDC2 = 83.3 k Curve D: RDC1 + RDC2 = 125 k
30 25 20 15 10 5 0
500
1000
1500
2000
R L Loop resistance (ohm)
Figure 19. Loop current as a function of loop resistance.
VTR Tip-Ring voltage (V) 20
15
A B C D
VBat2 = -24 V, RSG = Curve A: IConst = 50 mA Curve B: IConst = 40 mA Curve C: IConst = 30 mA Curve D: IConst = 20 mA
10 5 0 0
500
1000 1500 R L Loop resistance (ohm)
2000
Figure 20. Tip-ring voltage as a function of loop resistance.
18
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
PBL 387 10/1
VTRO (VPeak)
2
Typ. Max.
1
0 5 6
Max. VMargin = maximum |VBat2 | - |VTRdc| required for distortion free transmission of a given VTRO.
VMargin (V)
7 8
Figure 21. Overload level, VTRO as a function of VMargin.
RL (ohm) at I L = 18mA
2200
A
B
C
D
2100
2000
1900 4 5 6 7 8 9
VBat2 = -48 V Curve A: Curve B: Curve C: Curve D:
VMargin (V)
IConst = 20 mA IConst = 25 mA IConst = 30 mA IConst = 35 mA
Figure 22. Loop resistance at IL = 18 mA as a function of VMargin at open loop.
P (W) 3
A
2
B
1
C
0 0 500 1000 1500 R L Loop resistance (ohm) 2000
Curve A: Conventional 2x400 resistive feed Curve B: PBL 387 10/1, -48 V, 30 mA Curve C: PBL 387 10/1, -28 V, 30 mA
Figure 23. Power dissipation.
1522 PBL 387 10/1 Uen Rev.E (c) Ericsson Microelectronics AB, March 2001
19
Ordering Information
Package Temp. Range Part No.
28 pin PLCC Tube 28 pin PLCC Tape & Reel
-40- +85C PBL 387 10/1QNS -40- +85C PBL 387 10/1QNT
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics general conditions of sale, unless otherwise confirmed in writing.
Specifications subject to change without notice. This product is an original Ericsson product protected by US, European and other patents.
Ericsson Microelectronics
SE-164 81 Kista, Sweden Telephone: +46 8 757 50 00 Internet: www.ericsson.se/microelectronics For local sales contacts, please refer to our website or call: Int + 46 8 757 47 00, Fax: +46 8 757 47 76
Data Sheet
1522 PBL 397 10/1 Uen Rev. E (c) Ericsson Microelectronics AB, March 2000

▲Up To Search▲

Price & Availability of PBL38710

	To Download PBL38710 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .