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DATA SHEET
MICRONAS
UAC 355xB Universal Serial Bus (USB) Codecs
Edition May 13, 2004 6251-544-2DS
MICRONAS
UAC 355xB
Contents Page 4 4 6 7 7 7 7 7 9 9 10 10 10 10 10 10 11 11 11 11 11 12 12 12 12 13 14 14 14 14 14 14 15 15 15 15 15 15 Section 1. 1.1. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.3. 2.3.1. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.7. 2.8. 2.8.1. 2.8.2. 2.9. 2.10. 2.10.1. 2.10.2. 2.10.3. 2.10.4. 2.10.5. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.12. Title Introduction Features Hardware Description General Information Universal Serial Bus (USB) Transceiver USB Interface Microcontroller GPIO GPIO Port Configurations General-Purpose Timer Audio Interface Audio Streaming Interface Audio Control Interface Serial Data Output Direct Streaming Microcontroller Streaming The UAC 355xB Serial Audio Interfaces Synchronous I2S Input/Output Asynchronous I2S Input Asynchronous I2S Input with Optional I2S Output Power Supply I2C Bus Interface I2C Master I2C Slave Microphone and Line Input Analog Output Digital-to-Analog Converters Analog Filter Analog Volume Line-out/Headphone Amplifier Subwoofer Output Special I/O SOF (Start of Frame) SEN (Suspend Enable) Suspend Reset Clock System
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Contents, continued Page 16 17 17 17 17 17 18 18 18 19 19 19 20 21 21 21 24 24 24 26 26 28 31 31 31 32 32 33 34 36 36 38 40 43 45 45 45 46 48 Section 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. 3.9. 3.9.1. 3.9.2. 4. 4.1. 4.2. 4.3. 4.3.1. 4.4. 4.4.1. 5. 5.1. 5.2. 5.3. 5.3.1. 5.3.2. 5.3.3. 5.3.4. 5.4. 5.5. 5.6. 5.6.1. 5.6.2. 5.6.3. 5.6.4. 6. 6.1. 6.2. 6.3. 7. Title Audio Processing DSP Loop Automatic Gain Control Quasi-Peak Bass Control Treble Control Parametric Equalizer Volume, Mute, and Balance Control Subwoofer Output and Bass Management Micronas Bass (MB) Dynamic Amplification Adding Harmonics Firmware Features Device Descriptor Configuration Descriptor Audio Class Requests Vendor-Specific Requests Bootloader Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Audio Pins Interface Pins Other Pins Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics I2S Interface Timing Characteristics UAC 355xB Applications Recommended Low-Pass Filters for Analog Outputs External Clocking via XTI Typical Applications Data Sheet History
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Universal Serial Bus (USB) Codecs Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction UAC 355xB is Micronas' new USB audio IC family. It contains a high-performance stereo audio ADC/DAC, digital serial interfaces, and an additional DAC channel for the subwoofer signal. The audio ADC with direct microphone and line input makes the UAC 355xB the ideal solution for all kinds of USB codec applications. This includes the replacement of analog sound cards in PCs. Integrated headphone amplifiers allow direct headphone connection. Therefore, the IC can be employed as a single-chip headset solution without an extra power supply (buspowered). Apart from the standard audio processing, such as volume, bass, and treble, the UAC 355xB offers a programmable 5-band parametric equalizer for correcting the frequency response of the applied speaker. Adjustable dynamic low-frequency processing for the subwoofer channel leads to a reduced number of external analog components. Internal sampling rate converters offer high flexibility in handling all sampling rates for USB upstream and downstream independently. The codec function of the UAC 355xB is extended by additional interfaces like I2S, allowing all kinds of digital audio processing systems to be connected to the USB (e.g., Dolby Digital or MP3 decoding chips, such as DPL 4519G, MAS 3528E, or MAS 35x9F). General-purpose inputs and outputs connect the UAC 355xB to peripheral hardware, such as buttons, keyboards, LEDs, etc. Via I2C, more complex peripherals, such as LCD displays can be controlled; and the UAC 355xB itself can be remote-controlled via I2C in non-USB environments. All-in-all, the IC is designed as an ideal connecting matrix between USB, analog and digital audio input and output, home stereo, compressed audio, and all kinds of human interface devices. Many functions are adjustable to the customer's needs. Moreover, complete firmware-plug-in download functionality of the onchip microcontroller turns the UAC 355xB into a customer-specific IC. Micronas supplies standard ROM firmware based on the USB Composite Class, Audio Class, and HID Class, one firmware for general codec applications and one firmware for headset applications. Apart from the basic versions UAC3554/3555B with Micronas' standard firmware, there is an emulator version UAC 3556B, which contains an 8 KB program RAM in addition to the program ROM. This version can Version UAC 3554B UAC 3555B UAC 3556B Description USB headset USB codec
DATA SHEET
be used for firmware development, prototyping or small quantity production. Table 1-1: Members of the UAC 355xB Family
USB codec - emulator version with internal program RAM
1.1. Features - single-chip, USB specification 2.0-compliant, stereo audio A/D and D/A converter - supports 8/16-bit mono/stereo recording and up to 24-bit playback - supports streaming of compressed audio (Dolby Digital, MP3) to external decoder - Vendor Identification and Device Configuration with external EEPROM - bus-powered and self-powered mode possible - remote wake-up - 12 general-purpose I/O pins with HID support - I2S input/output interface - independent adaptive sample rates of 6.4 to 48 kHz for USB recording and playback (enhanced full duplex) - audio baseband control: bass, treble, loudness, volume, balance, and mute - dynamic bass management Micronas Bass (MB) - digital speaker equalizer (5-band parametric equalizer) - adjustable digital active crossover filter for subwoofer - THD better than -90 dB and SNR of typically 96 dB for D/A converters - THD better than -90 dB and SNR of typically 92 dB for A/D converters - power supply rejection ratio >95 dB for analog outputs - integrated low-power stereo headphone amplifier - subwoofer output - I2C interface (master/slave) - customized firmware extensions with plug-ins possible
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UAC 355xB
HID Compressed and GPIO I2C Audio
I2S
DAC D+ D- Audio Processing Unit (APU) ADC ROM ROM RAM
Volume Volume and and Headphone Headphone Amplifier Amplifier
OUTL OUTR Subwoofer
USB Controlling
Line-in L Programmable Gain Line-in R Mic In
Fig. 1-1: Block diagram of the UAC 355xB
Active Stereo Speakers
Subwoofer USB UAC 355xB
Headset
Stereo Equipment
Multichannel Audio (e.g., Dolby Digital)
Additional DSP (MAS 3587F) Fig. 1-2: System application diagram
Digital Audio I/O (e.g., MP3)
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2. Hardware Description
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VBUS 32
D- 36
D+ 37 35
USB Transceiver Volt. Reg. USB Interface
VREG
12 17 17 18 19 20 28 27 26 25 24 23 22 21 44 31 45 46
STRB RD ADR3/GPIO11 /PWM ADR2/GPIO10 ADR1/GPIO9 ADR0/GPIO8 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 TEST TRDY RES SUSPEND
SOF
47
GPIO MicroController
XTI
2
XTO
3
Oscillator and PLL
Audio Control Interface
Audio Streaming Interface
Compressed Audio Output
Control I/O
48
SEN SCL SCA USBCLK USBDAT USBWSO DAO DAI WSI CLI MCLK
I 2C
30 29 41 43 42
MICIN ADCL ADCR
62
Select
60 59
2-Ch. ADC
Audio Processing Unit (APU)
I2S
16 13 14 15 40
MICBIAS
61 39 38
Mic Bias
3-Channel DAC
54 53
FOPR FOUTR FINR FOPL FOUTL FINL FOPS
VDD VSS AVDD AREG0 AREG1 AVSS0 AVSS1 SGND SREF
10 9 4 6 5 63 64
Supply Voltage Reg. Reference
Analog Filter
55 51 50
Analog Volume Headphone Amplifier
56 7 8
52 57
OUTS OUTL (Subwoofer)
OUTR
Fig. 2-1: Detailed block diagram of the UAC 355xB
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2.2.3. Microcontroller The microcontroller is an 8-bit RISC controller which handles the Chapter-9 processing and the decoding of class and vendor-specific USB requests. Detailed information is available in a separate document. The basic configuration is - 2 KB RAM - 12 KB ROM In addition to this, the UAC 3556B has an 8 KB RAM, which can be used instead of the lower 8 KB ROM for emulation purposes or as a RAM extension to the standard 2 KB RAM. In the emulation mode, the UAC 3556B loads the 8 KB RAM via I2C from an external EEPROM, disables the lower 8 KB ROM afterwards, and restarts the microcontroller, executing the code from RAM. Another part of the RAM is reserved for download plug-ins. This is available in both UAC 3554B and UAC 3556B, and allows the addition of smaller portions of code to the basic firmware for extended functions or workarounds, if necessary. One example is adding extra functions to the GPIO pins, like control of external components via USB. Downloading of the plug-in can be done either from the USB host with an extra driver or from an external I2C EEPROM.
2.1. General Information This description summarizes all hardware platform capabilities of the UAC 355xB. The function of a certain application, however, is defined in the microcontroller's firmware. This is explained in Section 4. "Firmware" on page 20 for the standard codec and headset firmware. The basic functions (playback, recording, audio control, HID) of the UAC 355xB can entirely be used by any USB operating system without additional drivers. However, the IC offers far more functionality if vendorspecific controlling or download code is used. With external I2C controlling, the IC can even work as an audio codec in a non-USB environment. The use of this complete functionality is not described in the standard data sheet and can be found in separate application notes (www.micronas.com). A detailed block diagram of the UAC 355xB is depicted in Fig. 2-4. The functions of the blocks are explained in the following sections. 2.2. Universal Serial Bus (USB) 2.2.1. Transceiver The differential input transceiver is used to handle the USB data signal according to the full-speed (12 MB/s) USB driver characteristics (USB SPEC 2.0). This block is supplied by an internal voltage regulator. The internal pull-up resistor on the D+ line, indicating that the UAC 355xB is connected to the USB bus, can be switched on and off by firmware. 2.2.2. USB Interface The USB interface does all the low-level USB protocol handling, such as NRZI coding, bit stuffing and CRC computation. A receiver/transceiver logic handles the data traffic between the USB bus and the microcontroller memory.
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(Address is driven by UAC 355xB)
GPIO[11:8] GPIO[7:0] RD STRB
83 ns
Address
(External device drives data lines)
Data
166 ns
(typical)
UAC 355xB reads data here GPIO Address Mode: Read Fig. 2-2: UAC 355xB parallel interface timing (read)
(Address is driven by UAC 355xB)
GPIO[11:8] GPIO[7:0] RD STRB
83 ns
Address
(UAC 355xB drives data lines)
Data
166 ns
(typical)
valid data GPIO Address Mode: Write Fig. 2-3: UAC 355xB parallel interface timing (write)
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2.3.1. GPIO Port Configurations The UAC 355xB can set the GPIO port into different configurations. Standard mode In this mode the GPIO[0...11] pins are used as normal I/O pins, which can be set or read from the microcontroller. Address mode In this mode the GPIO pins can be used in a memory mapped fashion. There is a 16-Byte range of the microcontrollers address space which is transparent to the GPIOs. GPIO[0...7] are mapped to the data bus and GPIO[8...11] are mapped to the lower four bits of the address bus.
2.3. GPIO There are two groups of different types of GPIOs: - Input and output pins: GPIO[0...11] - Control pins: RD, STRB The port pins can also be set into different electrical states: - weak or strong driver strength - output or tristate - internal pull-down on or off There are two GPIO pins with special alternate functions (see Table 2-1) - GPIO[10] - Start Timer - GPIO[11] - PWM Output A description of these functions can be found in Section 2.4. "General-Purpose Timer" on page 10.
Table 2-1: GPIO port configurations Pin Name GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] Standard Mode Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O - Generic I/O - Start timer GPIO[11] - Generic I/O - PWM out RD no function Shows I/O direction Read (high level) input Write (low level) output - timing diagram Strobe pulse, marks valid data Addr [3] Address Mode Generic parallel I/O Generic parallel I/O Generic parallel I/O Generic parallel I/O Generic parallel I/O Generic parallel I/O Generic parallel I/O Generic parallel I/O Addr [0] Addr [1] Addr [2]
STRB
no function
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2.4. General-Purpose Timer The UAC 355xB audio codec family incorporates a timer. It is a 16-bit counter with clock prescaler. The clock runs at 12 MHz. The prescaler can be set to divide by 1 to 256. The current value of the counter can always be read back. The timer initiates interrupts on reaching the count value MaxA. The UAC 355xB can start the timer with a "high" level on GPIO[10]. The timer can be switched to PWM generation to configure GPIO[11] as PWM output. The structure of the timer is shown in Fig. 2-4. The PWM output and timer frequencies can be calculated as shown in Figure 2-5. 2.5. Audio Interface 2.5.1. Audio Streaming Interface
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The audio streaming interface directly connects the USB interface to the APU in order to transmit the digital audio data in both directions for playback and record. The following data formats are supported: Table 2-2: Audio Formats Playback 16-bit MONO 16-bit STEREO 24-bit STEREO Record 8-bit MONO 16-bit MONO 16-bit STEREO
2.5.2. Audio Control Interface The Audio Control Interface links the microcontroller to the APU and is used to initialize the APU and to transmit audio-related USB control data, such as volume setting, tone control etc. The Audio Control Interface supports full access to all APU registers via microcontroller. 2.5.3. Serial Data Output
Timer Interrupt PWM GPIO[11]
GPIO[10]
EXT_ENB
Control
12 MHz Prescaler
Tclk Counter
Used Pins: USBCLK, USBDAT This interface provides a data path for transferring compressed audio to peripheral ICs, such as Micronas' Dolby Digital decoder MAS 3528E or to an MP3 decoder, e.g., the MAS 3507D or MAS 3509F. This works independently from the normal USB playback. The audio format on the USB-OUT pins is burst I2S. Note: If this interface is used, the "Asynchronous I2S input with optional I2S output" is not available and vice versa.
Max A
Max B
Fig. 2-4: Timer structure
Timer frequency: Tclk = 12 MHz / Prescale PWM frequency: PWM = Tclk / (MaxA + MaxB) MaxA MaxB MaxA MaxB
This interface operates in different modes: 2.5.4. Direct Streaming In this mode, there is no preprocessing of the timing, i.e., the data on USBDAT are in phase with the 12 MHz data on the USB bus, which are sent to a specific endpoint. This can be bulk or isochronous data. The data appear as they are sent on the USB bus.
Fig. 2-5: PWM timing
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2.6.2. Asynchronous I2S Input Used Pins: DAI, WSI, CLI In this mode the UAC 355xB is slave, i.e., asynchronous input is possible at a sampling rate range from 6.4 kHz to 48 kHz. The external I2S source provides DAI, WSI, and CLI
2.5.5. Microcontroller Streaming In this mode, the microcontroller copies the data from the RAM to a shift register, which is connected to the USBDAT pin. The shift clock can be programmed between 6 MHz and 750 kHz and appears on USBCLK pin. 2.6. The UAC 355xB Serial Audio Interfaces Used Pins: DAO, DAI, WSI, CLI, USBDAT, USBCLK The UAC 3556B offers two digital serial interfaces (I2S). They are directly connected to the APU. The I2S interfaces operate in 16-bit or 32-bit mode. The master clock (MCLK) is programmable to 18.432 MHz, 24.576 MHz or 36.864 MHz. Delayed word strobe or standard I2S format can be selected via the programmable delay bit. Word strobe polarity is programmable, too. Detailed timing diagrams can be found in Section 5.6.4. "I2S Interface Timing Characteristics" on page 43. 2.6.1. Synchronous I2S Input/Output Used Pins: DAO, DAI, WSI, CLI In this mode, the UAC 355xB is master on the I2S, i.e, it generates WSI and CLI for a fixed 48 kHz sampling rate. External I2S sources must deliver data synchronous to the output.
UAC 355xB
DAI CLI WSI asynchronous input
Fig. 2-7: Asynchronous I2S input 2.6.3. Asynchronous I2S Input with Optional I2S Output Used Pins: Output: USBDAT, USBCLK, USBWSO Input: WSI, CLI, DAI In this mode, the I2S burst interface pins USBDAT, USBCLK and USBWSO can be used for synchronous I2S output (if the burst interface is not used), as described in Section 2.6.1. The I2S input pins WSI, CLI, DAI, however, operate asynchronously as described in Section 2.6.2.
DAI CLI
UAC 355xB
WSI DAO
synchronous input/output
USBDAT USBCLK UAC 355xB USBWSO DAI CLI WSI Fig. 2-8: Asynchronous I2S input with optional I2S output asynchronous input synchronous output
MCLK (optional) Fig. 2-6: Synchronous I S Input/Output
2
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2.7. Power Supply The UAC3554/6B has on-chip voltage regulators providing the optimal supply voltages for the analog and digital sections, thus allowing to power the IC by the USB Bus supply lines, as well as from external supply. They also serve to reduce cross-talk and EMI. For stable operation, all regulators need external capacitors. The regulators are 1. VREG: 3.4 V regulator for USB-signalling (saving external regulator) 2. AREG0: 3.5 V regulator for analog back-end 3. AREG1: 3.5 V regulator for analog circuitry apart from backend. Reference voltage for analog signals: SREF: 1.7 V (optional 2.3 V) reference voltage for analog circuitry. Note: It is recommended for AVSS0/1, SGND and VSS to be connected. In certain applications, however, it may be better to split signal ground from the other grounds in order to reduce noise. 2.8. I2C Bus Interface Pins: SDA, SCL
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The UAC 355xB is equipped with an I2C bus master/ slave interface. Bus format and timing follow the original specification for I2C (The I2C Specification V2.1). It operates with 5 V signalling at 100 kHz or 400 kHz. Both master and slave mode require support from the microcontroller firmware. 2.8.1. I2C Master This mode allows control of external I2C devices, such as EEPROMs, LCD-Displays etc. This interface is used to download configuration data and firmware from an EEPROM after power-up. The bus protocol (subaddressing and packet length) is defined by firmware and therefore programmable. Note: Micronas standard firmware (Section 4. "Firmware" on page 20) provides support for USB to I2C bridging, allowing control of I2C devices via USB.
2.8.2. I2C Slave In I2C slave mode, the interface provides an interrupt to the microcontroller after detecting the assigned I2C address (0x48). The corresponding interrupt service routine handles this request and interprets incoming data according to the application. One example of handling could provide full access to all memory locations.
Five-Volt Mode If a higher output level is required, the IC can operate in 5 V mode. In this case, the IC is powered from an external 5 V supply: AVDD has to be connected to AREG0 and AREG1 and SREF must be switched to 5 V mode.
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The input gain for the line input is programmable in the range of -3 dB to 19.5 dB. Table 2-4 shows the line input voltage versus gain setting and the input impedance (depends on gain setting) for full range ADC input (clipping level). After A/D conversion, there is a digital quasi-peak meter providing level information in APU register. If Mic input is selected, there is the option to switch the signal to both channels. In this case, the left channel is copied to the right channel after the peak meter.
2.9. Microphone and Line Input Pins: ADCR, ADCL, MICIN, MICBIAS The UAC 355xB provides a 2-channel ADC. The A/D converters achieve a signal-to-noise ratio better than 90 dB (typ.) and a bandwidth of 20 kHz (at fs=48 kHz). The left channel can be used as microphone or line input, whereas the right channel is always line input. Programmable input gain allows adaption of the input levels to the ADC range. The UAC 355xB allows direct connection to an electret microphone and provides the microphone bias voltage of 3.1 V (0.5 mA max.) on a separate pin, too. The microphone bias is automatically switched on when the microphone input is selected. The output resistance of the MICBIAS pin is typically 180 . There is a fixed +21.5 dB gain followed by a programmable gain of 0 dB to +22.5 dB. Table 2-3 shows the microphone voltage versus gain setting and the input impedance (depends on gain setting) for full range ADC input (clipping level).
Mic-Bias Mic
L Preamp
Q-Peak
A D A D
Mono
Line
R
Fig. 2-9: Analog input configuration
Table 2-3: Microphone input levels
Microphone Voltage [mVPP] 3 V Mode 283 238 200 168 142 119 100 84 71 60 50 42 36 30 25 21 Microphone Voltage [mVPP] 5 V Mode 377 317 267 225 189 159 134 113 95 80 67 56 47 40 34 28 Gain Setting [dB] Input Impedance [k] 137 117 100 85 72 62 52 44 37 32 27 23 19 16 14 11
Table 2-4: Line input levels
Line Input Voltage [mVpp] 3 V Mode 3388 2851 2399 2018 1698 1429 1202 1011 851 716 602 507 427 359 302 254 Line Input Voltage [mVpp] 5 V Mode 4517 3801 3198 2691 2264 1905 1603 1349 1135 955 803 676 569 478 403 339 Gain Setting [dB] Input Impedance [k] 85 79 73 67 61 55 49 44 39 34 30 26 23 19 17 14
0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 16.5 17 19.5 21 22.5
-3 -1.5 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 16.5 17 19.5
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2.10. Analog Output Pins: OUTL, OUTR, OUTS FOPL, FOPR, FOUTL, FOUTR, FINL, FINR, FOPS The analog output system comprises the stereo audio DAC, the subwoofer DAC, analog filters, op-amps for external out-of-band-noise filters, analog volume, mute, and the output amplifiers. 2.10.1. Digital-to-Analog Converters The UAC 355xB uses three multibit sigma delta DACs with high linearity and SNR better than 95 dBA. 2.10.2. Analog Filter AVSS Pins: FOPL, FOPR, FOUTL, FOUTR, FINL, FINR, FOPS This block contains the op-amps for the optional analog external out-of-band-noise filters. It is recommended to use a second-order filter for the main channels (OUTL, OUTR) (see Section 6. "UAC 355xB Applications" on page 45). It is possible to omit these filters and to save the external components. In this case, the op-amp has to be switched off and the pins FOOTL/R, FINL/R and FOPL/R must be connected. The output signal will contain more out-of-band noise, which is not audible, however. A first-order filter is required for the subwoofer output in order to attenuate the out-of-band noise caused by the sigma delta DACs. 2.10.3. Analog Volume The analog volume covers a range from +6 dB to -18 dB with 1.5 dB step size. This is the analog component of the overall volume system which covers a range from +12 dB to -114 dB with 1 dB step size and additional mute position. It is split into analog and digital volume. This splitting ensures that the DAC performance parameters do not degrade at reduced volume settings. The splitting is embedded in the audio processing and cannot be modified. Note: Positive volumes will degrade the THD at high input levels. OUTR 2.10.4. Line-out/Headphone Amplifier Pins: OUTL, OUTR Stereo Mode
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The line-out/headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or to a power amplifier. The stereo headphones require external serial resistors in both channels. See Section 6. "UAC 355xB Applications" on page 45.
OUTL
AVSS Fig. 2-10: Loudspeaker connection for Stereo mode Mono Mode In Mono mode, the DC coupling capacitors and further filter circuitry are not required. In this mode, the output pins OUTL/R operate in bridge mode with complementary signals. Therefore, the maximum output power increases, allowing small speakers to be driven directly.
OUTR
OUTL Fig. 2-11: Loudspeaker connection for Mono mode 2.10.5. Subwoofer Output Pins: OUTS The subwoofer output is designed for driving an external amplifier. The audio processing provides a programmable split filter and active bass management algorithms. Note: If the capacitive load is too high, a serial resistor is required.
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2.11. Special I/O Pins: SOF, SEN, SUSPEND, RESET The following sections describe some pins with special functions. 2.11.1. SOF (Start of Frame) The SOF pin provides a 1 ms periodic signal which is derived from the USB frame rate. It can be used for test purpose or as an USB-synchronous reference for vendor-specific external circuitry. 2.11.2. SEN (Suspend Enable) Pin: SEN This is a digital input that prevents the device from entering the low-power mode (Suspend). The UAC 355xB enters a low-power mode if: - there is J-state on D+, D- lines (USB-Suspend) and V bus high - V bus is low (USB disconnected)
Table 2-6: SUSPEND pin SUSPEND high low normal power low power
2.11.4. Reset Pin: RES The RES pin resets the UAC 355xB. During power-up the RES pin should be low until the clock system is up and running. Then this pin can be released and the UAC 355xB enters normal operating mode. Note: In low-power mode, the RES pin must not be low to avoid restart of the clock system and therefore entering normal power mode.
90%
Note: Both cases must be supported by the firmware In case of USB-Suspend, the SEN pin is also used as an input for the remote wake-up function.
AVDD VDD
RES Table 2-5: SEN pin SEN high low suspend enabled suspend disabled/remote wake-up 2.12. Clock System Pins: XTI, XTO 2.11.3. Suspend Pin: SUSPEND The SUSPEND pin is a digital output pin which indicates the low-power mode. It can be used to power down external circuitry, such as power amplifiers in a USB speaker.
20 ms
Fig. 2-12: Timing diagram of the reset procedure
The UAC 355xB requires a 12 MHz clock source, which is realized as an on-chip oscillator with external crystal. Also an external oscillator can be used. In this case, the clock has to be connected to XTI (see also Section 6. "UAC 355xB Applications" on page 45). The 12 MHz is the input clock for a PLL circuit which generates all clocks needed within the IC. The clock for the APU is programmable either to 48 MHz or 72 MHz. In case of 48 kHz, the UAC 355xB consumes less power, but on the other hand a reduced feature set for the audio processing has to be taken into account (see Fig. 3-1 on page 16).
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3. Audio Processing
Mic-Bias Mic
L Preamp
A D A D
Mono
Deemphasis off/50 s/75 s
USB
AGC
Treble/ Loudness
EQ
USB (downstream)
mix I2S
Complementary High Pass
Balance
Select
Select
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Q-Peak
ADC DSP-Loop mix Bass/ Mono/ Stereo + Right Invert Vol.
Line
R
dashed blocks not available in reduced feature set D A D A
Level
L
R
Low Pass Q-Peak
Vol.
MB
Adjust
D A
Subwoofer
I2S
mix I S Synchronous Mode only in reduced feature set
2
complete mix ADC+USBmix ADC input USB L/R
5 4 0 1 2 Scale
USB (upstream)
I2S input complete mix ADC+USBmix ADC input USB L/R
3 5 4 0 1 2 Scale
I2S out
I2S input
3
Fig. 3-1: Signal flow in the audio processing unit (APU)
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Micronas
DATA SHEET
UAC 355xB
The audio processing is realized by APU firmware. The audio building blocks can be split into USB-independent features such as parametric equalizer, I2S I/O, and blocks which belong to USB feature units, mixer units, and selection units defined in the USB Device Class Definition for Audio Devices. The USB feature unit provides basic manipulation of the incoming logical channels and can be controlled by the standard windows mixer tool. The parameters for the USB-independent features are predefined in the internal ROM, in an external EEPROM or a special host application which drives the IC. The UAC 355xB supports two logical channels (i.e. left and right) and a subwoofer channel which is derived with a split filter from left and right. Multichannel or surround systems, however, can also be realized using more than one UAC 355xB, because phase or delay distortion is eliminated in the device by locking the audio processing to the USB frame rate. An overview of the architecture is given in Fig. 3-1 on page 16. If the APU works with a 48 MHz clock it is necessary to select the reduced feature mode. The blocks, which are not available in reduced feature mode are shown with dashed lines in Fig. 3-1 on page 16. 3.1. DSP Loop The DSP-Loop block symbolizes the option to route the audio signal to an external DSP and back into the UAC 355xB via IS I/O. This allows to add more audio processing algorithms. 3.2. Automatic Gain Control The Automatic Gain Control (AGC) is one of the building blocks of the feature unit (USB Device Class Definition for Audio Devices 1.0, page 39). Different sound sources fairly often do not have the same volume level. The Automatic Gain Control solves this problem by equalizing the volume levels within a defined range. Below a threshold level the signals are not affected. The level-adjustment is performed with time constants in order to avoid short-time adjustments due to signal peaks.
Output Level dBr
-9 -15 -21
AGC off AGC on
-30
-24
-18
-12
-6
0
+6 dBr Input Level
Fig. 3-2: Simplified AGC characteristics Table 3-1: AGC parameters Parameter Decay time Settings 8 seconds 4 seconds 2 seconds 20 ms Default 4 seconds
3.3. Quasi-Peak Two quasi-peak detectors are provided: 1. after the ADCs. This allows the programming of an AGC in the microcontroller1) or a VU-meter on the host side. 2. in the DAC channel. This can be used, e.g., for a VU-meter on the host side. The feature is based on using fast attack and slow decay time constants. 3.4. Bass Control The bass control provides gain or attenuation to frequency components below a corner frequency of 120 Hz. The bass control works identically on both channels in a range of -12 dB to +12 dB. 3.5. Treble Control The treble control provides gain or attenuation to frequency components above a corner frequency of 6 kHz. The treble control works identically on both channels in a range of -12 dB to +12 dB.
1) not supported by standard microcontroller firmware
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3.6. Parametric Equalizer The parametric equalizer is an audio feature which is not accessed via standard USB controls. It allows the compensation of the frequency response of a speaker. Alternatively, frequency responses can be set to suit individual tastes. The equalizer consists of 5 individually adjustable bands. The control parameters and the parameter range for each band is shown in Table 3-2. Table 3-2: Equalizer parameters Parameter Center Frequency Gain/Attenuation Filter Quality (Q) Min. 50 Hz -6 dB 0.5 Max. 15 kHz +6 dB 3
DATA SHEET
the D/A converter will not be overloaded, even with fullscale input signals. The subwoofer is filtered by a thirdorder low-pass filter with programmable corner frequency and programmable characteristic followed by a level adjustment. At the main channels a complementary high-pass filter can be switched on. Subwoofer and main output use the same volume. Please note, that the predefined subwoofer parameters in the internal ROM are set in such a way, that the low frequencies of both channels are summed up and are distributed equally to left and right channel. This reduces the risk of overload of the speakers, but degrades the channel separation for low frequencies. Since the human perception cannot extract information about direction from low frequencies, this is no drawback.
5
medium
sharp
The adjustment of the equalizer is supported by an application program that allows to set up frequency responses and to download the corresponding filter coefficients into the UAC 355xB. When the frequency response matches the requirements, it can be programmed into the external EEPROM or can be set by a vendor specific device driver. The UAC 355xB is shipped with a flat frequency response. 3.7. Volume, Mute, and Balance Control
0 -5 10 15 20 25
very soft soft
The volume control is partly realized in the analog back-end. This preserves high audio quality (SNR) at low volume settings because signal and noise are attenuated in the same way. This is not the case for devices with pure digital volume control. The UAC 355xB uses digital volume control only for the fine tuning. The volume setting is smoothed by an internal ramping algorithm in order to avoid audible clicks during volume change. The splitting between analog and digital volume is handled by the UAC 355xB automatically. The balance is implemented digitally by attenuating one channel. The mute control is part of the volume system in the UAC 355xB. It functions simultaneously on both channels and can be switched on and off under USB control. Similar to the volume control, clicks are avoided by a ramping algorithm. 3.8. Subwoofer Output and Bass Management The subwoofer signal is created by combining the left and the right channels directly behind the equalizer block using the formula (L+R)/2. Due to division by 2,
200. f
2000
Fig. 3-3: Subwoofer characteristics (e.g. fc = 200 Hz)
Table 3-3: Subwoofer parameters Parameter Corner Frequ. Characteristic Settings/ Range 50 to 400 Hz - sharp edge - medium edge - soft edge - very soft edge Default 90 Hz sharp edge
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DATA SHEET
UAC 355xB
3.9.1. Dynamic Amplification Since the human impression of loudness depends on the frequency, a dynamic compression of the low frequencies adapts the sound to the human perception. In order to prevent clipping and to adapt the system to the signal amplitude which is really present at the output of the device, the MB contains a definable limit. The output signal amplitude is monitored and if it comes close to the limit, the gain is reduced automatically. Clipping effects are avoided.
Table 3-3: Subwoofer parameters, continued Parameter Complementary High-Pass Filter for L/R channel Settings/ Range - L/R unfiltered - L/R high-passfiltered - Subw. added to high-passfiltered L/R Level Adjustment Subw. DAC -60...+12 dB (relative to main volume) - off - on 0 dB Default Subw. added to high-passfiltered L/R
3.9. Micronas Bass (MB)
MB_CF SUBW_FREQ
Frequency
The Micronas Bass algorithm (MB) implements a sophisticated bass boost system, which extends the frequency range of loudspeakers or headphones. The MB is placed in the subwoofer path. For applications without a subwoofer, the enhanced bass signal can be added back onto the left/right channels. Micronas Bass combines two effects: dynamic amplification and adding harmonics. Several parameters allow tuning the characteristics of MB according to the loudspeaker, the cabinet, and personal preferences. For more detailed information on how to set up MB, Micronas will provide an appropriate Application Note. Table 3-4: MB parameters Parameter Effect Strength Harmonic Content Center Frequency Amplitude Limit Subwoofer Settings Range off...max 0...100% 20...300 Hz -32...0 dBFS Default if disabled off 0% 90 Hz 0 dBFS (=no limit) Default if enabled medium
Fig. 3-4: Dynamic amplification 3.9.2. Adding Harmonics MB exploits the psychoacoustic phenomenon of the `missing fundamental'. Adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental. In other words: Although the loudspeaker system is not capable of generating such low frequencies, the listener has the impression that it reproduces them.
Amplitude (db)
Frequency
50% 90 Hz 0 dBFS (=no limit)
MB_CF
Fig. 3-5: Adding harmonics
two sets for MB off/on available, for parameters see Table 3-3
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Signal Level
on
MB_LIMIT
Amplitude (db)
19
4. Firmware
Mic-Bias Mic
L Preamp
A D A D
Mono
Deemphasis off/50 s/75 s
Balance
Select
Select
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Q-Peak
ADC-mix only for headset firmware ADC
Line
R
mix Bass/ USB AGC Treble/ Loudness mix I 2S Low Pass Q-Peak mix MB
Adjust Complementary High Pass
switch to Line-L only for Codec Firmware
EQ
USB (downstream)
Mono/ Stereo + Right Invert
Vol.
D A D A
R L
Level
Vol.
D A
Subwoofer
I2S
complete mix ADC+USBmix ADC input
USB L/R
5 4 0 1 2 Scale
USB (upstream)
I2S input complete mix ADC+USBmix ADC input USB L/R
3 5 4 0 1 2 Scale
I2S out
I2S input
3
Fig. 4-1: Signal flow in the audio processing unit controlled by the codec/headset firmware using standard OS driver
DATA SHEET
Micronas
DATA SHEET
UAC 355xB
Table 4-1: Programmable Device Descriptor Items
Item idVendor Default UAC 3555B 0x074D 0x3554 0x000x1) 0x01 0x02 0x00 Default UAC 3554B 0x074D 0x3554 0x00041) 0x01 0x02 0x00
The previous chapters describe the UAC 355xB from the hardware point of view. The complete functionality, however, is defined by the microcontroller firmware. This firmware tailors the device to a specific application. Micronas offers two standard firmware versions embedded in the ROM. - UAC 3555B: Standard Codec - UAC 3554B: Standard Headset Note: It is possible to customize many parameters (IDs, strings, equalizer setting etc.) by means of an external EEPROM.
idProduct bcdDevice iManufacturer iProduct iSerialNumber
1)
Changes with firmware revisions
Both firmware versions are very similar. Differences are mentioned in the following chapters. 4.1. Features The main features of the standard firmware versions are - USB playback and record with independent sample rates - Sample rates from 6.4 kHz to 48 kHz - Microphone or Line input (only mic for UAC 3554B) - Audio baseband processing including dynamic bass management and subwoofer split filter - Basic audio control by GPIO-HID - Suspend mode and remote wake-up support - I2C master/slave support - Bootloader permitting download of configuration data, plug-ins or complete firmware (only for UAC 3556B) after power-on - Plug-in support (downloadable firmware extensions from external EEPROM or WIN driver). Most of the functions are defined in the device and configuration descriptor. The following chapters provide all noteworthy information, which is buried in this descriptors. It is assumed that the reader is familiar with the basic USB notation (USB Spec 2.01/ www.usb.org). 4.2. Device Descriptor The device descriptor contains the downloadable IDs and the index for several strings.
Associated to the string index there are three programmable strings. The ROM firmware defines only two: Table 4-2: Strings
String Manufacturer String Product String Default UAC 3555B Micronas UAC 3555B Default UAC 3554B Micronas Micronas USB Headset
4.3. Configuration Descriptor The configuration descriptor contains information on the bus/self-powered and remote wake-up capabilities. The UAC 355xB allows all combinations of these features. There is also a string index, allowing to associate a string to this configuration. The default string is a date code (time of code assembly). These items are programmable: Table 4-3: Programmable Configuration Descriptor Items
Item iConfig bmAttributes Default UAC 3555B 0x01 0xe0 (self-powered, remote wake-up) 0 (0 mA) Default UAC 3554B 0x01 0x80 (bus-powered) 50 (100 mA)
MaxPower
The configuration descriptor also provides all information concerning the audio flow in the Class Specific Audio Control Interface. Fig. 3-1 on page 16 shows the graphical representation for the codec firmware.
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DATA SHEET
EP1
USB
IT ID12
MU
Volume,Mute, Bass,Treble BassBoost AGC FU
Playback
OT ID14
D/A
Mic
IT ID10
FU Volume, muteID6 analog gain
SU ID8 "dummy units" MU ID7 ID2 ID9 analog+digital
ID1
Associated Input Terminals IT ID11
Sidetone Mixer
EP4
FU Volume analog
WIN MAC
Mic
OT ID13
USB-Up
Record
Fig. 4-2: Standard headset audio signal flow
EP1
Volume,Mute, Bass,Treble BassBoost AGC FU ID1
Playback
OT ID14
USB
IT ID12
D/A
Mic
IT ID11
FU Volume analog gain FU Volume analog gain ID3 ID2
SU
EP4 FU Volume Mute ID5 OT ID13
USB-Up
Line
IT ID10
ID8
Record
Fig. 4-3: Standard codec audio signal flow
These are the audio structures and how they appear to the USB host. Without any additional drivers the Microsoft Windows operating system provides sliders in the mixing tool to control volume setting, selectors etc. Using a vendor-specific application, however, it is possible to extend this to the full signal routing capabilities (see Section 3.1. on page 17). Static modifications (without sliders), such as - adding a sidetone path (analog-in to analog-out) to the codec firmware - adding I2S I/O can be achieved by plug-ins from external EEPROM or Windows device driver. The mixing unit MU7 in the headset firmware is a dummy unit and allows the WIN operating system to parse the descriptor correctly. Mac OS does not recognize the recording path if MU7 is present. For that reason it is possible to "short-cut" MU7 with an EEPROM based switch.
The mapping of this audio structure to the overall audio processing in the APU is shown in Fig. 4-1 on page 20. The dashed lines show signal paths which cannot be activated by standard Windows drivers and need support of vendor-specific drivers and applications (driver available from Micronas), especially for I2S input/output. Note: BassBoost enables a dynamic bass management algorithm with programmable (external EEPROM) characteristics.
The next part of the configuration descriptor defines the audio format for playback and record, which is different for codec and headset firmware. This is not programmable.
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DATA SHEET
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Table 4-4: Supported audio formats for codec (UAC 3556B & UAC 3555B Playback 16-bit Mono 16-bit Stereo Record 8-bit Mono 16-bit Mono 16-bit Stereo
Table 4-7: Extended key configuration for codec firmware Pin GPIO4 GPIO5 GPIO6 GPIO7 Function Next Track Previous Track Stop Play/Pause not used not used not used not used
Table 4-5: Supported audio formats for headset (UAC 3554B) Playback 16-bit Mono 16-bit Stereo 24-bit Stereo 16-bit Mono Record
GPIO8 GPIO9 GPIO10 GPIO11
Note: The media control keys GPIO4..7 do not work with all PC audio players!
The UAC 355xB accepts all sample rates from 6.4 kHz to 48 kHz independently for playback and record. The final portion of the configuration descriptor defines the HID functions: The firmware uses the GPIO pins to connect keys which are related to the USB HID class. The standard configuration defines the GPIO0 to GPIO3 as input pins for the audio control shown in Table 4-6. Table 4-6: Standard key configuration for codec and headset firmware Pin GPIO0 GPIO1 GPIO2 GPIO3 Function Volume Up Volume Down Mute on-off toggle BassBoost on-off toggle
Table 4-8: Extended key configuration for headset firmware Pin GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 Function local MIC mute toggle HID-Report on/off (1=HID-off) not used Mic AGC on/off (1=MIC AGC on) not used not used Speaker mute LED (1=muted) local mic mute LED - 0.5s blink if muted
Note: HID on/off and AGC on/off switch must be used as static, hardwired configuration pins. The HID-keys are polled every 1 ms by the microcontroller and the corresponding key codes are transmitted to the host on request when a key enters "high" state. The hosts polling rate is 8 ms. This parameter, however, is part of the configuration set, which can be downloaded from an external I2C EEPROM. GPIO4...11 pins are used differently in codec and headset firmware:
The local mic-mute works independently from the WIN-mixer settings and is not reported to the host. During local mic-mute the mixer settings do not affect the UAC 3554B, only after local mic-mute UAC 3554B goes back to the actual WIN-mixer settings. Sidetone level is also muted with local mic-mute.
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4.3.1. Audio Class Requests Both codec and headset firmware support all audio class requests which are required by the audio flow shown in Fig. 4-2 and Fig. 4-3. The MIN/MAX/RES setting follow the limits which are defined in the audio processing apart from the main volume setting (FU1). In this case the overall range from -114 dB to +6 dB is limited to -40 dB to +3 dB (plus mute position) in order to fit the audible range to the volume slider in the WIN mixer. 4.4. Vendor-Specific Requests These requests provide functions which extend standard controlling of the operating system. Micronas provides a driver for Windows-operating systems1) which supports: - SET MEM This request allows writing all RAM and Register locations on the chip. - GET MEM This request allows reading all memory locations on the chip. Block read is supported. - SET I2C This vendor request allows driving the I2C-master in the codec firmware. It allows writing to external I2C devices. - GET I2C This request supports I2C master reading from external devices. 4.4.1. Bootloader
DATA SHEET
The bootloader is a part of the firmware which allows communication with an external I2C EEPROM. The bootloader runs immediately after power-on. At this time the device is not connected to the USB bus. When the bootloader is finished, the pull-up resistor is switched on the D+ line. If no external EEPROM, according to the configuration shown in Table 4-10 is found, the UAC 355xB continues with the internal ROM code. After download of a complete firmware (UAC 3556B only), the bootloader resets the device and the code that was just downloaded is executed. The UAC 355xB can have different EEPROMS connected to the I2C bus. The UAC 355xB works as an I2C bus master at this point in time. Depending on EEPROM size, the EEPROM can hold different content. Various I2C EEPROM configurations can be used by means of bootstrap options at the pins USBDAT, USBCLK, and USBWSO: Table 4-9: Supported I2C EEPROM types EEPROM size 2 kbit 4...32 kbit 64 kbit 128 kbit Purpose Configuration (incl. VID/PID) Configuration Plug-in software Configuration On reset loadable firmware Configuration On reset loadable firmware Plug-in software
Note: UAC 3554B and UAC 3555B cannot load external firmware, only configuration and plug-ins.
1) for MAC and Linux also available
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DATA SHEET
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Table 4-10: I2C-Mode of external EEPROM USBWSO 1 1 USBDAT 1 0 USBCLK don't care don't care 0x50 1 byte subaddressing (UAC 3554B and UAC 3555B only) 0x51 2 byte subaddressing Address Subaddress Purpose internal ROM only I2C master disabled Configuration data Plug-in software 100 kHz I2C master Configuration data On reset loadable firmware Plug-in software 400 kHz I2C Configuration data On reset loadable firmware Plug-in software 400 kHz I2C Configuration data On reset loadable firmware Plug-in software 100 kHz I2C Configuration data On reset loadable firmware Plug-in software 100 kHz I2C
0
1
0
0
1
1
0x52 2 byte subaddressing
0
0
0
0x51 2 byte subaddressing
0
0
1
0x52 2 byte subaddressing
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5. Specifications 5.1. Outline Dimensions
DATA SHEET
Fig. 5-1: PMQFP64-2: Plastic Metric Quad Flat Package, 64 leads, 10 x 10 x 2 mm3 Ordering code: QI Weight approximately 0.5 g
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DATA SHEET
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Fig. 5-2: PQFN64-1: Plastic Quad Flat Non-leaded package, 64 pins, 9 x 9 x 0.85 mm3, 0.5 mm pitch Ordering code: XK Weight approximately 0.23
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UAC 355xB
5.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant VSS = if not used, connect to VSS OBL = obligatory; connect as described in circuit diagram VDD = connect to VDD
DATA SHEET
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1)
Pin Name NC XTI XTO AREG1 AVSS1 AVSS0 OUTL OUTR AREG0 AVDD RD1) STRB1) DAI WSI1) CLI1) DAO1) ADR3/GPIO 11/ PWM1) ADR2/GPIO 101) ADR1/GPIO 91) ADR0/GPIO 81) GPIO 71) GPIO 61) GPIO 51) GPIO 41)
Type
Connection
(If not used)
Short Description Not Connected Quartz Oscillator Pin 1 Quartz Oscillator Pin 2 Regulator Output for analog parts except amplifiers (supply voltage input for 5 V mode) VSS 1 for analog parts except amplifiers VSS 0 for audio output amplifiers Audio Output: headphone / speaker Left Audio Output: headphone / speaker Right Regulator Output for audio output amplifiers (supply voltage input for 5 V mode) analog VDD GPIO Read GPIO Strobe I2S Data Input I2S Word Strobe I2S Bit Clock I2S Data Output HID IO 11 HID IO 10 HID IO 9 HID IO 8 HID IO 7 HID IO 6 HID IO 5 HID IO 4
LV IN OUT OUT/IN IN IN OUT OUT OUT IN OUT OUT IN IN/OUT IN/OUT OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OBL OBL OBL OBL OBL LV LV OBL OBL LV LV VSS LV LV LV LV LV LV LV LV LV LV LV
Switchable driver (weak/strong)
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DATA SHEET
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Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
1) 2)
Pin Name GPIO 31) GPIO 21) GPIO 11) GPIO 01) SDA1) SCL1) TRDY VBUS NC NC VREG DMINUS DPLUS VSS VDD MCLK1) USBCLK1) USBWSO1) USBDAT1) TEST RES SUSPEND SOF SEN NC FOUTL FOPL FINL FOUTR FOPR
Type IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT IN
Connection
(If not used)
Short Description HID IO 3 HID IO 2 HID IO 1 HID IO 0 I2C Data I2C Clock Test Output Pin Sense USB Bus Not Connected Not Connected Capacitor for internal supply USB DATA MINUS USB DATA PLUS Digital VSS Digital VDD I2S Master Clock (384 x 48 kHz) Direct ISO-Endpoint Output Clock Direct ISO-Endpoint Output Word Strobe Direct ISO-Endpoint Output Data Test Enable Power On Reset, active low Low-Power Mode Indicator 1 ms Start-Of-Frame Signal Suspend Enable Not Connected Output to left external filter Filter Op Amp Inverting Input, left Input for FiltoutL Output to right filter op amp Right Filter op amp inverting input
LV LV LV LV LV LV LV OBL2) LV LV
OUT IN/OUT IN/OUT IN IN OUT IN/OUT IN/OUT IN/OUT IN IN OUT OUT IN
OBL OBL2) OBL2) OBL OBL LV LV LV LV VSS VDD LV LV VSS LV
OUT IN/OUT IN/OUT OUT IN/OUT
OBL OBL OBL OBL OBL
Switchable driver (weak/strong) For non-USB codec applications leave D+/- vacant and connect VBUS pin to VDD
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DATA SHEET
Pin No. 55 56 57 58 59 60 61 62 63 64
Pin Name FINR OUTS FOPS NC ADCR ADCL MICBIAS MICIN SGND SREF
Type IN/OUT OUT OUT
Connection
(If not used)
Short Description Input for FILTOUTR Analog Output Subwoofer Output to Subwoofer external filter Not Connected Line Input Right Line Input Left Supply Voltage for Microphone Microphone Input Signal Reference Ground Signal Reference voltage
OBL LV OBL LV
IN IN OUT IN IN IN/OUT
LV LV LV LV OBL OBL
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DATA SHEET
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5.3.2. Analog Audio Pins FOUTL (50) FOPL (51) FINL (52) FOUTR (53) FOPR (54) FINR (55) FOPS (57) Filter op amps are provided in the analog baseband signal paths. These inverting op amps are freely accessible for external use by these pins. The FOUTL/R pins are connected with the buffered output of the internal switch matrix. The FOPL/R pins are directly connected with the inputs of the inverting filter op amps. The FINL/R pins are connected to the outputs of the op amps. ADCL (60) ADCR (59) Line Input pins. MICIN (62) MICBIAS (61) Microphone input pin and microphone power supply pin. OUTL (7) OUTR (8) OUTS (56) These pins are connected to the internal output amplifiers. OUTL/R can be used for either line-out or stereo headphones. OUTS is the subwoofer output of line-out type. Note: A short-circuit at these pins for more than a momentary period may result in destruction of the internal circuits.
5.3. Pin Descriptions 5.3.1. Power Supply Pins The UAC 355xB combines various analog and digital functions which may be used in different modes. For optimized performance, major parts have their own power supply pins. All VSS power supply pins must be connected. VDD (39) VSS (38) The VDD and VSS power supply pair are connected internally with all digital parts of the UAC 355xB. AVDD (10) AVDD is the supply pin for the voltage regulators at AREG0 (9) and AREG1 (4). AVSS0 (6) AVSS0 is the ground connection for the headphone/ loudspeaker amplifier. AVSS1 (5) AVSS1 is the ground connection for the analog audio processing parts, except the headphone/loudspeaker amplifiers. SREF (64) Reference for analog audio signals. This pin is used as reference for the internal op amps. This pin must be blocked against SGND with a 3.3 F capacitor. Note: The pin has a typical DC level of 1.725 V. It can be used as reference input for external op amps when no current load is applied. SGND (63) Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean ground potential! Any external distortions on this pin will affect the analog performance of the UAC 355xB. AREG0 (9) Voltage regulator output for headphone/loudspeaker amplifiers supply. Connect an external ceramic capacitor to stabilize the regulator output. AREG1 (4) Voltage regulator output for analog audio processing parts supply, except the headphone/loudspeaker amplifiers. Connect an external ceramic capacitor to stabilize the regulator output.
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5.3.3. Interface Pins DMINUS (36) DPLUS (37) Differential USB port pins. The DPLUS pin has an internal switchable pull-up resistor. Both pins must be connected to the USB bus via a series resistor. VBUS (32) Sense USB Bus. USBCLK (41) Direct ISO Endpoint Output Clock. USBWSO (42) Direct ISO Endpoint Word Strobe. USBDAT (43) Direct ISO Endpoint Output Data. CLI (15) Clock line for the I2S bus. In master mode, this line is driven by the UAC 355xB; in slave mode, an external I2S clock has to be supplied. DAO (16) Output of digital serial sound data of the UAC 355xB on the I2S bus. DAI (13) Input of digital serial sound data to the UAC 355xB via I2S bus. WSI (14) Word strobe line for the I2S bus. In master mode, this line is driven by the UAC 355xB; in slave mode, an external I2S word strobe has to be supplied. MCLK (40) I2S master clock pin. SCA (29) Via this pin, the I2C bus data is written to or read from the UAC 355xB. SCL(30) Via this pin, the I2C bus clock signal has to be supplied. 5.3.4. Other Pins
DATA SHEET
XTI (2) XTO (3) The XTI pin is connected to the input of the internal crystal oscillator; the XTO pin to its output. Both pins should be directly connected to the crystal and two ground-connected capacitors (see application diagram). Note: Do not drive external clock circuits via XTI/XTO. SEN (48) Digital input that prevents the device from entering the low-power mode. This pin is also used to signal remote wake-up. TEST (44) Test enable. This pin is for test purposes only and must always be connected to VSS. VREG (35) Voltage regulator output for USB transceiver supply. Connect an external ceramic capacitor to stabilize the regulator output. RES (45) A Low signal at this pin resets the chip. GPIO 0...ADR/GPIO 11/PWM (28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17) These pins are configurable to be either input or output and can be used to connect audio function keys or signalling LEDs. RD (11) GPIO read pin. STRB (12) GPIO strobe pin. SUSPEND (46) This pin indicates that the host PC sets the USB bus to the suspend mode state. SOF(47) Start of Frame Signal. 1 ms signal that can be used for external application circuits. TRDY (31) Test Output Pin. This pin is intended for test purposes only and must not be connected.
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DATA SHEET
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5.4. Pin Configuration
USBCLK1) USBWSO1) USBDAT1) TEST RES SUSPEND SOF SEN MCLK1) VDD VSS DPLUS DMINUS VREG NC NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC FOUTL FOPL FINL FOUTR FOPR FINR OUTS FOPS NC ADCR ADCL MICBIAS MICIN SGND SREF 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 VBUS TRDY SCL1) SDA1) GPIO 01) GPIO 11) GPIO 21) GPIO 31) GPIO 41) GPIO 51) GPIO 61) GPIO 71) ADR0/GPIO 81) ADR1/GPIO 91) ADR2/GPIO 101) ADR3/GPIO 11/PWM1)
UAC 355xB
25 24 23 22 21 20 19 18 17
NC XTI XTO AREG1 AVSS1 AVSS0 OUTL OUTR DAI STRB1) RD1) AVDD AREG0
DAO1) CLI1) WSI1)
1)Switchable
driver (weak/strong)
Fig. 5-3: PMQFP64-2 and PQFN64-1 package
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5.5. Pin Circuits
DATA SHEET
ext. filter network FOUTn FOPn FINn
Fig. 5-8: Input Pins RES, TEST, SEN, DAI
SREF Fig. 5-4: Pins FINR, FOPR, FINL, FOPL SREF
-
+
A D
Fig. 5-9: Analog input pins MIC, MICBIAS, ADCL, ADCR SREF
115 k
SGND Fig. 5-5: Pins SREF, SGND SREF Fig. 5-10: Output Pins OUTL, OUTR FOUTn DVSUP SREF Fig. 5-6: Output Pins FOUTL, FOUTR GND AREG1 P P P N
Enable
OUTn
P N
Fig. 5-11: Digital Output Pins SOF, SUSPEND, TRDY
XTI
DVSUP XTO P N GND Fig. 5-12: Digital Output Pins MCLK, RD, STRB, DAO
N N AVSS1
Fig. 5-7: Clock oscillator XTI, XTO
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DATA SHEET
UAC 355xB
FOPS
D A
I
-
+
OUTS
Fig. 5-16: Input Pin VBUS
SREF Fig. 5-13: Subwoofer Output Pin OUTS and Output to Subwoofer External Filter FOPS
N GND
VREG P
1.5 k
Fig. 5-17: Input/Output Pins SDA, SCL
VREG AVDD -
+
DPLUS
DMINUS VSS
AREG0/1
Suspend
AVSS Fig. 5-14: Digital Input/Output Pins DMINUS, DPLUS, VREG Fig. 5-18: Analog Voltage Supply Pins AVDD, AVSS, AREG0/1
DVSUP P N GND Fig. 5-15: Input/Output Pins GPIO0...GPIO11, WSI, CLI, USBCLK, USBWSO, USBDAT
VDD -
+
VREG
VSS Fig. 5-19: Digital Voltage Supply Pins VDD, VSS, VREG
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UAC 355xB
5.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip 5.6.1. Absolute Maximum Ratings
DATA SHEET
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (VSUPA, VSUPD = 0 V) except where noted. All ground pins must be connected to a low-resistive ground plane close to the IC. Symbol Parameter Pin Name Limit Values Min. -10 -10 -10 -40 0 0 AVDD AVDD, AREG0/1 VDD AVSS0, AVSS1, VSS -0.3 -0.3 -0.3 -0.5 Max. 702) 115 120 125 1190 870 6 6 6 +0.5 V V V V C mW C C Unit
TA1) TC
Ambient Operating Temperature Case Operating Temperature for PQFN64-1 package for PMQFP64-2 package Storage Temperature Power Dissipation for PQFN64-1 package for PMQFP64-2 package Analog Supply Voltage3) Analog Supply Voltage4) Digital Supply Voltage Voltage Differences between different Grounds Input Voltage, all digital inputs Input Current, all digital inputs5)
TS PMAX
VSUPA VSUPA VSUPD VGRND
VIdig IIdig
1)
-0.3 -20
VSUPD + 0.3 +20
V mA
Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power consumption allowed for this package A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the "Absolute Maximum Ratings" must not be exceeded at worst case conditions of the application. Internal regulators used If internal regulators are not used, connect AVDD to AREG0/1. Positive value means current flowing into the circuit.
2)
3) 4) 5)
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DATA SHEET
UAC 355xB
Symbol
Parameter
Pin Name
Limit Values Min. -50 -0.3 -5 Max. +50 VVAREG0/1+ 0.3 +5 0.2 +20 +20
Unit
IOdig VIana IIana IOaudio IAREG0 IAREG1
1)
Output Current, all digital outputs Input Voltage, all analog inputs Input Current, all analog inputs1) Output Current, audio output1)2) Output Current, analog regulator2) Output Current, analog regulator2) OUTL/R AREG0 AREG1
mA V mA A mA mA
-0.2 -500 -50
These pins are not short-circuit proof! value means current flowing into the circuit.
2)Positive
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UAC 355xB
5.6.2. Recommended Operating Conditions
DATA SHEET
Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (VSUPA, VSUPD = 0 V) except where noted. All ground pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in section Section 2.7. "Power Supply" on page 12 of this document. Symbol Parameter Pin Name Min. Temperature Ranges and Supply Voltages TA TC Ambient Temperature Range Case Operating Temperature for PQFN64-1 package for PMQFP64-2 package Analog Audio Supply Voltage Power Dissipation for PQFN64-1 package for PMQFP64-2 package Digital Supply Voltage Capacitor at digital supply pin to ground Capacitor at VBUS pin to ground VDD VDD VBUS 4.1 5.0 100 22 AVDD 0 25 35 4.1 25 50 60 5.0 701) 95 105 5.6 6502) 6502) 5.6 V mW C C Limit Values Typ. Max. Unit
VSUPA PMAX
VSUPD CSUPD CSUPUSB
V nF nF
Analog Reference CSREF1 CSREF2 Analog Reference Capacitor Ceramic Capacitor in parallel SREF SREF 1 3.3 100 F nF
Analog Audio Inputs CinAD CinMI DC-Decoupling Capacitor at A/D converter inputs DC-Decoupling Capacitor at microphone input ADCL/R MICIN 390 100 nF nF
Analog Audio Filter Inputs and Outputs ZAFLO ZAFLI
1)
Analog Filter Load Output3) Analog Filter Load Input3)
FOUTL/R FINL/R
7.5 6 5.0 7.5
k pF k pF
A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the "Recommended Operating Conditions" must not be exceeded at worst case conditions of the application. PMAX variation: user-determined by application circuit for I/Os Please refer to Section 6. "UAC 3556/3554B Applications" on page 46
2) 3)
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DATA SHEET
UAC 355xB
Symbol
Parameter
Pin Name Min.
Limit Values Typ. 2.2 Max.
Unit
CFILTSUBW
Filter Capacitor for Subwoofer output
FOPS
nF
Analog Audio Outputs ZAOL_HP ZAOLSUBW, ZLine_out Output Load Headphone (16 series resistor required) Output Load Subwoofer (if the max. capacitive load is exceeded, a decoupling resistor of 220 is mandatory) DC-decoupling capacitor at subwoofer output Crystal Characteristics 1) TAC FP VACLK F/Fs F/Fs REQ C0 PD Ambient Temperature Range Load Resonance Frequency at Cload = 15 pF 2) Clock Amplitude Accuracy of Adjustment Frequency Variation versus Temperature Equivalent Series Resistance Shunt (parallel) Capacitance Drive Level 3 XTI XTI, XTO 0.5 -500 -500 0 12 VREG1
-0.5
OUTL/R OUTS, FINL/R
16 10
32 100
pF k 15 pF
470
nF
70
C MHz VPP ppm ppm pF mW
500 500 60 5 1
Voltage Regulator CVREG CAREG0 CAREG1 Transceiver RUSB Input Series Resistance DPLUS/ DMINUS 24 (5%) Voltage Regulator Capacitor (ceramic, X5R) Voltage Regulator Capacitor (ceramic, X5R) Voltage Regulator Capacitor (ceramic, X5R) VREG AREG0 AREG1 330 330 150 1000 470 220 600 270 nF nF nF
1) For device characteristics please refer to page 40 2) Cload should typically be 15 pF (+30% / -10%), e.g.,
Y5U. Refer to application circuit (see Fig. 6-3 on page 47).
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UAC 355xB
5.6.3. Characteristics At TA = 0 C to 70 C, VSUPD = 4.1 V to 5.6 V, VSUPA = 4.1 V to 5.6 V. Typical values at TA = 20 C, VSUPD = VSUPA = 5.0 V, quartz frequency = 12 MHz, duty cycle = 50%, bass/treble: 0 dB, Micronas Bass: off, AGC: off, equalizer: off (positive current flowing into the IC), 3 V Mode, reduced feature set, if not otherwise specified.
Symbol Parameter Pin Name Min. Digital Supply IVDD Current Consumption1) VDD 57 45 30 70 mA 80 A Limit Values Typ. Max. Unit
DATA SHEET
Test Conditions
72 MHz APU clock 48 MHz APU clock Suspend
Digital Input Pin II VIL VIH Input Leakage Current Input Low Voltage Input High Voltage GPIO[11:0], SEN, RES, VBUS, DAI, WSI, CLI VSUPD
1
0.4
A
V V
VGND VI VSUP
-0.4V
Digital Output Pin VOH Output High Voltage GPIO[11:0]SU SPEND,SOF, RD, STRB, WSI, CLI, DAO, SDA, SCL,MCLK VSUPD V Pins set to output Iout =8 mA
- 0.4
0.4 8 13) 2)3) V mA
VOL IO_max
Output Low Voltage Max. Output Current
output set to "weak" output set to "strong"
Analog Supply IAVDD Current Consumption Analog Audio AVDD 12 120 25 15 135 mA A mA Suspend RL 32 (external 16 series resistor required) Volume = 0 dB, Input signal 1kHz at 0 dBFS 1 kHz sine wave at 100 mVrms 100 kHz sine wave at 100 mVrms all analog blocks on, Mute
PSRRAA
Power Supply Rejection Ratio for Analog Audio Outputs (internal regulators active)
AVDD,4) OUTL/R/S
95 55
dB dB
1) 2) 3)
no load attached to GPIOs. max. output current for driving LEDs is 20 mA. the sum of these digital output pin currents must not exceed 100 mA. Higher currents might damage the device. 4) not tested in production. Please consider power limitations due to USB specification.
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DATA SHEET
UAC 355xB
Different Characteristics in Five-Volt Mode Symbol Parameter Pin Name Min. VMICBIAS VSREF VAI VMI Open Circuit Voltage Microphone Bias Signal Reference Voltage Analog Line Input Clipping Level (at input volume 0 dB) Microphone Input Clipping Level (at minimum input volume, i.e., 0 dB) Analog Output Voltage AC MICBIAS SREF ADCL/R MICIN 3.9 2.25 Limit Values Typ. 4.0 2.3 3.2 370 Max. 4.1 2.35 V Vpp mVpp RL >> 10 M, referred to SGND Unit Test Conditions
VAO
OUTL/R
3.2
Vpp
BW = 20 Hz...22 kHz, RL 10 k, volume = 0 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz, RL 10 k, volume = 0 dB, Input 100 Hz at 0 dBFS digital (I2S) BW = 20 Hz...22 kHz, RL 10k, Volume = 0 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = 0 dB, Input 1 kHz at - 20 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10k, Volume = -40 dB, Input 1 kHz at -3 dBFS digital (I2S) RL = 32 , 16 series resistance, Volume = 0 dB, Input = 0 dBFS digital (I2S) RL = 16 , no series resistors, right channel inverted and output set to mono (bridge mode) Volume = 0 dB, Input = 0 dBFS digital (I2S)
VAOS
Analog Output Voltage AC
OUTS
3.1
Vpp
THDHP
Total Harmonic Distortion
OUTL/R
-93
-85
dB
SNRAO1
Signal-to-Noise Ratio2)
OUTL/R
90
99
dB(A)
SNRAO2
Signal-to-Noise Ratio2)
OUTL/R
95
109
dB(A)
PHP
Output Power (Speaker/Headphone) Output Power in Bridge Mode (Mono Speaker/Headphone)
OUTL/R
17
mWeff
PHP
OUTL/R
320
mWeff
2)
related to 0 dBFS input level
Different Characteristics for Full-Feature Set (see Fig. 2-1 on page 6), Three-Volt Mode
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UAC 355xB
DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. 95 Max.
Unit
Test Conditions
SNRAO1
Signal-to-Noise Ratio2)
OUTL/R
88
dB(A)
BW = 20 Hz...22 kHz, A-weighted, RL 10k, Volume = 0 dB, Input 1 kHz at - 20 dBFS digital (I2S) BW = 20 Hz...22 kHz, Aweighted, RL 10 k, Volume = -40 dB, Input 1 kHz at -3 dBFS digital (I2S) BW = 20 Hz...22 kHz, unweighted, RL 10 k, Volume = 0 dB, Corner Frequency set to 400 Hz, Input 100 Hz at -20 dBFS digital (I2S) BW = 20 Hz...22 kHz, unweighted,RL 10k, Volume = -40 dB, corner frequency set to 400 Hz, Input 100 Hz at -3 dBFS digital (I2S) BW = 20 Hz...400 Hz unweighted, no digital input signal, corner frequency set to 400 Hz, Volume = Mute
SNRAO2
Signal-to-Noise Ratio2)
OUTL/R
93
100
dB(A)
SNRAS1
Signal-to-Noise Ratio2) Subwoofer
OUTS
75
85
dB
SNRAS2
Signal-to-Noise Ratio2) Subwoofer
OUTS
105
dB
LevMute
Mute Level Subwoofer
OUTS
-77
dB
2)
related to 0 dBFS input level
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DATA SHEET
UAC 355xB
5.6.4. I2S Interface Timing Characteristics
Symbol Parameter Pin Name Min. ts_I2S th_I2S td_I2S I2S Input Setup Time before Rising Edge of Clock I2S Input Hold Time after Rising Edge of Clock I2S Output Delay Time after Falling Edge of Clock CLI DAI USBCLK USBDAT CLI WSI DAO USBCLK USBWSI USBDAT CLI DAO USBCLK USBDAT 4 10 40 30 Limit Values Typ. Max. ns ns ns CL=30 pF Unit Test Conditions
to_I2S
I2S Output Setup Time before Rising Edge of Clock
ns
CL=30 pF
The interfaces can be used in three different modes.
1/FI2SWS WSI - Input
SONY format PHILIPS format Detail D CLI - Input Detail A DAI - Input
R LSB L MSB
SONY format PHILIPS format Detail C
L LSB R MSB
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail B DAO - OutputR LSB
L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail C
CLI - Output
1/FCLI =325.5 ns
Detail D
CLI - Output
1/FCLI =325.5 ns
Detail A,B
CLI - Output
Ts_I2S Th_I2S
DAI - Input Ts_I2S Td_I2S DAO - Output (30 pF load) To_I2S Td_I2S
WSI as OUTPUT
WSI as OUTPUT
Fig. 5-20: Timing: synchronous I2S input/output
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UAC 355xB
DATA SHEET
WSI - Input
SONY format PHILIPS format
SONY format PHILIPS format Detail C
CLI - Input Detail A DAI - Input
R LSB L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail C
CLI - Input
1/FCLI =325.5 ns
Detail D
CLI - Output
1/FCLI =325.5 ns
Detail A
CLI - Input
Ts_I2S Th_I2S
DAI - Input Ts_I2S Td_I2S
WSI as INPUT
WSI as OUTPUT
Fig. 5-21: Timing asynchronous I2S input
USBWSO - Output SONY format PHILIPS format Detail D USBCLK - Output USBDAT - Output
R LSB L MSB
SONY format PHILIPS format Detail C
Detail A
L LSB R MSB R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail C
USBCLK - Output
1/FCLI =325.5 ns
Detail D
USBCLK-Output
1/FCLI =325.5 ns
Detail A
USBCLK - Output
To_I2S
Td_I2S
Ts_I2S
Td_I2S
USBWSO as Output
USBWSO as Output
USBDAT - Output
Fig. 5-22: Timing synchronous I2S output
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DATA SHEET
UAC 355xB
6. UAC 355xB Applications 6.1. Recommended Low-Pass Filters for Analog Outputs
2nd-order
11 k 11 k
11 k 220 pF
1.0 nF
AVSS1
FOUTL(R)
FOPL(R)
FINL(R)
-
Fig. 6-1: 2nd-order low-pass filter
If the filter is not used, then FOUTL(R), FOPL(R), and FINL(R) are to be connected (dashed line) and the internal op-amp must be switched off. Table 6-1: Attenuation of 2nd-order low-pass filter Frequency 24 kHz 30 kHz Gain -1.5 dB -3.0 dB
Note: First or third-order low-pass is also possible, but then the frequency response degrades.
6.2. External Clocking via XTI AC coupling of the clock signal The input level should be in the range of 0.5 to 2.5 VPP. for a load capacitance of 22 pF at XTO. DC coupling of the clock signal The DC input level must be 0.5 x VAREG1 which is typically 1.75 V. The input level should not exceed 0.5 to 2.5 VPP. Also see Section 2.12. on page 15.
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6.3. Typical Applications
P3
Left In 11kk R29
C3
470n R1 1k C16 220n
R2
11k
R8
1 2 3
C15 2.2n + 3.3uF/Low ESR X1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R13
R15
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
C13 C11 6.8n 12MHz 27p
R17
R25 470k
11k
SREF SGND MICIN MICBIAS ADCL ADCR n.c. FOPS OUTS FINR FOPR FOUTR FINL FOPL FOUTL n.c.
11k
11k
R7 11k Left Out P4 Right Out P5 DVDD R9 11k R18 220k 1 2 HPdet 3 4 5
R10 100 R19 16 R20 16 R11 100
C14 27p
12MHz C5 220n
C23 150u C24 150u + +
AVDD C17 220n
C12 6.8n Mic detect JP3 MICdet GPIO6 HP detect JP4 GPIO5 HPdet
GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 SDA SCL TRDY VBUS
PK2 Headphone
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DVDD DVDD DVDD 8 U2 6 1 2 3 SCL CE0 CE1 CE2 VCC SDA WC 5 7
R30 1k C31 100n SDA
DL1 LED
GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 SDA SCL TRDY VBUS
D1 1N4001 POW1 7,5V DC C26 100n 1 + C29 6,8u/16V Vin
U3 VOLTREG GND Vout
DVDD 3
L5 Ferrite C27 100n
DVDD AVDD J2 C30 CE2 + 1 2 3 6,8u/16V J4 CE1 1 2 3 J6 CE0 1 2 3 R23 4.7k
2
GND
C28 100n KS1
4
single connection point
SCL
I2C EEPROM
R24 4.7k
DVDD
Fig. 6-2: Circuit for a typical codec application
+
C18 470n RD STRB DAI WSI CLI DAO
n.c. XTI XTO AREG1 AVSS1 AVSS0 OUTL OUTR AREG0 AVDD RD STRB DAI WSI CLI DAO
U1
UAC 355xB
SEN SOF SUSPEND RES TEST USBDAT USBWSO USBCLK MCLK VDD VSS Dplus Dminus VREG n.c. n.c.
11k
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UAC 355xB
R3 C7 220p C1 R27 11k R28 P2 11k Right In C2 470n C8 470n R4
11k P9 11k DVDD DVDD GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 TRDY TEST SOF #RES #SUSPEND SEN DVDD DVDD GPIO8 GPIO9 GPIO10 GPIO11 STRB RD DVDD 1 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
P1
Sub Out
C9 1n R12 220k D2 BAV99 R5 220pR6 11k 11k C32 220n C10 1n R31 100k R26 100k
SCL SDA 12MHz
AGND
PK1 Mic
1 2 3 4 5
MICdet
JP2 MicBias
C4
470n JX1 12MHz C19 100n C22 DVDD
2
JP5 DAT
12
JP6 WSO
12
JP7 CLK
HEADER 25X2 PI3 DAI WSI CLI 2 4 6 8 10 1 3 5 7 9
SEN 48 SOF 47 46 #SUSPEND #RES 45 TEST 44 43 USBDAT JP1 42 USBWSO 41 USBCLK SELF/BUS C21 40 MCLK 2 1 C20 100n 39 DVDD DVDD 100n 38 DGND VBUS 37 R21 24 36 R22 24 35 C6 34 33 470n
I2S In
C25 6.8u/10V/lowESR L2 L3 L4 L1 Ferrite Ferrite Ferrite Ferrite MCLK CLI WSI DAO
PU1 1 2 3 4 5 PI1 1 3 5 7 9 PI2 2 4 6 8 10
USB Type B
I2S Out
USBCLK USBWSO USBDAT
1 3 5 7 9
2 4 6 8 10
Burst I2S out
DATA SHEET
Micronas
DATA SHEET
UAC 355xB
UAC 3554B
Micronas
Fig. 6-3: Circuit for a headset application
May 13, 2004; 6251-544-2DS
47
UAC 355xB
7. Data Sheet History 1. Data Sheet: "UAC 355XB Universal Serial Bus (USB) Codecs", April 15, 2003, 6251-544-1DS. First release of the data sheet. 2. Data Sheet: "UAC 355XB Universal Serial Bus (USB) Codecs", May 12, 2004, 6251-544-2DS. Second release of the data sheet Major changes: - New Package Drawings for PQFN64-1 and PMQFP64-2 - Updated Electrical Characteristics: Absolute Maximum Ratings and Recommended Operating Conditions Tables. - Application Drawings modified.
DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-544-2DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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