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Intel386TM SXSA EMBEDDED MICROPROCESSOR
Static Intel386TM CPU Core Integrated Memory Management Unit
-- Low Power Consumption -- Operating Power Supply 4.5V to 5.5V - 25 and 33 MHz 4.75V to 5.25V - 40 MHz -- Operating Frequency SA-40 = 40 MHz SA-33 = 33 MHz SA-25 = 25 MHz Clock Freeze Mode Allows Clock Stopping at Any Time
Full 32-bit Internal Architecture
(MMU) -- Virtual Memory Support -- Optional On-chip Paging -- 4 Levels of Hardware-Enforced Protection -- MMU Fully Compatible with 80286 and Intel386 DX Processors Virtual 8086 Mode Allows Execution of 8086 Software in a Protected and Paged System
Large Uniform Address Space
-- 8-, 16-, 32-bit Data Types -- 8 General Purpose 32-bit Registers Runs Intel386 Architecture Software in a Cost-effective, 16-bit Hardware Environment -- Runs Same Applications and Operating Systems as the Intel386 SX and Intel386 DX Processors -- Object Code Compatible with 8086, 80186, 80286, and Intel386 Processors TTL-Compatible Inputs
High-performance 16-bit Data Bus
-- 16 Megabyte Physical -- 64 Terabyte Virtual -- 4 Gigabyte Maximum Segment Size Numerics Support Intel387TM SX and Intel387TM SL Math Coprocessors
On-chip Debugging Support Including
Breakpoint Registers
Complete System Development
Support
High Speed CHMOS Technology 100-Pin Plastic Quad Flatpack Package
-- Two-clock Bus Cycles -- Address Pipelining Allows Use of Slower, Inexpensive Memories
The Intel386TM SXSA embedded microprocessor is a 5-volt, 32-bit, fully static CPU with a 16-bit external data bus and a 24-bit external address bus. The Intel386 SXSA CPU brings the vast software library of the Intel386 architecture to embedded systems. It provides the performance benefits of 32-bit programming with the cost savings associated with 16-bit hardware systems. The Intel386 SXSA microprocessor is manufactured on Intel's 0.8-micron CHMOS V process. This process provides high performance and low power consumption for power-sensitive applications. Figure 3 and Figure 4 illustrate the flexibility of low power devices with respect to temperature and frequency relationships.
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringe-ment of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. Copyright(c) INTEL Corporation, 2002 June 2002 Order Number: 272419-004
Intel386TM SXSA EMBEDDED MICROPROCESSOR
Segmentation Unit 32 Effective Address Bus 32 Effective Address Bus 3-Input Adder Descriptor 32 Register Limit and Attribute PLA Protection Test Unit
Bus
Bus
Paging Unit Bus Control
Physical Address Bus
Adder
Request Prioritizer
Page Cache Control and Attribute PLA 27
Code Fetch/Page Table Fetch
HOLD, RESET INTR, NMI ERROR# BUSY#,HLDA
Address Driver Pipeline/ Bus Size Control MUX/ Transceivers
Control
BLE#, BHE# A23:1
Internal Control Bus
Displacement
Linear Address
32
M/IO#, D/C# W/R#, LOCK# ADS#, NA# READY#
Status Multiply/ Flags Divide Register File
Barrel Shifter/ Adder
Decode and Sequencing
Instruction Decoder Code 3-Decoded Stream Instruction Queue 32 Instruction Predecode Dedicated ALU Bus
Prefetcher/ Limit Checker 16-Byte Code Queue Instruction Prefetch
D15:0
ALU Control
Control ROM
Control
ALU
32
A2298-01
Figure 1. Intel386TM SXSA Microprocessor Block Diagram
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
1.0
PIN ASSIGNMENT
D1 D2 Vss Vcc D3 D4 D5 D6 D7 Vcc D8 D9 D10 D11 D12 Vss Vcc D13 D14 D15 A23 A22 Vss Vss A21
D0 Vss HLDA HOLD Vss NA# READY# Vcc Vcc Vcc Vss Vss Vss Vss CLK2 ADS# BLE# A1 BHE# NC Vcc Vss M/IO# D/C# W/R#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TOP VIEW
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A20 A19 A18 A17 Vcc A16 Vcc Vss Vss A15 A14 A13 Vss A12 A11 A10 A9 A8 Vcc A7 A6 A5 A4 A3 A2
NOTE: NC = No Connection
A2297-0A
Figure 2. Intel386TM SXSA Microprocessor Pin Assignment (PQFP)
LOCK# NC FLT# NC NC NC Vcc RESET BUSY# Vss ERROR# PEREQ NMI Vcc INTR Vss Vcc NC NC NC NC NC Vcc Vss Vss
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
Table 1. Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol
D0 VSS HLDA HOLD VSS NA# READY# VCC VCC VCC VSS VSS VSS VSS CLK2 ADS# BLE# A1 BHE# NC VCC VSS M/IO# D/C# W/R#
Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Symbol
LOCK# NC FLT# NC NC NC VCC RESET BUSY# VSS ERROR# PEREQ NMI VCC INTR VSS VCC NC NC NC NC NC VCC VSS VSS
Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
A2 A3 A4 A5 A6 A7
Symbol
Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
A21 VSS VSS A22 A23 D15 D14 D13 VCC VSS D12 D11 D10 D9 D8 VCC D7 D6 D5 D4 D3 VCC VSS D2 D1
Symbol
VCC A8 A9 A10 A11 A12 VSS A13 A14 A15 VSS VSS VCC A16 VCC A17 A18 A19 A20
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
2.0
PIN DESCRIPTIONS
Table 2 lists the Intel386 SXSA microprocessor pin descriptions. The following definitions are used in the pin descriptions: # I O I/O P G The named signal is active low. Input signal. Output signal. Input and output signal. Power pin. Ground pin. Table 2. Pin Descriptions Symbol A23:1 Type O Pin 80-79, 76-72, 70, 66-64 62-58, 56-51, 18 16 Name and Function Address Bus outputs physical memory or port I/O addresses.
ADS#
O
Address Status indicates that the processor is driving a valid bus-cycle definition and address onto its pins (W/R#, D/C#, M/IO#, BHE#, BLE#, and A23:1). Byte High Enable indicates that the processor is transferring a high data byte. Byte Low Enable indicates that the processor is transferring a low data byte. Busy indicates that the math coprocessor is busy. CLK2 provides the fundamental timing for the device. Data/Control indicates whether the current bus cycle is a data cycle (memory or I/O) or a control cycle (interrupt acknowledge, halt, or code fetch). When D/C# is high, the bus cycle is a data cycle; when D/C# is low, the bus cycle is a control cycle. Data Bus inputs data during memory read, I/O read, and interrupt acknowledge cycles and outputs data during memory and I/O write cycles. Error indicates that the math coprocessor has an error condition. Float forces all bidirectional and output signals, including HLDA, to a high-impedance state. Bus Hold Acknowledge indicates that the CPU has surrendered control of its local bus to another bus master. Bus Hold Request allows another bus master to request control of the local bus. Interrupt Request is a maskable input that causes the CPU to suspend execution of the current program and then execute an interrupt acknowledge cycle.
BHE# BLE# BUSY# CLK2 D/C#
O O I I O
19 17 34 15 24
D15:0
I/O
81-83, 86-90, 92-96, 99-100, 1 36 28 3 4 40
ERROR# FLT# HLDA HOLD INTR
I I O I I
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
Table 2. Pin Descriptions (Continued) Symbol LOCK# M/IO# Type O O Pin 26 23 Name and Function Bus Lock prevents other system bus masters from gaining control of the system bus while it is active (low). Memory/IO indicates whether the current bus cycle is a memory cycle or an input/output cycle. When M/IO# is high, the bus cycle is a memory cycle; when M/IO# is low, the bus cycle is an I/O cycle. Next Address requests address pipelining. No Connection should always be left unconnected. Connecting a NC pin may cause the processor to malfunction or cause your application to be incompatible with future steppings of the device. Nonmaskable Interrupt Request is a nonmaskable input that causes the CPU to suspend execution of the current program and execute an interrupt acknowledge function. Processor Extension Request indicates that the math coprocessor has data to transfer to the processor. Bus Ready indicates that the current bus cycle is finished and the external device is ready to accept more data from the processor. Reset suspends any operation in progress and places the processor into a known reset state. Write/Read indicates whether the current bus cycle is a write cycle or a read cycle. When W/R# is high, the bus cycle is a write cycle; when W/R# is low, it is a read cycle. System Power provides the nominal DC supply input.
NA# NC
I
6 20, 27, 29-31, 43-47
NMI
I
38
PEREQ READY#
I I
37 7
RESET W/R#
I O
33 25
VCC
P
8-10, 21, 32, 39, 42, 48, 57, 69, 71, 84, 91, 97 2, 5, 11-14, 22 35, 41, 49-50, 63, 67-68, 77-78, 85, 98
VSS
G
System Ground provides the 0V connection from which all inputs and outputs are measured.
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
3.0
DESIGN CONSIDERATIONS
3.3.
Package Thermal Specifications
This section describes the Static Intel386 SXSA microprocessor instruction set, component and revision identifier, and package thermal specifications.
3.1.
Instruction Set
Static Intel386 SXSA microprocessor is specified for operation with case temperature (TCASE) as specified in the "DC SPECIFICATIONS" on page 9. The case temperature can be measured in any environment to determine whether the microprocessor is within the specified operating range. The case temperature should be measured at the center of the top surface opposite the pins. An increase in the ambient temperature (TA) causes a proportional increase in the case temperature (TCASE) and the junction temperature (TJ). See Figures 3 and Figures 4 for case and ambient temperature relationships to frequency. A packaged device produces thermal resistance between junction and case temperatures (JC) and between junction and ambient temperatures (JA). The relationships between the temperature and thermal resistance parameters are expressed by these equations (P = power dissipated as heat = VCC x ICC): 1. 2. 3. TJ = TCASE + P x JC TA = TJ - P x JA TCASE = TA + P x [JA - JC]
The Static Intel386 SXSA microprocessor uses the same instruction set as the dynamic Intel386 SX microprocessor. However, the Static Intel386 SXSA microprocessor requires more clock cycles than the dynamic Intel386 SX microprocessor to execute some instructions. Table 4 lists these instructions and the Static Intel386 SXSA microprocessor execution times. For the equivalent dynamic Intel386 SX microprocessor execution times, refer to the "Instruction Set Clock Count Summary" table in the Intel386TM SX Microprocessor data sheet (order number 240187).
3.2.
Component and Revision Identifier
To assist users, the microprocessor holds a component identifier and revision identifier in its DX register after reset. The upper 8 bits of DX hold the component identifier, 23H. (The lower nibble, 3H, identifies the Intel386 architecture, while the upper nibble, 2H, identifies the second member of the Intel386 microprocessor family.) The lower 8 bits of DX hold the revision level identifier. The revision identifier will, in general, chronologically track those component steppings that are intended to have certain improvements or distinction from previous steppings. The revision identifier will track that of the Intel386 CPU whenever possible. However, the revision identifier value is not guaranteed to change with every stepping revision or to follow a completely uniform numerical sequence, depending on the type or intent of the revision or the manufacturing materials required to be changed. Intel has sole discretion over these characteristics of the component. The initial revision identifier for the Static Intel386 SXSA microprocessor is 09H.
A safe operating temperature can be calculated from equation 1 by using the maximum safe TJ of 115 C, the maximum power drawn by the chip in the specific design, and the JC value from Table 3. The JA value depends on the airflow (measured at the top of the chip) provided by the system ventilation. The JA values are given for reference only and are not guaranteed. Table 3. Thermal Resistances (0C/W) JA, JC Pkg 100 PQFP JC 5.1 JA versus Airflow (ft/min) 0 46.0 100 44.8 200 41.2
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
Table 4. Intel386TM SXSA Microprocessor Instruction Execution Times (in Clock Counts) Clock Count Instruction Virtual 8086 Mode (Note 1) Real Address Mode or Virtual 8086 Mode 28 27 28 27 28 30 31 31+6n (Note 2) 30+8n (Note 2) 14 15 14 15 17 18 17+6n (Note 2) 16+8n (Note 2) 7 10 Protected Virtual Address Mode (Note 3) 35 7/29 8/29 7/29 9/29 9/32 10/33 10+6n/32+6n (Note 2) 10+8n/31+8n (Note 2) 7 10
POPA IN: Fixed Port Variable Port OUT: Fixed Port Variable Port INS OUTS REP INS REP OUTS HLT MOV C0, reg
NOTES:
1. The clock count values in this column apply if I/O permission allows I/O to the port in virtual 8086 mode. If the I/O bit map denies permission, exception fault 13 occurs; see clock counts for the INT 3 instruction in the "Instruction Set Clock Count Summary" table in the Intel386TM SX Microprocessor data sheet (order number 240187). 2. n = the number of times repeated. 3. When two clock counts are listed, the smaller value refers to a register operand and the larger value refers to a memory operand.
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
4.0
DC SPECIFICATIONS
NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design.
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ................................ -65C to +150C Case Temperature Under Bias ................. -65C to +112C Supply Voltage with Respect to VSS ............... -0.5V to 6.5V Voltage on Other Pins .......................... -0.5V to VCC + 0.5V
OPERATING CONDITIONS*
VCC (Digital Supply Voltage - 25 and 33 MHz) ...4.5V to 5.5V VCC (Digital Supply Voltage - 40 MHz) ...........4.75V to 5.25V TCASE minimum (Case Temperature Under Bias) ......... 0C TCASE maximum ......................................... see Figure 4 Operating Frequency ................................ 0 MHz to 40 MHz
Table 5. DC Characteristics Symbol
VIL VIH VILC VIHC VOL VOH ILI
Parameter
Input Low Voltage Input High Voltage CLK2 Input Low Voltage CLK2 Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current (for all pins except PEREQ, BUSY#, FLT#, ERROR#) Input Leakage Current (PEREQ) Input Leakage Current (BUSY#, FLT#, ERROR#) Output Leakage Current Supply Current CLK2 = 80 MHz, CLK = 40 MHz CLK2 = 66 MHz, CLK = 33 MHz CLK2 = 50 MHz, CLK = 25 MHz Standby Current (Freeze Mode) Input Capacitance Output or I/O Capacitance CLK2 Capacitance
Min. -0.3 2.0 -0.3 VCC - 0.8 2.4 VCC - 0.5
Max. +0.8 VCC + 0.3 +0.8 VCC + 0.3 0.45
Unit
V V V V V V V
Test Condition
IOL = 5 mA IOH = -1 mA IOH = -0.2 mA 0 VIN VCC
15
A
IIH IIL ILO ICC
150 -120 15 275 225 175
A A A mA mA mA
VIH = 2.4V (Note 1) VIL = 0.45V (Note2) 0.45V VOUT VCC (Notes 3, 4) typical = 200 mA typical = 175 mA typical = 140 mA
ICCF CIN COUT CCLK NOTES:
1. 2. 3. 4. 5.
150 10 12 20
A pF pF pF
typical = 10 A (Notes 3 4) FC = 1 MHz (Note 5) FC = 1 MHz (Note 5) FC = 1 MHz (Note 5)
PEREQ input has an internal weak pull-down resistor. BUSY#, FLT# and ERROR# inputs each have an internal weak pull-up resistor. ICC max measurement at worst-case frequency, VCC, and temperature with reset active. ICC typical and ICCF typical are measured at nominal VCC and are not fully tested. Not fully tested.
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
100
90 85 80 70 58
75 Ta (C) 50
45
25
12
16
20
25
33
40
Operating Frequency (MHz)
A2586-01
Figure 3. Ambient Temperature vs. Frequency at Zero Air Flow and TJ = 115 C
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
115 112 111.5 111 Tc (C) 110 110 108.5 107
105 12 16 20 25 33 40
Operating Frequency (MHz)
A2587-01
Figure 4. Case Temperature vs. Frequency at TJ = 115 C
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
5.0
AC SPECIFICATIONS
Table 6 lists output delays, input setup requirements, and input hold requirements. All AC specifications are relative to the CLK2 rising edge crossing the 2.0V level. Figure 5 shows the measurement points for AC specifications. Inputs must be driven to the indicated voltage levels when AC specifications are measured. Output delays are specified with minimum and maximum limits measured as shown. The minimum delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest
acceptable sampling window. Within the sampling window, a synchronous input signal must be stable for correct operation. Outputs ADS#, W/R#, D/C#, MI/O#, LOCK#, BHE#, BLE#, A23:A1 and HLDA change only at the beginning of phase one. D15:0 (write cycles) change only at the beginning of phase two. The READY#, HOLD, BUSY#, ERROR#, PEREQ, FLT# and D15:0 (read cycles) inputs are sampled at the beginning of phase one. The NA#, INTR and NMI inputs are sampled at the beginning of phase two.
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
PH1 CLK2 b A OUTPUTS (A23:1,BHE# BLE#,ADS#,MI/O# D/C#W/R#,LOCK# HLDA) B Min Valid a Output n
Tx
PH2
Max a Valid Output n+1 A B Min Max a Valid Output n+1
OUTPUTS (D15:0)
Valid a Output n C D Valid Input a
INPUTS (N/A#,INTR NMI) INPUTS (READY#,HOLD FLT#,ERROR# BUSY#,PEREQ D15:0)
3.0V 0V
a
C 3.0V 0V a Valid Input
D a
LEGEND a - 1.5V b - 2.0V A - Maximum Output Delay Spec B - Minimum Output Delay Spec C - Minimum Input Setup Spec D - Minimum Input Hold Spec
A2296-02
Figure 5. Drive Levels and Measurement Points for AC Specifications
13
Intel386TM SXSA EMBEDDED MICROPROCESSOR
Table 6. AC Characteristics 40 MHz Symbol Parameter Min. (ns) 0 12.5 4.5 3.5 4.5 3.5 4 4 4 4 4 4 4 4 7 2 4 4 5 2 7 4 4 17 17 13 20 13 20 13 20 18 4 4 4 4 4 4 7 2 4 4 5 2 7 4 5 17 20 Max. (ns) 40 33 MHz Min. (ns) 0 15 6.25 4 6.25 4.5 4 4 15 20 15 20 15 20 23 4 4 4 4 4 4 7 2 4 4 5 3 9 4 7 22 22 Max . (ns) 33 25 MHz Min. (ns) 0 20 7 4 7 5 7 7 17 30 17 30 17 30 23 (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) CL = 50 pF (Note 3) CL = 50 pF (Note 3) CL = 50 pF (Note 3) CL = 50 pF (Note 5) CL = 50 pF (Note 3) CL = 50 pF Max. (ns) 25 Test Condition
Operating Frequency t1 t2a t2b t3a t3b t4 t5 t6 t7 t8 t9 t10 t11 t12 t12a t13 t14 t15 t16 t19 t20 t21
NOTES:
1. 2. 3. 4.
MHz (Note 1)
CLK2 Period CLK2 High Time CLK2 High Time CLK2 Low Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A23:1 Valid Delay A23:1 Float Delay BHE#, BLE#, LOCK# Valid Delay BHE#, BLE#, LOCK# Float Delay W/R#, M/IO#, D/C#, ADS# Valid Delay W/R#, M/IO#, D/C#, ADS# Float Delay D15:0 Write Data Valid Delay D15:0 Write Data Hold Time D15:0 Write Data Float delay HLDA Valid Delay NA# Setup Time NA# Hold Time READY#Setup Time READY#Hold Time D15:0 Read Setup Time
Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. These are not tested. They are guaranteed by characterization. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. These inputs may be asynchronous to CLK2. The setup and hold specifications are given for testing purposes to ensure recognition within a specific CLK2 period. 5. Minimum time not 100% tested.
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
Table 6. AC Characteristics (Continued) 40 MHz Symbol Parameter Min. (ns) 3 4 2 4 2 5 5 5 Max. (ns) 33 MHz Min. (ns) 3 9 2 5 2 5 5 5 Max . (ns) 25 MHz Min. (ns) 5 9 3 8 3 6 6 6 (Note 4) (Note 4) (Note 4) Max. (ns) Test Condition
t22 t23 t24 t25 t26 t27 t28 t29
D15:0 Read Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI, INTR Setup Time NMI, INTR Hold Time PEREQ, ERROR#, BUSY#, FLT# Setup Time PEREQ, ERROR#, BUSY#, FLT# Hold Time
t30
4
4
5
(Note 4)
NOTES:
Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. These are not tested. They are guaranteed by characterization. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. These inputs may be asynchronous to CLK2. The setup and hold specifications are given for testing purposes to ensure recognition within a specific CLK2 period. 5. Minimum time not 100% tested. 1. 2. 3. 4.
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Intel386TM SXSA EMBEDDED MICROPROCESSOR
CPU Output CL
A2200-0A
Figure 6. AC Test Loads
t t t A B C t5 2a 2b
1
CLK2
t3b t3a
t4
A = Vcc -.8 B = 2.0V C = .8V
A2291-0A
Figure 7. CLK2 Waveform
16
Intel386TM SXSA EMBEDDED MICROPROCESSOR
TX CLK2
PH2
PH1
TX
PH2
PH1
TX
t19 READY#
t20
t23 HOLD t21 D15:0 (Input) BUSY# ERROR# PEREQ FLT# t29
t24
t22
t30
t15 NA# t27 INTR NMI
t16
t28
A2292-01
Figure 8. AC Timing Waveforms -- Input Setup and Hold Timing
17
Intel386TM SXSA EMBEDDED MICROPROCESSOR
TX CLK2
PH2
PH1
TX
PH2
PH1
TX
t8 BHE#, BLE# LOCK# Valid n t10 W/R#, M/IO# D/C#, ADS# Valid n t6 A23:1 Valid n
Min
Max Valid n+1
Min
Max Valid n+1
Min
Max Valid n+1 t12,t12a Min Max Valid n+1
D15:0 (Output)
Valid n
HLDA
A2293-01
Figure 9. AC Timing Waveforms -- Output Valid Delay Timing
18
Intel386TM SXSA EMBEDDED MICROPROCESSOR
Th PH2 CLK2 t8 t9 BHE#, BLE# LOCK# t11 W/R#, M/IO# D/C#, ADS# t7 A23:1 t13 D15:0 Min Min Max Min Max (High Z) Min Max t10 (High Z) t6 (High Z) Max Min Min Min PH1 PH2 PH1
TI or T1 PH2
Max
Max
Max
t12 (High Z)
Min
Max
t13 Also applies to data float when write cycle is followed by read or idle. t14 HLDA
A2294-01
Min
Max
t14
Min
Max
Figure 10. AC Timing Waveforms -- Output Float Delay and HLDA Valid Delay Timing
19
Intel386TM SXSA EMBEDDED MICROPROCESSOR
Reset PH2 or PH1 CLK2 t26 RESET t25 PH2 or PH1
Initialization Sequence PH2 PH1
A2205-0A
Figure 11. AC Timing Waveforms -- RESET Setup and Hold Timing and Internal Phase
6.0
REVISION HISTORY
This -003 data sheet contains the following changes from the -002 version. * Changed VCC at 40 MHz to 4.75V to 5.25V (Pages 1 and 9) * Renamed "Powerdown Mode" to "Clock Freeze Mode" on page one. * Added clarifications to Figure 1. * Corrected pin numbering for A23:1 in Table 2 * Changed the first sentence in Section 3.3 from "...on page 12" to "...on page 9." * Changed the first sentence on page 12 from "Table 7 lists..." to "Table 6..." Also changed the first sentence of the fourth paragraph on page 12 from "...A25:1" to "...A23:1."
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