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LTC1658 14-Bit Rail-to-Rail Micropower DAC in MSOP
FEATURES
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DESCRIPTION
The LTC(R)1658 is a single supply, rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC) in an 8-lead MSOP package. It includes an output buffer amplifier and an easy-to-use 3-wire cascadable serial interface. The LTC1658 output swings from 0V to VREF. The REF pin can be tied to VCC for rail-to-rail output swing. The LTC1658 operates from a single 2.7V to 5.5V supply. The typical power supply current is 270A. The low power supply current makes the LTC1658 ideal for battery-powered applications. The space saving MSOP provides the smallest 14-bit DAC system available.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
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14-Bit Resolution 8-Lead MSOP Package Buffered True Rail-to-Rail Voltage Output 3V or 5V Single Supply Operation Very Low Power: ICC(TYP) = 270A Power-On Reset 3-Wire Cascadable Serial Interface is Compatible with SPI and MICROWIRETM Maximum DNL Error: 1LSB Low Cost
APPLICATIONS
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Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones
TYPICAL APPLICATION
Functional Block Diagram: 14-Bit Rail-to-Rail DAC
2.7V TO 5.5V 8 VCC 2 DIN 1 CLK P 3 CS/LD 16-BIT SHIFT REG AND DAC LATCH 14 14-BIT DAC 6 REF
+ -
VOUT
7
DNL ERROR (LSB)
RAIL-TO-RAIL VOLTAGE OUTPUT
4 DOUT TO OTHER DACS POWER-ON RESET GND 5
1658 TA01
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Differential Nonlinearity vs Input Code
1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 0 4096 8192 CODE 12288 16383
1658 TA02
1
LTC1658 ABSOLUTE MAXIMUM RATINGS
VCC to GND .............................................. - 0.5V to 7.5V TTL Input Voltage .................................... - 0.5V to 7.5V VREF ..........................................................- 0.5V to 7.5V VOUT ........................................... - 0.5V to (VCC + 0.5V) Junction Temperature .......................... - 65C to 125C
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW CLK DIN CS/LD DOUT 1 2 3 4 8 7 6 5 VCC VOUT REF GND
LTC1658CMS8 LTC1658IMS8 MS8 PART MARKING LTCW LTFW
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 250C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL DAC Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity Zero Scale Error VREF VCC - 0.1V (Note 2) VREF VCC - 0.1V (Note 2) TA = 25C, N8 and S8 Package TA = TMIN to TMAX, N8 and S8 Package TA = TMIN to TMAX, MSOP Package TA = 25C, N8 and S8 Package, (Note 7) TA = TMIN to TMAX, N8 and S8 Package, (Note 7) TA = TMIN to TMAX, MSOP Package, (Note 7)
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PARAMETER
CONDITIONS
Offset Error
VOSTC
Offset Error Temperature Coefficient Gain Error Gain Error Drift
q
Power Supply VCC ICC Positive Supply Voltage Supply Current Short-Circuit Current Low Short-Circuit Current High For Specified Performance 2.7V VCC 5.5V (Note 4) VOUT Shorted to GND VOUT Shorted to VCC
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Op Amp DC Performance
q q
2
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W
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(Note 1)
Operating Temperature Range Commercial ............................................ 0C to 70C Industrial ............................................. -40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
TOP VIEW CLK 1 DIN 2 CS/LD 3 DOUT 4 N8 PACKAGE 8-LEAD PDIP 8 7 6 5 VCC VOUT REF GND
ORDER PART NUMBER LTC1658CN8 LTC1658IN8 LTC1658CS8 LTC1658IS8 S8 PART MARKING 1658 1658I
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 100C/W(N8) TJMAX = 125C, JA = 150C/W(S8)
MIN 14 14
TYP
MAX
UNITS Bits Bits
1.0 8.0 1.5 4.0 7.0 1.5 4.0 7.0 5 20 2.5 2.7 270 55 55 5.5 550 120 120
LSB LSB mV mV mV mV mV mV V/C LSB ppm/C V A mA mA
LTC1658
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER Output Impedance to GND Output Line Regulation AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Reference Input RIN VREF Digital I/O VIH VIL VOH VOL VIH VIL VOH VOL ILEAK CIN t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 t2 t3 t4 t5 t6 t7 t8 t9 Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CLOAD = 15pF (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CLOAD = 15pF (Note 6) VCC = 5V VCC = 5V VCC = 5V, IOUT = - 1mA, DOUT Only VCC = 5V, IOUT = 1mA, DOUT Only VCC = 3V VCC = 3V VCC = 3V, IOUT = - 1mA, DOUT Only VCC = 3V, IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 6)
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CONDITIONS Input Code = 0 Input Code = 16383, VCC = 2.7V to 5.5V, REF = 2.5V
q q
MIN
TYP 70
MAX 200 1.5
UNITS mV/V V/s s nV * s k
0.35
1.0 12 0.3
(Note 3) to 0.5LSB
REF Input Resistance REF Input Range (Notes 5, 6)
q q
30 0 2.4
60 VCC
V V
0.8 VCC - 0.7 0.4 2.0 0.6 VCC - 0.7 0.4 10 10 40 0 40 40 50 40 20 5 20 60 0 60 60 80 60 30 10 30 150 100
V V V V V V V A pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching (VCC = 4.5V to 5.5V)
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Switching (VCC = 2.7V to 5.5V)
q q q q q q q q q
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LTC1658
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life a device may be impaired. Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale). See Applications Information. Note 3: DAC switched between code 16383 and code 50. Note 4: Digital inputs at 0V or VCC. Note 5: VOUT can only swing from (GND + VOS) to (VCC - VOS) when output is unloaded. See Applications Information. Note 6: Guaranteed by design. Not subject to test. Note 7: Measured at code 50.
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL) vs Input Code
5 4 3
INL ERROR (LSB)
DNL ERROR (LSB)
2 1 0 -1 -2 -3 -4 -5 0 4096 8192 CODE 12288 16383
1658 G01
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 CODE 12288 16383
1658 G02
SUPPLY CURRENT (mA)
Minimum Supply Headroom for Full Output Swing vs Load Current
1.0 OUTPUT PULL-DOWN VOLTAGE (V) 0.9 0.8 0.7 VCC - VOUT (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 LOAD CURRENT (mA) 15
1658 G04
VOUT < 1LSB CODE: ALL 1s VOUT = 4.096V 125C
OFFSET ERROR (LSB)
4
UW
25C -55C
Differential Nonlinearity (DNL) vs Input Code
1.0 0.8 0.6
2 3
Supply Current vs Logic Input Voltage
ALL DIGITAL INPUTS TIED TOGETHER
1
0 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 5
1658 G03
Minimum Output Voltage vs Output Sink Current
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 OUTPUT SINK CURRENT (mA) 15
1658 G05
Offset Error vs Temperature
0 -0.5 -1.0
CODE: ALL ZEROS
125C
-1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -55 -25 5 35 65 TEMPERATURE (C) 95 125
1658 G06
25C
-55C
LTC1658 TYPICAL PERFOR A CE CHARACTERISTICS
Gain Error vs Temperature
5 4 3
GAIN ERROR (LSB)
2 1 0 -1 -2 -3 -4 -5 -55 -25 5 35 65 TEMPERATURE (C) 95 125
1658 G06
PIN FUNCTIONS
CLK (Pin 1): The TTL Level Input for the Serial Interface Clock. DIN (Pin 2): The TTL Level Input for the Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock and is loaded MSB first. The LTC1658 requires a 16-bit word to be loaded in. The last two bits are don't cares. CS/LD (Pin 3): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. DOUT (Pin 4): Output of the Shift Register Which Becomes Valid on the Rising Edge of the Serial Clock. GND (Pin 5): Ground. REF (Pin 6): Reference Input. There is a gain of one from this pin to the output. When tied to VCC the output will swing from GND to VCC. The output can only swing to within it's offset specification of VCC (see Applicatons Information). VOUT (Pin 7): Buffered Rail-to-Rail DAC Output. VCC (Pin 8): Positive Supply Input. 2.7V VCC 5.5V.
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Broadband Noise
1LSB/DIV
BW = 1Hz TO 100kHz
200s/DIV
1658 G08
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LTC1658
TI I G DIAGRA W
t1 t2 CLK t9 B13 MSB B0 LSB BX DUMMY BX DUMMY t4 t3 t6 t7 B12 B11 t8 t5 B12 B11 BX BX B13 CURRENT WORD
1658 TD
DEFI ITIO S
Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB Where VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Gain Error: Gain error is the difference between the output of a DAC from its ideal full-scale value after offset error has been adjusted. Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/16383)]/LSB Where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/16384 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero.
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DIN
CS/LD
DOUT
B13 PREVIOUS WORD
LTC1658
OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The input word must be 16 bits wide. The last two bits are don't cares. The buffered output of the 16-bit shift register is available on the DOUT pin which swings from GND to VCC. Multiple LTC1658s may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip while the clock and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of
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the chips then the CS/LD signal is pulled high to update all of them simultaneously. Voltage Output The LTC1658 rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 400mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40, at 5V VCC, when driving a load to the rails. The output can drive 1000pF without going into oscillation. The output swings from 0V to the voltage at the REF pin, i.e., there is a gain of 1 from REF to VOUT. Please note, if REF is tied to VCC the output can only swing to (VCC - VOS). See Applications Information.
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LTC1658
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 1b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 1c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
OUTPUT VOLTAGE
0
OUTPUT VOLTAGE
0V NEGATIVE OFFSET INPUT CODE (b)
1658 F01
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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VREF = VCC
POSITIVE FSE
OUTPUT VOLTAGE
INPUT CODE (c) VREF = VCC
8192 INPUT CODE (a)
16383
LTC1658
TYPICAL APPLICATIO S
An Optoisolated 4mA to 20mA Process Controller
VLOOP 3.8V TO 30V LT(R)1121-3.3 IN OUT 237k 1% 20k
+
1F VCC REF VOUT 60.4k 1% 5k 3.01k 1%
FROM OPTOISOLATED INPUTS
OPTOISOLATORS
CLK DIN CS/LD
500
This circuit shows how to use an LTC1658 to make an optoisolated digitally controlled 4mA to 20mA process controller. The controller circuitry, including the optoisolation, is powered by the loop voltage that can have a wide range of 3.8V to 30V. The 3.3V output of the LT1121-3.3 is used for the 4mA offset current and VOUT is
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CLK DIN
LTC1658
+
LT1077
1k
CS/LD
Q1 2N3440
-
RS 10 3.3V
1658 TA04
IOUT CLK DIN CS/LD
3.6k
4N28
used for the digitally controlled 0mA to 16mA current. RS is a sense resistor and the op amp modulates the transistor Q1 to provide the 4mA to 20mA current through this resistor. The potentiometers allow for offset and full-scale adjustment. The control circuitry dissipates well under the 4mA budget at zero-scale.
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LTC1658
TYPICAL APPLICATIO S
A 14-Bit Analog Input/Output Channel for a PC
5V D1 510 DIFFERENTIAL INPUT 510 D3 D4 1F 10F D2 510 1 510 2 3 4 5 6 7 8 AIN + AIN - VREF VREFCOMP AGND EXTCLKIN SCLK CLKOUT U1 LTC1417 VCC VSS BUSY CONVST RD SHDN DGND DOUT 16 15 14 13 12 11 10 9 1F
U2 LTC1658 1 2 3 4 CLK DIN CS/LD DOUT VCC VOUT REF GND ANALOG OUTPUT 8 7 6 5
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1F 2 4 3 D
U3 1/2 74HC74 Q CLR Q 5 1 6 5V PR CK C5 47F
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U4 LT1021-5 4
2 C4 150F
D6
D5
4
3
2
1
51k SELECT
TX
8
9
6
5
51k DIN
RTS
U3 1/2 74HC74 12 10 11 D PR CK Q CLR Q 9 13 8 5V
12
13 51k SCLK
DTR
11
10
DOUT
CTS
C3 0.1F 5V
1658 TA05 1658 TA05
LTC1658
PACKAGE DESCRIPTION U
Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 0.004* (3.00 0.102) 0.040 0.006 (1.02 0.15) 0.007 (0.18) 0.021 0.006 (0.53 0.015) 0 - 6 TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP 0.192 0.004 (4.88 0.10) 0.118 0.004** (3.00 0.102) 0.034 0.004 (0.86 0.102) 8 76 5
0.006 0.004 (0.15 0.102)
MSOP (MS8) 1197
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
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N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 - 0.325 (7.620 - 8.255) 0.045 - 0.065 (1.143 - 1.651) 0.130 0.005 (3.302 0.127) 0.400* (10.160) MAX 8 7 6 5
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076)
0.255 0.015* (6.477 0.381)
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
1
2
)
3
4
0.100 0.010 (2.540 0.254)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 8 7 6 5
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
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4
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1658
TYPICAL APPLICATION
14-Bit, 3V to 5V Single Supply, Voltage Output DAC
2.7V TO 5.5V
RELATED PARTS
PART NUMBER LTC1257 LTC1446/LTC1446L LTC1448 LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1456 LTC1458/LTC1458L LTC1659 DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V Dual 12-Bit VOUT DACs in SO-8 Package Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality Single Rail-to-Rail 12-Bit VOUT DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 5V, Low Power Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Multiplying VOUT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC. Ultralow Drift 5ppm/C, Initial Accuracy: 0.05% Low Drift 10ppm/C, Initial Accuracy: 0.05%
References LT1019 LT1634 Precision Voltage Reference Micropower Precision Reference
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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0.1F DIN VCC P CLK LTC1658 CS/LD DOUT TO NEXT DAC FOR DAISY-CHAINING GND REF VOUT OUTPUT 0V TO REF
1658 TA03
1658f LT/TP 0299 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

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