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E2B0017-27-Y2
Semiconductor MSC5301B-01
Semiconductor LCD COMMON/SEGMENT DRIVER WITH RAM
This version: Nov. 1997 MSC5301B-01 Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSC5301B-01 is an LCD driver LSI with built-in RAM. The device's bit mapping method offers greater flexibility because each bit of the RAM for display controls each section on the LCD panel. It can form a graphic display system of 64 x 16 dots in one chip. In addition, the display can be expanded by using additional LSIs.
FEATURES
* LCD driving voltage range : 6 to 16V * Operating power supply voltage range : 5V 10% * Display duty : 1/16 (1/5 bias) * Common output : 16 outputs * Segment output : 64 outputs * RAM capacity : 16 x 64 = 1024 bits * Serial transfer clock frequency (fSCK) : 500 kHz Max. * Multichip configuration available * Blanking available * Built-in RC oscillation circuit * Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name: MSC5301B-01GS-BK)
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MSC5301B-01
BLOCK DIAGRAM
V4 V1 C0 C15 VDSP S63 S0 V2 V3
VDSP 16-DOT COM DRV (4-LEVEL DRV) 64-DOT SEG DRV (4-LEVEL DRV) GND VCC GND 4-16 DECODER 64-BIT LATCH
4-BIT LATCH
RA3 RA2 RA1
RAM 64x16 =1024 BITS
WA3 WA2 WA1 WA0 WE
READ (4-BIT) ADDRESS COUNTER
RA0
TIMING GENERATOR
64-BIT LATCH INPUT CTL
64-BIT SHIFT REGISTER LATCH
CHIP CTL
A/D
SI BLK CTL FRAM IN/OUT POR OSC 8-BIT SHIFT REGISTER CTL CS1 CSO 6-BIT LATCH SCK
OS1
OS2
BLK
POR
FRAM
VCC
GND
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
100 S52 99 S51 98 S50 97 S49 96 S48 95 S47
S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 V4 V1 CS0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
,
94 S46 93 S45 92 NC 91 S44 90 S43 33 34 35 36 37 38 39 40 41
MSC5301B-01
89 S42 88 S41
87 S40 86 S39 85 S38
84 S37
83 S36
82 S35 81 S34
80 S33 79 S32 78 S31 77 S30 76 S29 75 S28 74 S27 73 S26 72 S25 71 S24 70 S23 69 S22 68 S21 67 S20 66 S19 65 S18 64 S17 63 S16 62 S15 61 S14 60 S13 59 S12 58 S11 57 S10 56 S9 55 S8 54 S7 53 S6 52 S5 51 S4
31 32
42
43
44
45 46
47
48
49
CS1 LATCH A/D SI SCK POR BLK FRAM OS1 OS2 VCC GND VDSP V2 V3 S0 S1 S2 S3
NC: No connection 100-Pin Plastic QFP
50
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Power Supply Voltage Input Voltage Input Voltage Power Dissipation Storage Temperature Symbol VCC VDSP VIN VINDP PD TSTG Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 85C -- Rating -0.3 to +6.5 -0.3 to +18.0 *1 -0.3VVINVCC+0.3 -0.3VINDPVDSP+0.3 275 -55 to +125 Unit V V V V mW C
*1
VDSP>V1>V2>V3>V4>GND
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Power Supply Voltage Operating Temperature Shift Frequency Oscillation Frequency Frame Frequency Symbol VCC VDSP Top fSCK f fFR Condition GND = 0V GND = 0V -- -- -- -- Range 4.5 to 5.5 6.0 to 16.0 *1 -40 to +85 25 to 500 3.84 to 16.0 60 to 250 Unit V V C kHz kHz Hz
*1
VDSP>V1>V2>V3>V4>GND
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ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage Hysteresis Voltage 1 Hysteresis Voltage 2 Pull-up Resistance Pull-up Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage Common Driver Output Voltage Symbol VIH VIL VHS1 VHS2 RPU VPH IIH IIL VOH VOL VDP V1 V4 VSS Segment Driver Output Voltage VDP V2 V3 VSS Supply Current 1 Supply Current 2 ICC IDSP VCC = 5.0V VCC = 5.0V VDSP = 10V *6 VI = 0V II < 1mA VCC = 5.5V, VIH = 5.5V VCC = 5.5V, VIL = 0V IO = -0.4mA IO = 1.6mA VDSP = 10V *5 I = -10mA I = 10mA I = 10mA I = +10mA I = -10mA I = 10mA I = 10mA I = +10mA *7 *8 Condition -- -- -- -- *1 *1 *2 *9 *2 *2 *3 *3 *4 *4 Min. 3.5 0 0.3 0.2 10 4.9 -- -- 4.6 -- VDSP-0.4 V1-0.4 V4-0.4 -- VDSP-0.4 V2-0.4 V3-0.4 -- -- -- (VCC = 5V, Ta=-40 to +85C) Typ. -- -- 0.8 0.4 35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. VCC 1.5 1.4 0.8 60 -- 10 10 -- 0.4 -- V1+0.4 V4+0.4 0.4 -- V2+0.4 V3+0.4 0.4 6.0 0.5 Unit V V V V kW V mA mA V V V V V V V V V V mA mA
*1 *2 *3 *4 *5 *6 *7
Applicable to all input pins Applicable to LATCH, A/D, SI, SCK, BLK and POR pins Applicable to CS0, CS1, OS1 and FRAM pins Applicable to FRAM and f pins Applicable to C0 - C15 pins Applicable to S0 - S63 pins ff = 6.4 kHz, fSCK = 200 kHz, no load, display pattern = checkers VDSP = 16V, Current flows into VCC pin *8 ff = 6.4 kHz, fSCK = 200 kHz, no load, display pattern = checkers VDSP = 16V, Current flows into VDSP pin *9 Applicable to OS1 pin
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Semiconductor AC Characteristics
MSC5301B-01
(VCC = 5V, Ta = -40 to +85C) Parameter SCK Clock Period SI Data Setup Time SI Data Hold Time SCK-LATCH Time LATCH Pulse Width A/D Setup Time A/D Hold Time A/D-SCK Time POR, BLK Fall Time f, FRAM Rise Time f, FRAM Fall Time Frame Frequency Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 fFR Condition -- -- -- -- -- -- -- -- -- CL = 50 pF CL = 50 pF *1 Min. 2 1 1 1 15 1 1 1 -- -- -- 85 Typ. -- -- -- -- -- -- -- -- -- -- -- 100 Max. -- -- -- -- -- -- -- -- 20 0.3 0.3 115 Unit ms ms ms ms ms ms ms ms ms ms ms Hz
*1
The dispersion of external resistors and capacitors is not included. RS = 1k, RT = 16k, CT = 4700pF, VCC = 4.5V to 5.5V
t1 SCK t2 t3
SI
t4
t5
t7
LATCH
t6 A/D
t8
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MSC5301B-01
VCC 90%
POR, BLK
10% GND t9
VCC 90% f, FRAM
10% GND t11 t10
VDSP V1 C0 V4 GND 1/fFR Frame A 1/fFR Frame B
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FUNCTIONAL DESCRIPTION
Pin Functional Description * OS1 (Pin 39), OS2 (Pin 40), f (Pin 41) These are pins for the RC oscillation circuit. Connect external resistors and a capacitor as shown below. When inputting the external clock pulse, input it to OS1 pin. OS2 and f pins should be left open.
OS1
OS2
f
RS
CT
RT
The relationship between the frame frequency fFR and internal clock frequency ff is expressed by the following equation: (RC oscillation frequency = internal clock frequency) ff = 4 x 16 x fFR In addition, the relationship between the frame frequence fFR and frame synchronizing signal frequency fFRAM is expressed by the following equation. fFRAM = fFR/2 * CS0 (Pin 30), CS1 (Pin 31) Chip select input pins. Master or slave mode is selected by CS0 and CS1 as shown in the table below. A maximum of 4 chips can be connected in this manner. Use the master mode when using a single device.
CS0 L H L H CS1 L L H H Operation mode Master mode Slave mode Slave mode Slave mode H : VCC level L : GND level
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* FRAM (Pin 38) This is an input and output pin for the frame synchronizing signal to be used for master/slave configuration. This is used as an output pin in master mode and as an input pin in slave mode. * SI (Pin 34) This is a serial data input of address data (8 bits) and segment data (64 bits). A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained. * SCK (Pin 35) This is a shift clock input of address data (8 bits) and segment data (64 bits). The serial data is shifted at the rising edge of SCK pulse. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained. * LATCH (Pin 32) This is a latch pulse input of address data (8 bits) and segment data (64 bits). The latch data comes through at "H" level of LATCH and the data just before "H" level is latched at "L" level. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained. * A/D (Pin 33) This is a data select signal input of address data (8 bits) and segment data (64 bits). "H" level is set in the case of address 8-bit input and "L" level is set in the case of segment data 64-bit input. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained. * VDSP (Pin 44), V1 (Pin 29), V2 (Pin 45), V3 (Pin 46), V4 (Pin 28), VCC (Pin 42), GND (Pin 43) These are power supply pins for this LSI and bias power supply pins for LCD driving. VCC, which is a power supply pin, is from 4.5V to 5.5V and GND, which is a ground pin, is 0V. VDSP, which is an LCD driving power supply pin, is usually used in the range between 6V and 16V. V1, V2, V3 and V4 are bias power supply pins for LCD driving and are usually used with the bias voltage supplied from an external source.
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* BLK (Pin 37) This is an input pin to control the LCD panel display. When a "H" level is input (or when this pin is open), the segment output pins S0 - S63 come to the levels V2 - V3 and the LCD panel is turned off. In addition, during this period, reading of data from display RAM stops but writing into the display RAM of address and segment data input from the SI pin is enabled. When this pin is changed from "H" to "L" level, the frame synchronizing signal FRAM is output within 2 cycles of an internal clock ff, and multiple chips are synchronized. Then, the display RAM address is set to "0000". After 1/16 frame cycle from FRAM signal generation, the output is applied from the "0001" data of the display RAM address to the segment driver. When the power supply is turned on, keep this pin to "H" level (or leave open) until writing data to the RAM is completed, because the display RAM contents are undefined at power-on. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained. * POR (Pin 36) This is a power-on-reset input pin. When a "H" level is input (or when this pin is open), the common and segment outputs come to the static display-off state regardless of the BLK pin and the segment output pins S0 - S63 become V3 level and the common output pins C0 - C15 become V4 level. When this pin changes from "H" to "L" level, the frame synchronizing signal FRAM is output within 2 cycles of an internal clock ff, synchronized at multichip, and is moreover dynamicoperated from the frame B . The display RAM address is set to "0000." After 1/16 frame cycle from FRAM signal generation, the data at display RAM address "0001" is output to the segment driver. However, because the BLK pin is usually at "H" level when the power-on-reset is released, reading data from the display RAM stops and display-off segment data is forcibly transferred to the segment output. A pull-up resistor (10 kW - 60 kW) and a Schmitt are contained. * C0 (Pin 12) - C15 (Pin 27) These are 16-output pins of common driver which are used for LCD panel driving. The outputs have 4 levels. VDSP and GND levels are select levels. The V1 and V4 levels are non-select levels. * S0 (Pin 47) - S63 (Pin 11) These are 64-output pins of segment driver which are used for LCD panel driving. The outputs have 4 levels. VDSP and GND levels are used as display-on ones, which correspond to "1" of the display RAM data. V2 and V3 levels are used as display-off ones, which correspond to "0" of the display RAM data.
NOTES ON USE
Note the following when turning power on and off: The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-on and power-off sequences: When turning power on: First turn VCC ON, next VDSP, V4, V3, V2, V1 ON. Or both ON at the same time. When turning power off: First turn VDSP, V4, V3, V2, V1 OFF, next VCC OFF. Or both OFF at the same time.
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Semiconductor Relationship Between LCD Screen Size and Display RAM
MSC5301B-01
This LCD driver has built-in RAM for the display of 16 x 64 = 1024 bits and each address corresponds to each 1/16 duty of the LCD. The data corresponds to the number of dots in the X direction. The relation between the LCD screen size and the display RAM is shown below.
Address Data A3 A2 A1 A0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Number of dots in X direction (64) S63 S0 C0 C1 C2 C3 C4 C5 C7 C8 C9 C10 C11 C12 C13 C14 C15 C6
Relationship Between Frame Cycle and Display RAM Data The output of the display RAM data corresponds to the segment output. The relationship between the frame cycle and the display RAM data is as follows:
First line address
Segment output (Contents of RAM)
0000
0001
0010
0011
1110
1111
0000
1/16 duty
0001
1 frame cycle
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Semiconductor Multiple Configuration
MSC5301B-01
This LCD driver can form multiple configuration. It is possible to form a maximum of 4 devices (a panel of up to 256 16 dots in size can be formed) by using chip select signals CS0 and CS1. The devices in multiple configuration must be synchronized with one another. In this configuration, one device in the master mode and the other devices in the slave mode are used in combination. In the master mode, the original oscillation signal f and the synchronous signal FRAM are output; in the slave mode, the original oscillation signal f and the synchronous signal FRAM are input. Refer to items CS0 and CS1 of pin description on the mode setting method. The original oscillation signal output pin f of the master mode device is connected to the OS1 pin of the slave mode device and the synchronizing signal pin FRAM is also connected to the FRAM pin of the slave mode device. Connect SI, SCK, LATCH, A/D, POR and BLK of the master mode device to SI, SCK, LATCH, A/D, POR and BLK of each of the slave mode devices and connect them to CPU for control. In addition, connect the devices so that VDSP, V1, V2, V3, V4 and GND are shared between the devices, and connect them to each voltage level divided by external resistors.
Address Data Configuration
(MSB) 7 6 5 4 Dummy data Upper address DM DM CS1 CS0 3 A3 2 1 Lower address A2 A1 (LSB) 0 A0
2 bits
2 bits
4 bits
The lower address, which is the display RAM address, corresponds to the common sides C0 - C15 of the LCD panel. The upper address corresponds to the logical state of chip select pins CS0 and CS1 and the lower address is set to the device. For the device to output the common signal (f, FRAM), set both of the upper address 2 bits to "L". The 2 bits of dummy data can be set to either "L" or "H".
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Semiconductor Serial Signal to be Input From CPU The following signals are input from an external CPU to this LCD driver. - Serial transfer clock AE SCK - Serial transfer data AE SI - Serial transfer latch AE LATCH - Serial data select AE A/D The operations are shown in the following table.
Mode Address data input mode Segment data input mode A/D H SCK Shifts at LATCH 8-bit address latch at falling 8-bit address data SI
MSC5301B-01
the rising edge edge (level sensitive) Shifts at 64-bit segment data latch at
Serial input from LSB side 64-bit segment data Serial input from S63 corresponding data "1" : Display-on data, "0" : Display-off data
L
the rising edge falling edge (level sensitive)
Timing Chart of Serial Signal Transferred From CPU
A/D
"H" at address data setting
"L" at segment data setting
1
2
3
4
5
6
7
8
1
2
3
63 64
SCK
A0 A1 A2 A3 CS0 CS1 Dummy Dummy
S63 S62 S61
S1
S0
SI
LSB
MSB Address data (8 bits) Segment data (64 bits)
LATCH Address latch signal RAM write signal
Notes: 1. Make sure to set the address before writing the segment data to RAM. Then, write the segment data to RAM. 2. While the POR pin is "H" (upon power-on reset), neither the address data nor the segment data can be entered.
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Operation upon Power ON (When Single Device Used)
Semiconductor
VCC
POR
BLK
f (External R and C)
FRAM
Common signal output Segment signal output Frame A
Frame B
Frame A
Frame B
Frame B
Frame A
Frame B
Frame A
Dynamic light-out state RAM address 0-F 0-F 0-0 0-F
Dynamic operation (normal operation) 0-F 0-F 0-F
MSC5301B-01
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PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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