View TMS57002PH_190374.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TMS57002PH(1/3) IL00D
C-MOS DIGITAL AUDIO SIGNAL PROCESSOR
--TOP VIEW--
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC
GND GND
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VDD VDD
NC NC
NC NC
NC(TMS57002PH) NC NC VDD GND NC
VDD GND
NC NC NC
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
I/O I I -- -- I O O O O I I -- -- O I/O I/O I/O I/O I/O I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SIGNAL SYNPOL BCKO NC NC LRCKO SO0 SO1 CAS RAS CLKSEL CLKIN GND GND WE ED0 (LSB) ED1 ED2 ED3 ED4 ED5
PIN NO. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
I/O -- -- I/O I/O O O -- O -- O O -- -- O O -- O I I I
PIN NO. NC 41 NC 42 ED6 43 ED7 (MSB) 44 EA0 (LSB) 45 EA1 46 NC 47 EA2 48 NC 49 EA3 50 EA4 51 GND 52 VDD 53 54 EA5 55 EA6 56 NC 57 EA7 58 TEST0 59 TEST1 60 TEST2 SIGNAL
I/O O O -- -- I I I I -- I I -- -- I I O I O O I
SIGNAL EA8 EA9 (MSB) NC NC D0 (LSB) D1 D2 D3 NC D4 D5 VDD VDD D6 D7 (MSB) PC0 BIO OVFA OVFM RS
NC NC
PIN I/O SIGNAL NO. NC 61 -- NC 62 -- EMPTY 63 O MUTE I 64 CS I 65 WR I 66 PLOAD I 67 68 O NC/DREADY* CLOAD I 69 STRB I 70 NC 71 -- VDD 72 -- 73 -- GND 74 -- NC I 75 BCKI I 76 LRCKI 77 -- NC I 78 SI0 I 79 SI1 I 80 SYNC * : TMS57002PH ; NC.
TMS57002PH(2/3)
78 79 6 7
SI0 SI1
SO0 SO1
75 2 76 5 80 11 10 1
BCKI BCKO LRCKI LRCKO SYNC CLKIN CLKSEL SYNPOL
PC0 EMPTY
56 63
EA9 EA8 EA7 EA6 EA5 EA4
42 41 37 35 34 31 30 28 26 25 8 9 14
INPUT BCKI BCKO BIO CLKIN CLKSEL CLOAD CS D0 - 7 DREADY LRCKI LRCKO MUTE PLOAD RS SI0, 1 STRB SYNC SYNPOL
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
60 66 65 67 69 64 57
RS WR CS PLOAD CLOAD MUTE BIO
EA3 EA2 EA1 EA0 CAS RAS WE
BIT CLOCK FOR SERIAL INPUT BIT CLOCK FOR SERIAL OUTPUT BRANCH CONTROL MASTER CLOCK CLKIN FREQUENCY SELECT (L ; 512 fs H ; 256 fs) COUNTING LOAD CHIP ENABLE FOR PARALLEL PORT PARALLEL PORT DATA READY SIGNAL TO HOST CONTROLLER RIGHT AND LEFT CHANNEL THRESHOLD CLOCK FOR SERIAL INPUT RIGHT AND LEFT CHANNEL THRESHOLD CLOCK FOR SERIAL OUTPUT MUTE PROGRAM LOAD RESET (L ; RESET H ; NORMAL OPERATION) SERIAL INPUT DATA 0, 1 DATA STROBE FOR PARALLEL PORT PROGRAM SYNC SIGNAL SYNC SIGNAL EFFECTIVE EDGE SELECT (L ; DOWN H ; UP)
55 54 51 50 48 47 46 45
D7 D6 D5 D4 D3 D2 D1 D0
ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0
15 16 17 18 19 20 23 24
TEST0 - 2 ; FOR TEST WR ; RIGHT ENABLE FOR PARALLEL PORT OUTPUT CAS EA0 - 9 EMPTY OVFA OVFM PC0 RAS SO0, 1 WE
70
STRB
OVFA OVFM
58 59
38 39 40
TEST0 TEST1 TEST2 DREADY 68
; ; ; ; ; ; ; ; ;
COL ADDRESS STROBE FOR OUTER EXTERNAL RAM OUTER EXTERNAL RAM ADDRESS COUNTING BUFFER EMPTY ALU OVERFLOW FLAG (OPEN DRAIN OUTPUT) MAC OVERFLOW FLAG (OPEN DRAIN OUTPUT) PROGRAM COUNTER 0 ROW ADDRESS STROBE FOR OUTER EXTERNAL RAM SERIAL OUTPUT DATA 0, 1 RIGHT ENABLE FOR OUTER EXTERNAL RAM
INPUT/OUTPUT ED0 - 7 ; OUTER EXTERNAL RAM DATA
TMS57002PH(3/3) PARALLEL PORT COEFFICIENT BUFFER 16 W x 32-BIT EXTERNAL RAM INTERFACE
PROGRAM RAM
DATA RAM BANK 0
DATA RAM BANK 1
COEFFICIENT RAM
CONTROL
256 W x 24-BIT
256 W x 24-BIT
32 W x 24-BIT
256 W x 32-BIT
D0 - 7 45 - 48, 50, 51, 54, 55 RAS (9), CAS (8), WE (14) EA0 - 9 26, 28, 30, 31, 34, 35, 37, 41, 42 ED0 - 7 (15 - 20, 23, 24)
T-REG
A-BUS-24-BIT B-BUS-32-BIT C-BUS-32-BIT D-BUS-24-BIT
SEQUENCE CONTROL
32-BIT 24-BIT MAC
32-BIT
32-BIT SERIAL PORT
CONTROL SI0, SI1 (78, 79) SO0, SO1 (6, 7)
ALU
STATUS REGISTER REPEAT COUNTER
24 x 32 + 52 = 52-BIT
ACC

▲Up To Search▲

Price & Availability of TMS57002PH

	To Download TMS57002PH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .