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AS4C256K16E0
(R)
5V 256Kx16 CMOS DRAM (EDO) Features
* Organization: 262,144 words x 16 bits * High speed - 30/35/50 ns RAS access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time * Low power consumption - Active: 500 mW max (AS4C256K16E0-25) - Standby: 3.6 mW max, CMOS I/O (AS4C256K16E0-25) * EDO page mode * Refresh - 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - Self-refresh option is available for new generation device only. Contact Alliance for more information. * Read-modify-write * TTL-compatible, three-state I/O * JEDEC standard packages - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II * 5V power supply * Latch-up current > 200 mA
Pin arrangement
SOJ
Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7
Pin designation
TSOP II
1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8
Pin(s) A0 to A8
RAS
Description Address inputs Row address strobe Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control Power (5V 0.5V) Ground
I/O0 to I/O15
OE UCAS LCAS
AS4C256K16E0
NC NC WE RAS NC A0 A1 A2 A3 VCC
AS4C256K16E0
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
WE
VCC GND
Selection guide
Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum EDO page mode cycle time Maximum operating current Maximum CMOS standby current
Shaded areas contain advance information.
AS4C256K16E0-30
30 16 10 10 65 12 180 2.0
AS4C256K16E0-35
35 18 10 10 70 14 160 2.0
AS4C256K16E0-50
50 25 10 10 85 25 140 2.0
Unit
ns ns ns ns ns ns mA mA
tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC2
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Copyright (c) Alliance Semiconductor. All rights reserved.
AS4C256K16E0
(R)
Functional description
The AS4C256K16E0 is a high performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4C256K16E0 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The AS4C256K16E0 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the 512 x 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design. Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following:
* RAS-only refresh cycles * Hidden refresh cycles * CAS-before-RAS refresh cycles * Normal read or write cycles * Self-refresh cycles*
The AS4C256K16E0 is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated testing and insertion equipment. System level features include single power supply of 5V 0.5V tolerance and direct interface with TTL logic families.
Logic block diagram
VCC GND REFRESH CONTROLLER
COLUMN DECODER SENSE AMP
DATA I/O BUFFER
I/O0 to I/O15
RAS
RAS CLOCK GENERATOR
UCAS LCAS
CAS CLOCK GENERATOR
A0 A1 A2 A3 A4 A5 A6 A7 A8
ADDRESS BUFFERS
OE
ROW DECODER 512x512x16 ARRAY (4,194,304)
SUBSTRATE BIAS GENERATOR
WE
WE CLOCK GENERATOR
Recommended operating conditions
Parameter Supply voltage Input voltage Symbol VCC GND VIH VIL Min 4.5 0.0 2.4 -1.0 Typ 5.0 0.0 - -
(Ta = 0C to +70C) Max 5.5 0.0 VCC + 1 0.8 Unit V V V V
*Self-refresh option is available for new generation device only. Contact Alliance for more information.
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AS4C256K16E0
(R)
Absolute maximum ratings
Parameter Input voltage Output voltage Power supply voltage Operating temperature Storage temperature (plastic) Soldering temperature x time Power dissipation Short circuit output current Latch-up current Symbol Vin Vout VCC TOPR TSTG TSOLDER PD Iout Min -1.0 -1.0 -1.0 0 -55 - - - 200 Max +7.0 +7.0 +7.0 +70 +150 260 x 10 1 50 - Unit V V V C C
o
C x sec
W mA mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC electrical characteristics
-30 Parameter
Input leakage current Output leakage current Operating power supply current
-35 Min
-10 -10 - -
-50 Min
-10 -10 - -
Symbol
IIL IOL ICC1
Test conditions
0V Vin +5.5V pins not under test = 0V DOUT disabled, 0V Vout +5.5V RAS, UCAS, LCAS, address cycling; tRC=min RAS = UCAS = LCAS = VIH RAS cycling, UCAS = LCAS = VIH, tRC = min RAS=UCAS=LCAS=VIL, address cycling: tSC = min RAS=UCAS=LCAS= VCC - 0.2V RAS, UCAS, LCAS, cycling; tRC = min IOUT = -5.0 mA IOUT = 4.2 mA RAS = UCAS = LCAS=VIL, WE = OE = A0-A8 = VCC-0.2V, DQ0-DQ15 = VCC-0.2V, 0.2V are open
Min
-10 -10 - -
Max
10 10 180 2.0
Max
10 10 160 2.0
Max Unit Note
10 10 140 2.0 A A mA mA 1,2
TTL standby power ICC2 supply current Average power supply current, RAS refresh mode EDO page mode average power supply current CMOS standby power supply current CAS-before-RAS refresh power supply current Output Voltage ICC3
-
200
-
190
-
140
mA
1
ICC4
-
190
-
180
-
70
mA
1,2
ICC5
-
1.0
-
1.0
-
1.0
mA
ICC6 VOH VOL ICC7
- 2.4 -
200 - 0.4
- 2.4 -
190 - 0.4
- 2.4 -
140 - 0.4
mA V V
1
Self refresh current
-
2.0
-
2.0
-
2.0
mA
Shaded areas contain advance information.
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AS4C256K16E0
(R)
AC parameters common to all waveforms
Std Symbol tRC tRP tRAS tCAS tRCD tRAD tRSH(R) tCSH tCRP tASR tRAH tT tREF tCLZ -30 Parameter Random read or write cycle time
RAS precharge time RAS pulse width CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS hold time (read cycle) RAS to CAS hold time CAS to RAS precharge time
-35 Max - - 75K - 20 14 - - - - - 50 8 - Min 70 25 35 6 16 11 10 35 5 0 6 1.5 - 0 Max - - 75K - 24 17 - - - - - 50 8 - Min 85 25 50 10 15 15 10 50 5 0 9 3 - 3
-50 Max - - 75K - 35 25 - - - - - 50 8 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ms ns 4,5 3 8 6 7 Notes
Min 65 25 30 5 15 10 10 30 5 0 5 1.5 - 0
Row address setup time Row address hold time Transition time (rise and fall) Refresh period
CAS to output in low Z
Shaded areas contain advance information.
Read cycle
Std Symbol tRAC tCAC tAA tAR(R) tRCS tRCH
tRRH
-30 Parameter Access time from RAS Access time from CAS Access time from address Column add hold from RAS Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS Lead time
CAS precharge time
-35 Max 30 10 16 - - - - - - 8 Min - - - 28 0 0 0 18 4 0 Max 35 10 18 - - - - - - 8 Min - - - 30 0 0 0 25 5 0
-50 Max 50 10 25 - - - - - - 8 Unit ns ns ns ns ns ns ns ns ns ns 8,10 9 9 Notes 6 6,13 7,13
Min - - - 26 0 0 0 16 3 0
tRAL tCPN tOFF
Output buffer turn-off time
Shaded areas contain advance information.
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AS4C256K16E0
(R)
Write cycle
Std Symbol tASC tCAH tAWR tWCS tWCH tWCR tWP tRWL tCWL tDS tDH -30 Parameter
Column address setup time
-35 Max - - - - - - - - - - - - Min 0 5 28 0 5 28 5 11 11 0 5 28 Max - - - - - - - - - - - - Min 0 9 30 0 9 30 9 12 12 0 9 30
-50 Max - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns 12 12 11 11 Notes
Min 0 5 26 0 5 26 5 10 10 0 5 26
Column address hold time Column address hold time to RAS Write command setup time Write command hold time Write command hold time to RAS Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time
tDHR Data-in hold time to RAS Shaded areas contain advance information.
Read-modify-write cycle
Std Symbol tRWC tRWD tCWD tAWD tRSH(W) -30 Parameter
Read-write cycle time RAS to WE delay time CAS to WE delay time
-35 Max - - - - - - Min 105 54 28 35 10 15 Max - - - - - - Min 120 60 30 40 12 15
-50 Max - - - - - - Unit ns ns ns ns ns ns 11 11 11 Notes
Min 100 50 26 32 10 15
Column address to WE delay time
CAS to RAS hold time (write)
CAS pulse width (write) tCAS(W) Shaded areas contain advance information.
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AS4C256K16E0
(R)
EDO page mode cycle
Std Symbol tPC tCAP tCP tPCM tCRW tRASP -30 Parameter
Read or write cycle time
-35 Max - 19 - - - 75K Min 14 - 4 58 46 35 Max - 21 - - - 75K Min 25 - 5 60 50 50
-50 Max - 23 - - - 75K Unit ns ns ns ns ns ns Notes 14 13
Min 12 - 3 56 44 30
Access time from CAS precharge
CAS precharge time
EDO page mode RMW cycle Page mode CAS pulse width (RMW)
RAS pulse width
Shaded areas contain advance information.
Refresh cycle
Std Symbol tCSR tCHR tRPC tCPT -30 Parameter
CAS setup time (CAS-before-RAS) CAS hold time (CAS-before-RAS)
-35 Max - - - - Min 10 8 0 8 Max - - - - Min 10 10 0 8
-50 Max - - - - Unit ns ns ns ns Notes 3 3
Min 10 7 0 8
RAS precharge to CAS hold time
CAS precharge time (CAS-before-RAS counter test)
Shaded areas contain advance information.
Output enable
Std Symbol tROH tOEA tOED tOEZ tOEH -30 Parameter
RAS hold time referenced to OE OE access time OE to data delay
-35 Max - 10 - 8 - Min 5 - 5 - 8 Max - 10 - 8 - Min 5 - 8 - 8
-50 Max - 10 - 8 - Unit ns ns ns ns ns 8 Notes
Min 5 - 5 - 8
Output buffer turnoff delay from OE
OE command hold time
Shaded areas contain advance information.
Self refresh cycle
Std Symbol tRASS tRPS tCHS -30 Parameter
RAS pulse width (CBR self refresh) RAS precharge time (CBR self refresh) CAS hold time (CBR self refresh)
-35 Max - - - Min 100K 85 30 Max - - - Min
-50 Max - - - Unit ns ns ns Notes
Min 100K 85 30
100K 85 30
Shaded areas contain advance information.
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AS4C256K16E0
(R)
Notes
1 2 3 ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL (min) GND and VIH (max) VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS tWS (min) and tWH tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD tRWD (min), tCWD tCWD (min) and tAWD tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCAP. tASC tCP to achieve tPC (min) and tCAP (max) values. These parameters are sampled and not 100% tested.
4 5 6 7 8 9 10 11
12 13 14 15
Key to switching waveform
Undefined/don't care Rising input Falling input
Read cycle waveform
tRC tRAS tRCD tRSH tRP
RAS
tCSH tCRP tASC tRCS tCAH tCAS
UCAS, LCAS
tRAD tASR tRAH tAR tRAL
Address
Row Address
Col Address
tRRH tRCH
WE
tROH
OE
tRAC tAA tOEA tCAC tCLZ tOEZ tOFF
I/O
Data Out
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AS4C256K16E0
(R)
Upper byte read cycle waveform
tRC tRAS tRP
RAS
tRCD tCSH tCRP tCAS tRSH tCRP
UCAS
tCRP
LCAS
tRAH tRAD tASR tASC tRAL tCAH
Address
Row
tRCS
Column
tRCH tRRH tROH
WE OE
tOEA tRAC tAA tCAC tCLZ tOFF tOEZ
Upper I/O Lower I/O
Data Out
Lower byte read cycle waveform
tRAS tRC tRP
RAS
tRCD tCSH tCRP tCAS tRSH tCRP
LCAS
tCRP
UCAS
tRAH tRAD tASR tASC tRAL tCAH
Address WE
Row
tRCS
Column
tRRH tROH tRCH
OE Upper I/O
tOEA tRAC tAA tCAC tCLZ tOFF tOEZ
Lower I/O
Data Out
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AS4C256K16E0
(R)
Early write cycle waveform
tRC tRAS tRP
RAS
tCSH tRSH tCRP tRCD tAWR tRAD tASC tASR tRAH tCAH tRAL tCAS
UCAS, LCAS
Address
Row Address
Col Address
tWCR tCWL tRWL tWP tWCS tWCH
WE
OE
tDHR tDS tDH
I/O
Data In
Upper byte early write cycle waveform
tRC tRAS tRP
RAS
tAWR tASR tRAH tRAD tRAL
Address
Row Address
tASC tRCD
Column Address
tCAH tRSH tCSH tCAS tRPC tCWL tWCS tRWL tWCR tWP tWCH tCRP
tCRP
UCAS
tCRP
LCAS
WE OE
tDHR tDS tDH
Upper I/O Lower I/O
Data In
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AS4C256K16E0
(R)
Lower byte early write cycle waveform
tRAS tRC tRP
RAS
tRAD tASR tRAH tAWR tRAL
Address UCAS
Row Address
tCRP
Column Address
tRPC tASC tRCD tCSH tCAH tCAS tRSH tWCR tRWL tCWL tWCS tWP tWCH tCRP
tCRP
LCAS
WE OE Upper I/O
tDHR tDS tDH
Lower I/O
Data In
Write cycle waveform
tRC tRAS tRP
(OE controlled)
RAS
tCSH tCRP tRCD tRSH tCAS tRAL tAWR tRAD tASR tRAH tASC tCAH
UCAS, LCAS
Address
Row Address
Col Address
tWCR tCWL tWP tRWL
WE
tOEH
OE
tDHR tOED tDS tDH
I/O
Data In
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AS4C256K16E0
(R)
Upper byte write cycle waveform
tRC tRAS tRP
(OE controlled)
RAS
tRAD tAWR tASR tRAH tRAL
Address
Row Address
tRCD tCRP
Column Address
tCSH tRSH tCAH tASC tCAS tCRP
UCAS
tCRP tRPC tCWL tRWL tWP
LCAS
WE
tOEH
OE
tDS tDH
Upper I/O Lower I/O
Data In
tOED
Lower byte write cycle waveform
tRC tRAS tRP
(OE controlled)
RAS
tRAD tASR tRAH tAWR tRAL
Address
Row Address
tRCD
Column Address
tCAH tCAS tCSH tACS tRSH tRPC tCWL tRWL tWP tCRP
tCRP
LCAS
tCRP
UCAS
WE
tOEH
OE Upper I/O
tDS tDH
Lower I/O
Data In
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AS4C256K16E0
(R)
Read-modify-write cycle waveform
tRWC tRAS tRP tCAS tCRP tRCD tCSH tRSH
RAS
UCAS, LCAS
tRAD tASR tRAH
tAR tRAL tASC tCAH
Address
Row Address
Col Address
tRWD tAWD tRCS tCWD tOEA tOEZ tOED tRWL tCWL tWP
WE OE
tRAC
tAA tCAC tCLZ tDS tDH
I/O
Data Out
Data In
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AS4C256K16E0
(R)
Upper byte read-modify-write cycle waveform
tRWC tRAS tRP
RAS
tCSH tRCD tCRP tCAS tRSH tCRP
UCAS
tCRP tRPC tACS tRAL tCAH
LCAS
tRAD tASR tRAH
Address
Row
Column Address
tRWD tAWD tRCS tCWD tOEA tOED tDS tCWL tRWL tWP
WE OE Upper Input
tCLZ tCAC tAA tRAC
Data In
tOEZ
Upper Output
Data Out
tOED
Lower Input Lower Output
Data Out
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AS4C256K16E0
(R)
Lower byte read-modify-write cycle waveform
tRWC tRAS tRP
RAS
tCRP tRPC tCSH tRCD tCRP tCAS tRSH tCRP
UCAS
LCAS
tRAD tASR tACS tRAH tRAL tCAH
Address
Row
Column Address
tRWD tAWD tRCS tCWD tOEA tCWL tRWL tWP
WE OE Upper Input Upper Output
Data Out
tOED tDS
Lower Input
tRAC tAA tCAC tCLZ
Data In
tOEZ
Lower Output
Data Out
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AS4C256K16E0
(R)
EDO page mode read cycle waveform
tRASP tRP
RAS
tCSH tCRP tRCD tCAS tCP tRSH tPC
UCAS, LCAS
tRAD tASR tRAH
tAR tASC
tCAH tRAL
Address WE
Row
Col Address
tRCS tRCH tOEA
Col Address
tRCS
Col Address
tRCH tOEA tRRH
OE
tRAC tCLZ tCAC tAA tCAC tCAP
I/O
Data Out
Data Out
EDO page mode byte read cycle waveform
tRASP tRP tRSH tCAS tCP tPC tCRP tCAS tRAH tRAD tASC tCAH tASC tCAH tPC tCP tRAL tASC tRPC tCRP
RAS
tCSH tCRP tRCD tCAS
UCAS
LCAS
tASR
tCAH
Address
Row
Column 1
tRCS tRCH tOEA
Column 2
tRCS tOEA tCAC tCLZ tAA tCAP
Column n
tRCS tRCH tOEA
WE OE
tOFF tOEZ
Lower I/O
tAA tRAC tCAC tCLZ tOFF tOEZ
Data Out 2
tAA tCAP tCAC tCLZ
tOFF tOEZ
Upper I/O
Data Out 1 Data Out n
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AS4C256K16E0
(R)
EDO page mode early write cycle waveform
tRASP tRAH tRWL tRCD tCSH tCAS tASC tWCS tCP tRAL tPC tCAH tRSH
RAS
tCRP
UCAS, LCAS
tASR tRAD
tAR
Address
Row address
Col address
Col Address
Col Address
tCWL tWP tWCH tOEH
WE OE
tHDR tDS tDH
I/O
Data In
Data In
Data In
EDO page mode byte early write cycle waveform
tRASP tRP tRSH tCAS tCP tPC tCRP tCAS tRAD tRAH tASR tASC tRAL tCAH tPC tRPC tCP
RAS
tCSH tCRP tRCD tCAS tCRP
UCAS
LCAS
tCAH tASC tCAH tASC
Address
Row
Column 1
Column 2
Column n
tRWL tWCH tWCS tWP tCWL
tWCH tWCS tWP tCWL
tWCH tWCS tWP tCWL
WE OE
tDS tDH
Lower I/O
tDS tDH
Data In 2
tDS tDH
Upper I/O
Data In 1 Data In n
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AS4C256K16E0
(R)
EDO page mode read-modify-write cycle waveform
tRASP tRP
RAS
tPCM tCSH tRCD tCAS tCP tCRP
UCAS, LCAS Address
tASR
tRAD tRAH tCAH tCAH
tRAL tCAH
Row Ad
tRCS
Col Ad
tRWD tCWD tAWD
Col Ad
tCWL tCWD
Col Address
tRWL tCWD tAWD tCWL tWP
WE
tOEA tOEZ tAA tRAC tCLZ tCAC tDS tDH tDS tCLZ tCAC tCAP tCLZ tCAC tOED tOEA
OE
I/O
Data In Data Out
Data In Data Out
Data In Data Out
CAS-before-RAS refresh cycle waveform
tRC tRP tRAS
(WE = VIH )
RAS
tRPC tCPN tCSR tCHR
UCAS, LCAS
tOFF
I/O
RAS only refresh cycle waveform
tRC tRAS tRP tRPC
(WE = OE = VIH or VIL)
RAS
tCRP
UCAS, LCAS Address
tARS
tRAH
Row Address
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AS4C256K16E0
(R)
EDO page mode byte read-modify-write cycle
tRASP tRP
RAS
tCSH tRCD tCRP tCAS tRSH tCAS
tCRP
UCAS
tPCM tCP tCAS tCP
LCAS
tRAD tRAH tASR tASC tCAH tCAH tAWD tASC tRAL tCAH tAWD tASC
Address
tRCS
R
C1
tAWD tCWD tRWD tWP
C2
Cn
tRWL tCWD tCWD tCWL tWP tOEA tOEA tOED tDS tCAP tDH tCWL tWP
tCWL
WE
tOEA
OE
tOED tDH tDS
Upper Input
tRAC tAA tCAC
Data In 1
tOEZ tCLZ tOED
Data In n
tAA tCAC tCLZ tOEZ
Upper Output
Data Out 1
tDH
Data Out n
Lower Input
tDS tAA tOEZ tCAC tCLZ
Data In 2
Lower Output
Data Out 2
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AS4C256K16E0
(R)
Hidden refresh cycle (read) waveform
tRC tRAS tPR tCHR tRCD tRSH tCRP tRAS tRC tPR
RAS
tCRP
CAS
tRAD tRAH tASR tASC tAR
Address
Row
tRCS
Col Address
tRRH tOEA
WE OE
tRAC tAA tCAC tCLZ tOFF tOEZ
I/O
Data Out
Hidden refresh cycle (write) waveform
tRC tRAS tRP
RAS
tCRP tRCD tRSH
UCAS, LCAS
tRAD tRAH tASR tASC tRAL tCAH tAR
Address
Row Address
Col Address
tRWL tWCR tWP
tWCS
tWCH
WE
tDS tDHR tDH
I/O OE
Data In
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AS4C256K16E0
(R)
CAS-before-RAS refresh counter test cycle waveform
tRAS tRSH tRP
RAS
tCSR tCHR tCPT tCAS
UCAS, LCAS
tCAH tRAL
Address
Col Address
tAA tCAC tCLZ tOFF
I/O Read Cycle
tRCS
Data Out
tRRH tRCH tOEA tROH
WE
OE
tRWL tCWL tWP tWCH tWCS
Write Cycle
WE
tDH tDS
I/O OE
Data In
tRCS tCWD tAWD
tWP tCWL
WE Read-Write Cycle
tOEA tOED
OE
t AA tCLZ tCAC tDH tOEZ tDS
I/O
Data Out
Data In
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AS4C256K16E0
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CAS-before-RAS self refresh cycle
tRP tRASS tRPS
RAS
tRPC tCP tCSR tCHS tRPC
UCAS, LCAS
tCEZ
DQ
Typical DC and AC characteristics
1.5 Normalized access time 1.4 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 Supply voltage (V) Typical supply current ICC vs. supply voltage VCC 6.0 Ta = 25C Normalized access time tRAC vs. supply voltage VCC 1.5 Normalized access time 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 125 Ambient temperature (C) Typical supply current ICC vs. ambient temperature Ta Typical access time Normalized access time tRAC vs. ambient temperature Ta 100 90 80 70 60 50 40 30 50 100 150 200 Load capacitance (pF) 250 Typical access time tRAC vs. load capacitance CL
70 60 Supply current (mA) 50 40 30 20 10 0.0 4.0
70 60 50 40 30 20 10
35 30 Power-on current (mA) 25 20 15 10 5 0.0 2
Typical power-on current IPO vs. cycle rate 1/tRC
Supply current (mA) 4.5 5.0 5.5 Supply voltage (V)
6.0
0.0 -55
-10 35 80 125 Ambient temperature (C)
4 6 8 Cycle rate (MHz)
10
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35 30 Refresh current (mA)
Typical refresh current ICC3 vs. supply voltage VCC
Typical refresh current ICC3 vs. Ambient temperature Ta 35 30 25 20 15 10 5 Stand-by current (mA) 20 40 60 80 Ambient temperature (C) Refresh current (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
Typical TTL stand-by current ICC2 vs. supply voltage VCC
25 20 15 10 5 0 4.0 4.5 5.0 5.5 Supply voltage (V) 6.0
0 0.0
4.0
4.5 5.0 5.5 Supply voltage (V)
6.0
Typical TTL stand-by current ICC2 vs. ambient temperature Ta 3.5 Output sink current (mA) 3.0 Stand-by current (mA) 2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 Ambient temperature (C)
70 60 50 40 30 20 10
Typical output sink current IOL vs. output voltage VOL Output source current (mA) 0.5 1.0 1.5 Output voltage (V)
70 60 50 40 30 20 10 0.0
Typical output source current IOH vs. output voltage VOH
0.0 0.0
2.0
0.0
1.0 2.0 3.0 Output voltage (V)
4.0
Typical EDO page mode current ICC4 vs. ambient temperature Ta 35 EDO page mode current (mA) 30 25 20 15 10 5 0.0 0 20 40 60 80 Ambient temperature (C) EDO page mode current (mA)
Typical EDO page mode current ICC4 vs. supply voltage VCC 35 30 25 20 15 10 5 0.0 4.0 4.5 5.0 5.5 Supply voltage (V) 6.0
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Package dimensions
44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23
c A A1 A2 b c d E He e l
44-pin TSOP II
E He
1
2
3
4
5
6
7
8
9 10
13 14 15 16 17 18 19 20 21 22
d l
0-5
A A1 b
e
A2 e
D
44-pin TSOP II Min Max (mm) (mm) 1.2 0.05 0.95 1.05 0.30 0.45 0.127 (typical) 18.28 18.54 10.03 10.29 11.56 11.96 0.80 (typical) 0.40 0.60
40-pin SOJ
E1 E2
Pin 1 B A A1 b A2 E c
Seating Plane
A A1 A2 B b c D E E1 E2 e
40-pin SOJ 400 mil Min Max 0.128 0.148 0.025 1.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.020 1.035 0.370 (typical) 0.390 0.410 0.435 0.445 0.050 (typical)
Capacitance
Parameter Input capacitance I/O capacitance Symbol CIN1 CIN2 CI/O Signals A0 to A8
RAS, UCAS, LCAS, WE, OE
= 1 MHz, Ta = room temperature, VCC = 5V 0.5V Test conditions Vin = 0V Vin = 0V Vin = Vout = 0V Max 5 7 7 Unit pF pF pF
I/O0 to I/O15
Ordering codes
Package \ Access time Plastic SOJ, 400 mil, 40-pin TSOP II, 400 mil, 40/44-pin
Shaded areas contain advance information.
30 ns AS4C256K16E0-30JC
35 ns AS4C256K16E0-35JC
50 ns AS4C256K16E0-50JC AS4C256K16E0-50TC
Part numbering system
AS4C DRAM prefix 256K16E0 Device number -XX
RAS access time
X Package: J = SOJ T = TSOP II
C Commercial temperature range, 0C to 70 C
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(c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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