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MT90869
Flexible 16K Digital Switch (F16kDX) Advance Information
Features
* 16,384-channel x 16,384-channel non-blocking unidirectional switching.The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 64 stream inputs and 64 stream outputs. 8,192-channel x 8,192-channel non-blocking Backplane to Local stream switch. 8,192-channel x 8,192-channel non-blocking Local to Backplane stream switch. 8,192-channel x 8,192-channel non-blocking Backplane input to Backplane output switch. 8,192-channel x 8,192-channel non-blocking Local input to Local output stream switch. Rate conversion on all data paths, Backplane to Local, Local to Backplane, Backplane to Backplane and Local to Local streams. Backplane port accepts 32 ST-BUS streams with data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s in any combination, or a fixed allocation of 16 streams at 32.768Mb/s. Local port accepts 32 ST-BUS streams with data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any combination. Per-stream channel and bit delay for Local input streams. Per-stream channel and bit delay for Backplane input streams. Per-stream advancement for Local output streams. Per-stream advancement for Backplane output streams. Constant throughput delay for frame integrity. Per-channel high impedance output control for Local and Backplane streams. Per-channel driven-high output control for local and backplane streams. High impedance-control outputs for external drivers on backplane and local port. Per-channel message mode for local and backplane output streams. Connection memory block programming for fast device initialization. BER testing for local and backplane ports. Automatic selection between ST-BUS and GCIBUS operation. Non-multiplexed Motorola microprocessor interface.
DS5490 ISSUE 2 December 2001
Ordering Information MT90869AG 272 Ball - PBGA -40 to +85oC * * * * * * Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard. Memory Built-In-Self-Test (BIST), controlled via microprocessor registers or JTAG test port. 1.8V core supply voltage. 3.3V I/O supply voltage. 5V tolerant inputs, outputs and I/Os. Per stream subrate switching at 4 bit, 2 bit and 1 bit depending on stream data rate.
* * * * *
*
Applications
* * * * * * Central Office Switches (Class 5) Mediation Switches Class-independent switches Access Concentrators Scalable TDM-Based Architectures Digital Loop Carriers
*
* * * * * * * * * * * * *
Device Overview
The MT90869 has two data ports, the Backplane and the Local port. The Backplane port has two modes of operation, either 32 input and 32 output streams operated at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any combination, or 16 input and 16 output streams operated at 32.768Mb/s. The Local port has 32 input and 32 output streams operated at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any combination. The MT90869 contains two data memory blocks (Backplane and Local) to provide the following switching path configurations: * Backplane-to-Local, supporting 8K x 8K data switching, * Local-to-Backplane, supporting 8K x 8K data switching, * Backplane-to-Backplane, supporting 8K x 8K data switching. * Local-to-Local, supporting 8K x 8K data switching.
1
MT90869
VDD_IO VDD_CORE VSS (GND) RESET ODE
Advance Information
BSTi0-31
Backplane Data Memories (8,192 channels)
Local Interface
LSTi0-31
Backplane Interface BSTo0-31
Backplane Connection Memory (8,192 locations)
Local Connection Memory (8,192 locations)
Local Interface LSTo0-31
LCST0-3 BCST0-3 BORS Local Data Memories (8,192 channels) Backplane Timing Unit LORS
FP8i
Local Timing Unit
Microprocessor Interface and Internal Registers Test Port
FP8o FP16o C8o C16o
PLL C8i
VDD_PLL DS CS R/W A14-A0 DTA D15-D0 TMS TDI TDO TCK TRST
Figure 1 - MT90869 Functional Block Diagram The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from the connection memory contents (Message Mode). In Connection Mode the contents of the connection memory defines, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per channel basis. This feature is useful for transferring control and status information to external circuits or other ST-BUS devices. The device uses a master frame pulse (FP8i) and master clock (C8i) to define the frame boundary and timing for both the backplane port and the local port. The device will automatically detect whether an STBUS or a GCI-BUS style frame pulse is being used. There is a two frame delay from the time RESET is de-asserted to the establishment of full switch functionality. During this period the frame format is determined before switching begins. The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the local port. Subrate switching is accomplished by oversampling (i.e., 1 bit switching can be accomplished by sampling a 2 Mb/s stream at 16 Mbps). Refer to MSAN 175. A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and switching configurations. The microprocessor port provides access for Register read/write, Connection Memory read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control signals. The microprocessor may monitor channel data in the backplane and local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The MT90869 is manufactured in a 27mm x 27mm body, 1.27mm ball-pitch, 272-PBGA to JEDEC standard MS-034 BAL-2 Iss. A.
2
1 3 4 5 7 VDD_CORE ODE DTA TCK BCSTo1 LCSTO3 LSTo0 LSTo1 A8 A11 A14 DS 8 9 10 11 18 BSTo2 A2 6 14 15 16 17 19 13 12
2
20 A
A BSTo5 BSTo4
GND
IC
LSTo2
IC B
B BSTo8 IC LSTo3 VDD_CORE BSTo1 IC A5 A7 A10 IC CS VDD_CORE TDI TRST BCSTo2 LCSTo2
BSTo6
BSTo7
LSTo4
LSTo5
C IC LCSTo0 BSTo3 BSTo0 A1 A4 A6 IC A13 RW RESET TDO BCSTo0 BCSTo3 LCSTo1 LSTo6 LSTo7 LSTo8
C
BSTo9
BSTo10
D BSTo13 GND A0 VDD_IO A3 GND A9 A12 VDD_IO TMS GND VDD_CORE VDD_IO IC
D GND LSTo9 LSTo10 LSTo11 E BSTo16 BSTo17 LSTo12 LSTo13 LSTo14 LSTo15 F BSTo20 VDD_IO VDD_IO LSTo16 LSTo17 LSTo18 G BSTo23 BSTo24 LSTo19 LSTo20 LSTo21 LSTo22 H BSTo27 GND GND LSTo23 LSTo24 LSTo25 J BSTo30 GND GND GND GND BSTo31 LSTo26 LSTo27 LSTo28 LSTo29 K BSTi0 VDD_IO GND GND GND GND LSTo30 LSTo31 LORS VDD_CORE L GND VDD_IO LSTi0 LSTi1 LSTi2
Advance Information
BSTo11
BSTo12
E
(as viewed through top of package)
BSTi3 GND GND GND BSTi4 M BSTi7 GND GND BSTi8 GND GND LSTi3 LSTi4 LSTi5 LSTi6 N VDD_CORE GND GND LSTi7 LSTi8 LSTi9 P BSTi13 BSTi14 LSTi10 VDD_CORE LSTi11 LSTi12 R BSTi17 VDD_IO VDD_IO LSTi13 LSTi14 LSTi15 T BSTi20 BSTi21 VDD_CORE LSTi16 LSTi17 LSTi18 U IC GND BSTi28 VDD_IO D10 GND D4 VDD_IO GND VDD_PLL GND FP8i VDD_IO VDD_CORE GND LSTi19 LSTi20 LSTi21 V IC BSTi29 VDD_CORE D13 D9 D7 D3 D0 IC IC C8o FP8o IC IC LSTi22 LSTi23 LSTi24 LSTi25 W BSTi25 BSTi30 D15 D12 D8 D6 D2 IC IC C8i C16o FP16o IC IC IC LSTi26 LSTi27 IC Y D14 D11 VDD_CORE D5 D1 IC VDD_CORE NC NC VDD_CORE IC IC LSTi29 LSTi30 LSTi31 LSTi28 IC BSTi31
BSTo14
BSTo15
F
BSTo18
BSTo19
A1 corner identified by metallized marking
G
BSTo21
BSTo22
H
BSTo25
BSTo26
J
BSTo28
BSTo29
K
VDD_CORE
BORS
L
BSTi1
BSTi2
M
BSTi5
BSTi6
N
BSTi9
BSTi10
P
BSTi11
BSTi12
R
BSTi15
BSTi16
T
BSTi18
BSTi19
U
Figure 2 - MT90869 PBGA Connections (272 PBGA) Pin Diagram
BSTi22
IC
V
VDD_CORE
IC
W
BSTi23
BSTi24
MT90869
Y
BSTi26
BSTi27
3
MT90869
Pin Description
Name VDD_IO Package Coordinates D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 A7, B4, B12, D14, K1, K20, N3, P18, T17, U16, V1, V5, Y7, Y11, Y14 U12 A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12, N4, N17, U4, U8, U11, U13, U17 K3, L1, L2, L3, L4, M1, M2, M3, M4, N1, N2, P1, P2, P3, P4, R1 Description
Advance Information
Power Supply for Periphery Circuits: +3.3V
VDD_CORE
Power Supply for Core Logic Circuits: +1.8V
VDD_PLL VSS (GND)
Power Supply for Analogue PLL: +1.8V Ground
BSTi0 - 15
Backplane Serial Input Streams 0 to 15 (5V Tolerant, Internal pulldown). In Non-32Mb/s Mode, these pins accept serial TDM data streams at a data-rate of:16.384 Mb/s (with 256 channels per stream), 8.192 Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048Mb/s (with 32 channels per stream). The data-rate is independently programmable for each input stream. In 32Mb/s Mode, these pins accept serial TDM data streams at a fixed data-rate of 32.768 Mb/s (with 512 channels per stream).
BSTi16 - 31
R2, R3, T1, T2, T3, T4, U1,W1, W2, Y1, Y2, U5, V4, W4, Y4
Backplane Serial Input Streams 16 to 31 (5V Tolerant, Internal pulldown). In Non-32Mb/s Mode, these pins accept serial TDM data streams at a data-rate of:16.384 Mb/s (with 256 channels per stream), 8.192 Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048Mb/s (with 32 channels per stream). The data-rate is independently programmable for each input stream. In 32Mb/s Mode, these pins are unused and should be externally connected to a defined logic level.
4
Advance Information
Pin Description (continued)
Name BSTo0 - 15 Package Coordinates C5, B5, A5 C4, A4, A3, B1, B2, B3, C1, C2, D1, D2, D3, E1, E2 Description
MT90869
Backplane Serial Output Streams 0 to 15 (5V Tolerant, Three-state Outputs). In Non-32Mb/s Mode, these pins output serial TDM data streams at a data-rate of:16.384 Mb/s (with 256 channels per stream), 8.192 Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048Mb/s (with 32 channels per stream). The data-rate is independently programmable for each output stream. In 32Mb/s Mode, these pins output serial TDM data streams at a fixed data-rate of 32.768 Mb/s (with 512 channels per stream). Refer to descriptions of the BORS and ODE pins for control of the output High or High-Impedance state.
BSTo16 - 31
E3, E4, F1, F2, F3, G1, G2, G3, G4, H1, H2, H3, J1, J2, J3, J4
Backplane Serial Output Streams 16 to 31 (5V Tolerant Three-state Outputs). In Non-32Mb/s Mode, these pins output serial TDM data streams at a data-rate of:16.384 Mb/s (with 256 channels per stream), 8.192 Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048Mb/s (with 32 channels per stream). The data-rate is independently programmable for each output stream. These pins are unused when the 32Mb/s Mode is selected. Refer to descriptions of the BORS and ODE pins for control of the output High or High-Impedance state.
BCSTo0-3
C14, A15, B15, C15
Backplane Output Channel High Impedance Control (5V Tolerant Three-state Outputs). Active high output enable which may be used to control external buffering individually for a set of backplane output streams on a per channel basis. In non-32Mb/s mode (stream rates 2Mb/s to 16Mb/s): BCSTo0 is the output enable for BSTo[0,4,8,12,16,20,24,28], BCSTo1 is the output enable for BSTo[1,5,9,13,17,21,25,29], BCSTo2 is the output enable for BSTo[2,6,10,14,18,22,26,30], BCSTo3 is the output enable for BSTo[3,7,11,15,19,23,27,31]. In 32Mb/s mode (stream rate 32Mb/s): BCSTo0 is the output enable for BSTo[0,4,8,12], BCSTo1 is the output enable for BSTo[1,5,9,13], BCSTo2 is the output enable for BSTo[2,6,10,14], BCSTo3 is the output enable for BSTo[3,7,11,15]. Refer to descriptions of the BORS and ODE pins for control of the output High or High-Impedance state.
5
MT90869
Pin Description (continued)
Name FP8i Package Coordinates U14 Description
Advance Information
Frame Pulse Input (5V Tolerant). This pin accepts the Frame Pulse signal. The pulse width may be active for 122ns or 244ns at the frame boundary and the Frame Pulse Width bit (FPW) of the Control Register must be set Low (default) for a 122ns and set High for a the 244ns pulse condition.The device will automatically detect whether an ST-BUS or GCIBUS style frame pulse is applied. Master Clock Input (5V Tolerant). This pin accepts a 8.192MHz clock. The internal Frame Boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit of the control register. Chip Select (5V Tolerant). Active low input used by the microprocessor to enable the microprocessor port access. This input is internally set low during a device RESET. Data Strobe (5V Tolerant). This active low input works in conjunction with CS to enable the microprocessor port read and write operations. Read/Write (5V Tolerant). This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Address 0 - 14 (5V Tolerant). These pins form the 15-bit address bus to the internal memories and registers. A0 = LSB Data Bus 0 - 15 (5V Tolerant). These pins form the 16-bit data bus of the microprocessor port. D0 = LSB Data Transfer Acknowledgment (5V Tolerant). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required to hold a HIGH level. (Max. IOL = 10mA). Test Mode Select (5V Tolerant with internal pull-up). JTAG signal that controls the state transitions of the TAP controller. Test Clock (5V Tolerant). Provides the clock to the JTAG test logic. Test Serial Data In (5V Tolerant with internal pull-up). JTAG serial test instructions and data are shifted in on this pin. Test Serial Data Out (5V Tolerant Three-state Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Test Reset (5V Tolerant with internal pull-up) Asynchronously initializes the JTAG TAP controller to the Test-Logic-Reset state. To be pulsed low during power-up for JTAG testing. This pin must be held LOW for normal functional operation of the device. Device Reset (5V Tolerant with internal pull-up). This input (active LOW) asynchronously applies reset and synchronously releases reset to the device. In the reset state, the outputs LSTo0 - 31 and BSTo0 - 31 are set to a high or high impedance depending on the state of the LORS and BORS external control pins, respectively. It clears the device registers and internal counters. This pin must stay low for more than 2 cycles of input clock C8i for the reset to be invoked.
C8i
W12
CS
B11
DS R/W A0 - A14
A11 C11 D5, C6, A6, D7, C7, B7, C8, B8, A8, D9, B9, A9, D10, C10, A10 V10, Y9, W9, V9, 49, Y8, W8, V8, W7, V7, U7, Y6, W6, V6, Y5, W5 A13
D0 - D15
DTA
TMS TCK TDI TDO
D12 A14 B13 C13
TRST
B14
RESET
C12
6
Advance Information
Pin Description (continued)
Name LSTi0-31 Package Coordinates L18, L19, L20, M17, M18, M19, M20, N18, N19, N20, P17, P19, P20, R18, R19, R20, T18, T19, T20, U18, U19, U20, V17, V18, V19, V20, W18, W19, Y20, Y17, Y18, Y19 W13 Description
MT90869
Local Serial Input Streams 0 to 31 (5V Tolerant with internal pulldown). These pins accept serial TDM data streams at a data-rate of:16.384 Mb/s (with 256 channels per stream), 8.192 Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048Mb/s (with 32 channels per stream). The data-rate is independently programmable for each input stream.
C16o
C16o Output Clock (Three-state Output). A 16.384MHz clock output. The clock falling edge or rising edge is aligned with the local frame boundary, this is controlled by the COPOL bit of the Control Register. C8o Output Clock (Three-state Output). A 8.192MHz clock output. The clock falling edge or rising edge is aligned with the local frame boundary, this is controlled by the COPOL bit of the Control Register. Frame Pulse Output (Three-state Output). Frame pulse output is active for 61ns at the frame boundary. The frame pulse, running at a 8KHz rate, will be the same format (ST-BUS or GCI-BUS) as the input frame pulse (FP8i). Frame Pulse Output (Three-state Output). Frame pulse output is active for 122ns at the frame boundary. The frame pulse, running at 8KHz rate, will be the same style (ST-BUS or GCI-BUS) as the input frame pulse (FP8i). Local Serial Output Streams 0 to 31 (5V Tolerant Three-state Outputs). These pins output serial TDM data streams at a data-rate of:16.384 Mb/s (with 256 channels per stream), 8.192 Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048Mb/s (with 32 channels per stream). The data-rate is independently programmable for each output stream. Refer to descriptions of the LORS and ODE pins for control of the output High or High-Impedance state. Local Output Channel High Impedance Control (5V Tolerant Threestate Outputs). Active high output enable which may be used to control external buffering individually for a set of local output streams on a per channel basis. LCSTo0 is the output enable for LSTo[0,4,8,12,16,20,24,28], LCSTo1 is the output enable for LSTo[1,5,9,13,17,21,25,29], LCSTo2 is the output enable for LSTo[2,6,10,14,18,22,26,30], LCSTo3 is the output enable for LSTo[3,7,11,15,19,23,27,31]. Refer to descriptions of the LORS and ODE pins for control of the output High or High-Impedance state.
C8o
V13
FP16o
W14
FP8o
V14
LSTo0 - 31
A17, A18, A19, B18, B19, B20, C18, C19, C20, D18, D19, D20, E17, E18, E19, E20, F18, F19, F20, G17, G18, G19, G20, H18, H19, H20, J17, J18, J19, J20, K17, K18 C17, C16, B16, A16
LCSTo0-3
7
MT90869
Pin Description (continued)
Name ODE Package Coordinates A12 Description
Advance Information
Output Drive Enable (5V Tolerant, Internal pull-up). An asynchronous input providing Output Enable control to the BSTo0- 31, LSTo0-31, BCSTo0-3 and LCSTo0-3 outputs. When LOW, the BSTo0-31 and LSTo0- 31 outputs are driven high or high impedance (dependent on the BORS and LORS pin settings respectively) and the outputs BCSTo0-3 and LCSTo0-3 are driven low. When HIGH, the outputs BSTo0- 31, LSTo0-31, BCSTo0-3 and LCSTo0-3 are enabled.
BORS
K2
Backplane Output Reset State (5V Tolerant, Internal pull-down). When this input is LOW the device will initialize with the BSTo0-31 outputs driven high, and the BCSTo0-3 outputs driven low. Following initialization, the Backplane stream outputs are always active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by outputs BCSTo0-3. When this input is HIGH, the device will initialize with the BSTo0-31 outputs and the BCSTo0-3 outputs at high impedance. Following initialization, the Backplane stream outputs may be set active or high impedance using the ODE pin or on a per-channel basis with the BE bit in Backplane Connection Memory.
LORS
K19
Local Output Reset State (5V Tolerant, Internal pull-down). When this input is LOW, the device will initialize with the LSTo0-31 outputs driven high and the LCSTo0-3 outputs driven low. Following initialization, the Local stream outputs are always active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by the LCSTo0-3. When this input is HIGH, the device will initialize with the LSTo0-31 outputs and the LCSTo0-3 outputs at high impedance. Following initialization, the Local stream outputs may be set active or high impedance using the ODE pin or on a per-channel basis with the LE bit in Local Connection Memory.
NC IC0
Y12, Y13 A2, A20, B6, B10, B17, C3, C9, D16, U2, U3, V2, V3, V11, V12, V15, V16, W10, W11, W15, W16, W17, W20, Y3, Y10, Y15, Y16
No Connect No connection to be made. Internal Connects These inputs MUST be held LOW.
8
Advance Information
1.0 Bidirectional and Unidirectional Switching Applications
MT90869
The MT90869 has a maximum capacity of 16,384 input channels and 16,384 output channels. This is calculated from the maximum number of streams and channels: 64 input streams (32 backplane, 32 local) at 16.384Mb/s and 64 output streams (32 backplane, 32 local) at 16.384Mb/s. One typical mode of operation is to separate the Backplane and Local sides, as shown in Figure 3 below.
BSTi0-31 32 streams BACKPLANE BSTo0-31 32 streams MT90869
LSTo0-31 32 streams LOCAL LSTi0-31 32 streams
Figure 3 - 8,192 x 8,192 Channels (16Mb/s), Bidirectional Switching In this system setup, the chip has a capacity of 8,192 input channels and 8,192 output channels on the Backplane side as well as 8,192 input channels and 8,192 output channels on the Local side. Note that some or all of the output channels on one side can come from the other side, i.e.: Backplane input to Local output switching. Often a system design does not need to differentiate between a Backplane and Local side, and merely needs maximum switching capacity. In this case, the MT90869 can be used as shown in Figure 4 to give the full 16,384 x 16,384 channel capacity.
BSTi0-31 32 streams INPUT LSTi0-31 32 streams MT90869
BSTo0-31 32 streams OUTPUT LSTo0-31 32 streams
Figure 4 - 16,384 x 16,384 Channels (16Mb/s), Unidirectional Switching In this system, the Backplane and Local inputs and outputs are combined so that the switch appears as a 64 stream input by 64 stream output switch. This style of operation is similar to older switch designs, such as the MT90826. Note, in either configuration the Backplane may be operated in the 32Mb/s Mode, providing 512 channels on each of the 16 available input and output streams (BSTi0-15 and BSTo0-15) operating at a data-rate of 32.768Mb/s, in conjunction with the Local streams (LSTi0-31 and LSTo0-31) operated at 16.384Mb/s. This allows data-rate conversion between 32.768Mb/s and 16.384Mb/s without loss to the switching capacity.
9
MT90869
1.1 Flexible Configuration
Advance Information
The F16KDX can be configured as an 8K by 8K non-blocking bi-directional digital switch, a 16K by 16K unidirectional non-blocking digital switch, and as a blocking switch with various switching capacities. A. Non-Blocking Bi-directional Configuration (Typical System Configuration) * * * * 8,192-channel 8,192-channel 8,192-channel streams 8,192-channel x 8,192-channel non-blocking switching from backplane to local streams x 8,192-channel non-blocking switching from local to backplane streams x 8,192-channel non-blocking switching from backplane input to backplane output x 8,192-channel non-blocking switching from local input to local output streams
B. Unidirectional Configuration Because the input and output drivers are synchronous, the user can combine input backplane streams and input local streams or output backplane streams and output local streams to increase the total number of input and output streams of the switch in a unidirectional configuration. * 16,384-channel x 16,384-channel non-blocking switching from input to output streams
C. Blocking Configuration The F16KDX can be configured as a blocking bi-directional switch if it is an application requirement. For example, it can be configured as a 12k by 4K blocking switch: * * * * 12,288-channel x 4,096-channel blocking switching from backplane to local streams 4,096-channel x 12,288-channel blocking switching from local to backplane streams 12,288-channel x 12,288-channel non-blocking switching from backplane input to backplane output streams 4,096-channel x 4,096-channel non-blocking switching from local input to local output streams
MT90869 BSTi0-31 LSTi0-15 BSTo0-31 LSTo0-31 Total 48 streams input and 48 output 12K by 12K 4K by 12K Total 16 streams input and 16 streams output 12K by 4K 4K by 4K LSTi16-31 LSTo16-31
Figure 5 - 12K by 4K Blocking Configuration
10
Advance Information
2.0
2.1
MT90869
Functional Description
Switching Configuration
The device supports five switching configurations. (1) Backplane-to-Local, (2) Local-to-Backplane, (3) Backplane-to-Backplane, (4) Local-to-Local, and (5) Uni-directional switch. The following sections describe the switching paths in detail. Configurations (1) - (4) enable a non-blocking switch with 8192 input channels and 8192 output channels at Backplane stream data-rates of 16.384Mb/s or 32.768 Mb/s, and Local stream datarates of 16.384Mb/s. The switch paths of Configurations (1) to (4) may be operated simultaneously. 2.1.1 Backplane-to-Local path
The device can provide data switching between the Backplane input port and the Local output port. The Local Connection Memory determines the switching configurations. 2.1.2 Local-to-Backplane path
The device can provide data switching between the Local input port and the Backplane output port. The Backplane Connection Memory determines the switching configurations. 2.1.3 Backplane-to-Backplane path
The device can provide data switching between the Backplane input and output ports. The Backplane Connection Memory determines the switching configurations. 2.1.4 Local-to-Local path
The device can provide data switching between the Local input and output ports. The Local Connection Memory determines the switching configurations. 2.1.5 Uni-directional Switch
The device may be optionally configured to provide a 16,384 x 16,384 uni-directional switch by grouping together all input and all output streams. All streams may be operated at a data-rate of 16.384Mb/s, or a combination of 16.384Mb/s and 32.768 Mb/s. Lower data-rates may be employed with a corresponding reduction in switch capacity. 2.2 Port Data Rate Modes and Selection
The selection of individual stream data-rates is summarized in Table 1. 2.2.1 Local Port Rate Selection The local port has 32 input (LSTi0-31) and 32 output (LSTo0-31) data streams. All input and output streams may be individually selected for operation at a data rate of either 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s. The timing of the input and output clocks and frame pulses are shown in Figure 6, Local Port Timing Diagram for 2,4,8 and 16Mb/s stream rates. 2.2.1.1 Local Input Port
The bit rate for each input stream is selected by writing to a dedicated Local Input Bit Rate Register (LIBRR031). Refer to Table 41, Local Input Bit Rate Register (LIBRRn) Bits.
11
MT90869
Stream Number Input stream - Backplane 0-15 (BSTi0-15) Input stream - Backplane 16-31 (BSTi16-31) Output stream - Backplane 0-15 (BSTo0-15) Output stream - Backplane 16-31 (BSTo16-31) Input stream - Local 0-31 (LSTi0-31) Output stream - Local 0-31 (LSTo0-31)
Advance Information
Rate Selection Capability (for each individual stream) 2.048, 4.096, 8.192 or 16.384Mb/s - Non-32Mb/s Mode 32.768Mb/s - 32Mb/s Mode 2.048, 4.096, 8.192 or 16.384Mb/s - Non-32Mb/s Mode Unused - 32Mb/s Mode 2.048, 4.096, 8.192 or 16.384Mb/s - Non-32Mb/s Mode 32.768Mb/s - 32Mb/s Mode 2.048, 4.096, 8.192 or 16.384Mb/s - Non-32Mb/s Mode Unused - 32Mb/s Mode 2.048, 4.096, 8.192 or 16.384Mb/s 2.048, 4.096, 8.192 or 16.384Mb/s
Table 1 - Per-stream Data-Rate Selection: Backplane and Local, Non-32Mb/s Mode and 32Mb/s Mode
FP8i (ST-BUS) (8kHz)
C8i (ST-BUS)
(8.192MHz)
FP8i (GCI) (8kHz) (8.192MHz)
C8i (GCI)
Channel 0 Channel 255 2 1 0 6 5 4 3 2 1 0 7
LSTi/LSTo0-31 (16Mb/s) ST
1
0
7
6
5
4
3
Channel 0
Channel 255 5 6 7 1 2 3 4 5 6 7 0
LSTi/LSTo0-31 (16Mb/s) GCI LSTi/LSTo0-31 (8Mb/s) ST LSTi/LSTo0-31 (8Mb/s) GCI LSTi/LSTo0-31 (4Mb/s) ST LSTi/LSTo0-31 (4Mb/s) GCI LSTi/LSTo0-31 (2Mb/s) ST LSTi/LSTo0-31 (2Mb/s) GCI
6
7
0
1
2
3
4
Channel 0 0 7 6 Channel 0 7 0 1 Channel 0 0 7 Channel 0 7 0 Channel 0 0 7 Channel 0 7 0 1 6 6 1 2 3 4 5 4 3
Channel 127 2 1 0 7
Channel 127 5 6 7 0
Channel 63 0 Channel 63 7 Channel 31 0 Channel 31 7 0 7 0 7
Figure 6 - Local Port Timing Diagram for 2,4,8 and 16Mb/s stream rates
12
Advance Information
2.2.1.2 Local Output Port
MT90869
The bit rate for each output stream is selected by writing to a dedicated Local Output Bit Rate Register (LOBRR0-31). Refer to Table 43, Local Output Bit Rate Register (LOBRRn) Bits. Operation of stream data in the Connection Mode or the Message Mode is determined by the state of the LMM bit, and the channel High-impedance state controlled by the LE bit of the Local Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection Memory. Refer to Section 6.1, Local Connection Memory, and Section 12.3, Local Connection Memory Bit Definition.
2.2.2
Backplane Port Rate Selection
The Backplane streams may be operated in one of two modes, namely Non-32Mb/s Mode and 32Mb/s Mode. The Local stream data-rates are not affected by the operating mode of the Backplane. The operating mode of the Backplane is determined by setting the Control Register bit, MODE32. Setting the bit HIGH will invoke the 32Mb/s Mode. Setting the bit LOW will invoke the Non-32Mb/s mode. The default bit value on device Reset is LOW. The timing of the input and output clocks and frame pulses are shown in Figure 7, Backplane Port Timing Diagram for 2, 4, 8, 16 and 32Mb/s stream rates. Non-32Mb/s Mode: Each of the 32 Backplane streams (BSTi0-31 and BSTo0-31) and Local streams (LSTi0-31 and LSTo0-31) can be independently programmed for a data-rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s. 32Mb/s Mode: 16 of the Backplane input streams (BSTi0-15) and 16 Backplane output (BSTo0-15) streams operate at a fixed rate of 32.768Mb/s. In this mode, the upper 16 input (BSTi16-31) and 16 output (BSTi16-31) streams are unused. All 32 Local streams can be independently programmed for a data-rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s.
2.2.2.1
Backplane Input Port
The bit rate for each input stream is selected by writing to a dedicated Backplane Input Bit Rate Register (BOBRR0-31). Refer to Table 45, Backplane Input Bit Rate Register (BIBRRn) Bits. If the 32Mb/s mode is selected by writing to the Control Register bit (MODE32), the settings in BIBRRn are ignored. 2.2.2.2 Backplane Output Port
The bit rate for each output stream is selected by writing to a dedicated Backplane Output Bit Rate Register (BOBRR0-31). Refer to Table 47, Backplane Output Bit Rate Register (BOBRRn) Bits. If the 32Mb/s mode is selected by writing to the Control Register bit (MODE32), the settings in BOBRRn are ignored. Operation of stream data in the Connection Mode or the Message Mode is determined by the state of the BMM bit, and the channel High-impedance state controlled by the BE bit of the Backplane Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section 6.2, Backplane Connection Memory and Section 12.4, Backplane Connection Memory Bit Definition.
13
MT90869
FP8i (ST-BUS) (8kHz) C8i (ST-BUS) (8.192MHz) FP8i (GCI) (8kHz) C8i (GCI) (8.192MHz)
Channel 0 Channel 1 Channel 510
Advance Information
Channel 511
BSTi/BSTo0-15 (32Mb/s) ST BSTi/BSTo0-15 (32Mb/s) GCI BSTi/BSTo0-31 (16Mb/s) ST
32107654321076543210
65432107654321076 Channel 510 Channel 511
Channel 0
Channel 1
45670123456701234567
12345670123456701 Channel 255
Channel 0 1 0 7 6 5 4 3 2 1 0 6 5
4
3
2
1
0
7
Channel 0
Channel 255 5 6 7 1 2 3 4 5 6 7 0
BSTi/BSTo0-31 (16Mb/s) GCI BSTi/BSTo0-31 (8Mb/s) ST BSTi/BSTo0-31 (8Mb/s) GCI BSTi/BSTo0-31 (4Mb/s) ST BSTi/BSTo0-31 (4Mb/s) GCI BSTi/BSTo0-31 (2Mb/s) ST BSTi/BSTo0-31 (2Mb/s) GCI
6
7
0
1
2
3
4
Channel 0 0 7 6 Channel 0 7 0 1 Channel 0 0 7 Channel 0 7 0 Channel 0 0 7 Channel 0 7 0 1 6 6 1 2 3 4 5 4 3
Channel 127 2 1 0 7
Channel 127 5 6 7 0
Channel 63 0 Channel 63 7 Channel 31 0 Channel 31 7 0 7 0 7
Figure 7 - Backplane Port Timing Diagram for 2, 4, 8, 16 and 32Mb/s stream rates
14
Advance Information
2.3 Backplane Frame Pulse Input and Master Input Clock Timing
MT90869
The backplane frame pulse (FP8i) is an 8kHz input signal active for 122ns or 244ns at the frame boundary. The FPW bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 16, Control Register Bits, for details. The active state and timing of FP8i may conform either to the ST-BUS or to the GCI-BUS as shown in Figure 6, Local Port Timing Diagram for 2,4,8 and 16Mb/s stream rates, and Figure 7, Backplane Port Timing Diagram for 2, 4, 8, 16 and 32Mb/s stream rates. The MT90869 will automatically detect whether an ST-BUS or a GCIBUS style frame pulse is being used for the master frame pulse (FP8i). The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL. For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS style frame pulse with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated otherwise. In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to the local port. The local frame pulses (FP8o, FP16o) will be provided in the same style as the master frame pulse (FP8i). The polarity of C8o and C16o, at the Frame Boundary, can be controlled by the Control Register bit, COPOL. An analogue phase lock loop (APLL) is used to multiply the external clock frequency to generate an internal clock signal operated at 131.072MHz. The MT90869 requires the cycle to cycle variation of the master clock (C8i) to be less than 1ns to assure proper device operation. 2.4 Backplane Frame Pulse Input and Local Frame Pulse Output Alignment
The MT90869 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being switched. Figure 8, Backplane and Local Frame Pulse Alignment for Data Rates of 2Mb/s, 4Mb/s, 8Mb/s and 16Mb/s, refers. For further details of Frame Pulse conditions and options see Section 13.1, Control Register (CR), Figure 18, Frame Boundary Conditions, ST- BUS Operation, and Figure 19, Frame Boundary Conditions, GCI - BUS Operation.
FP8i C8i BSTi/BSTo0-31 (2Mb/s) BSTi/BSTo0-31 (4Mb/s) BSTi/BSTo0-31 (8Mb/s) BSTi/BSTo0-31 (16Mb/s) FP8o C8o LSTi/LSTo0-31 (2Mb/s) LSTi/LSTo0-31 (4Mb/s) LSTi/LSTo0-31 (8Mb/s) LSTi/LSTo0-31 (16Mb/s)
CH0 CH0 CH0
CH 0 CH 1
CH0 CH0 CH0
CH 0 CH 1
CH1 CH1 CH2 CH4
CH 7 CH 8 CH 9
CH2 CH3 CH4 CH7
CH 13 CH 14 CH 15
CH5 CH9 CH10
CH 20 CH 21
CH1
CH
2
CH2
CH 3 CH 4 CH 5
CH3
CH 6
CH5
CH 10 CH 11
CH6
CH 12
CH8
CH 16 CH 17
CH11
CH 22 CH 23
CH 18
CH 19
CH1 CH1 CH2 CH4
CH 7 CH 8 CH 9
CH2 CH3 CH4 CH7
CH 13 CH 14 CH 15
CH5 CH9
CH 19
CH1
CH 2 CH 3
CH2
CH 4 CH 5
CH3
CH 6
CH5
CH 10 CH 11
CH6
CH 12
CH8
CH 16
CH10
CH 20
CH11
CH 23
CH CH 17 18
CH CH 21 22
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2Mb/s, 4Mb/s, 8Mb/s and 16Mb/s
15
MT90869
3.0
3.1
Advance Information
Input and Output Offset Programming
Input Channel Delay Programming (Backplane and Local Input Streams)
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and Backplane streams. The following sections explain the details of these offset programming features. The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay of zero such that Ch0 is the first channel that appears after the frame boundary. By programming the Backplane or Local input channel delay registers, BCDR0-31 and LCDR0-31, users can assign the Ch0 position to be located at any one of the channel boundaries in a frame. For delays within channel boundaries, the input bit delay programming can be used.
FP8o
C8o
Ch 0 Ch 1 Ch126 Ch127
BSTi0-31/LSTi0-31 Channel Delay = 0 (Default)
32107654321076543210 Channel Delay,1 Ch127
65432107654321076
Ch 0
Ch125
Ch126
BSTi0-31/LSTi0-31 Channel Delay = 1
32107654321076543210
65432107654321076
Ch126
Channel Delay, 2 Ch127
Ch0
Ch125 7654321076
BSTi0-31LSTi0-31 Channel Delay = 2
3210765432107654321076543210
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram The use of Input Channel Delay in combination with Input Bit Delay enables the Ch0 position to be placed anywhere within a frame to a resolution of 1/4 of the bit period. 3.2 Input Bit Delay Programming (Backplane and Local Input Streams)
In addition to the Input Channel Delay programming, the Input Bit Delay programming feature provides users with greater flexibility when designing switch matrices for high speed operation. The input bit delay may be programmed on a per-stream basis to accommodate delays created on PCM highways. For all streams the delay is up to 7 3/4 bits with a resolution of 1/4 bit, for the selected data-rate. See Figure 10 and Figure 11 for Input Bit Delay Timing at 16Mb/s and 8Mb/s data rates, respectively. The local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR31, corresponding to the local data streams, LSTi0 to LSTi31, and the backplane input delay is defined by the Backplane Input Delay registers, BIDR0 to BIDR31, which correspond to the backplane data streams, BSTi0 to BSTi31.
16
Advance Information
MT90869
FP8o C8o
Ch255 Ch0 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5 4
BSTi0-31/LSTi0-31 Bit Delay = 0 (Default) BSTi0-31/LSTi0-31 Bit Delay = 1/4
3
2
Bit Delay, 1/4 Ch255 3 2 1 0 7 6 5 Ch0 4 3 2 1 0 7 6 Ch1 5 4
Bit Delay, 1/2
BSTi0-31/LSTi0-31 Bit Delay = 1/2
Ch255 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 3/4
BSTi0-31/LSTi0-31 Bit Delay = 3/4
Ch255 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 1 Ch255 Ch0 2 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5
BSTi0-31/LSTi0-31 Bit Delay = 1
3
BSTi0-31/LSTi0-31 Bit Delay = 7 1/2
Ch254 2 1 0 7 6 5
Ch127 4 3 2 1 0 7
Bit Delay, 7 1/2 Ch0 6 5 4
BSTi0-31/LSTi0-31 Bit Delay = 7 3/4
Ch254 2 1 0 7 6 5
Ch127 4 3 2 1 0 7
Bit Delay, 7 3/4 Ch0 6 5 4
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16Mb/s
17
MT90869
Advance Information
FP8o C8o
Ch127 Ch0 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5 4
BSTi0-31/LSTi0-31 Bit Delay = 0 (Default) BSTi0-31/LSTi0-31 Bit Delay = 1/4
3
2
Bit Delay, 1/4 Ch127 3 2 1 0 7 6 5 Ch0 4 3 2 1 0 7 6 Ch1 5 4
Bit Delay, 1/2
BSTi0-31/LSTi0-31 Bit Delay = 1/2
Ch127 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 3/4
BSTi0-31/LSTi0-31 Bit Delay = 3/4
Ch127 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 1 Ch127 Ch0 2 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5
BSTi0-31/LSTi0-31 Bit Delay = 1
3
BSTi0-31/LSTi0-31 Bit Delay = 7 1/2
Ch126 2 1 0 7 6 5
Ch127 4 3 2 1 0 7
Bit Delay, 7 1/2 Ch0 6 5 4
BSTi0-31/LSTi0-31 Bit Delay = 7 3/4
Ch126 2 1 0 7 6 5
Ch127 4 3 2 1 0 7
Bit Delay, 7 3/4 Ch0 6 5 4
Figure 11 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 8Mb/s 3.3 Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual local or backplane output streams with respect to the frame boundary. Each output stream has its own advancement value which can be programmed by the output advancement registers. The output advancement selection is useful in compensating for various parasitic loading on the serial data output pins. 3.3.1 Local Output Advancement Programming
The local output advancement registers, LOAR0-31, are used to control the local output advancement. The advancement is determined with reference to the internal system clock rate (131.072MHz). For 2Mb/s, 4Mb/s, 8Mb/s or 16Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to approximately 0ns, -15ns, -30ns or -45ns as shown in Figure 12. 3.3.2 Backplane Output Advancement Programming
The backplane output advancement registers, BOAR0-31 are used to control the backplane output advancement. The advancement is determined with reference to the internal system clock rate (131.072MHz). For 2Mb/s, 4Mb/s, 8Mb/s or 16Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to approximately 0ns, -15ns, -30ns or -45ns as shown in Figure 12. For 32Mb/s streams, the advancement may be 0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7ns, -15ns or -22ns.
18
Advance Information
FP8o
MT90869
System Clock
131.072 Mhz
Ch255 Ch0 Bit 0 Ch255 Bit 7 Bit Advancement, -2 Bit 0 Ch255 Bit 7 Bit Advancement, -4 Ch0 Bit 0 Ch255 Bit 7 Bit Advancement, -6 Bit 0 Bit 7 Bit 6 Bit 6 Ch0 Bit 5 Bit 4 Bit 5 Bit 4 Bit 6 Bit 6 Ch0 Bit 5 Bit 5
BSTo0-31/LSTo0-31 Bit Advancement = 0 (Default) BSTo0-31/LSTo0-31 Bit Advancement = -2
Bit 1
Bit 1
BSTo0-31/LSTo0-31 Bit Advancement = -4
Bit 1
BSTo0-31/LSTo0-31 Bit Advancement = -6
Bit 1
Figure 12 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16Mb/s
19
MT90869
4.0
4.1
Advance Information
Port High Impedance Control
Local Port High Impedance Control
The input pin, LORS, selects whether the Local output streams, LSTo0-31 are set to high impedance at the output of the MT90869 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-3 signals. Setting LORS to a LOW state will configure the output streams, LSTo0-31, to transmit bi-state channel data with per-channel high-impedance determined by external circuits under the control of the LCSTo0-3 outputs. Setting LORS to a HIGH state will configure the output streams, LSTo0-31, of the MT90869 to invoke a high-impedance output on a per-channel basis. The state of the LORS pin is detected and the MT90869 configured accordingly during a RESET operation, e.g. following power-up. The LORS pin is asynchronous and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. 4.1.1 LORS Set LOW
The data (channel control bit) transmitted by LCSTo0-3 replicates the Local Output Enable Bit (LE) of the Local Connection Memory, with a LOW state indicating the channel be set to High Impedance. Section 12.3, Local Connection Memory Bit Definition, refers. The LCSTo0-3 outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the per-channel high impedance state for specific streams. Eight output streams are allocated to each control line as follows:(See also Pin Description)
* * * * LCSTo0 outputs the channel control bits for streams LSTo0, 4, 8, 12, 16, 20, 24 and 28. LCSTo1 outputs the channel control bits for streams LSTo1, 5, 9, 13, 17, 21, 25 and 29. LCSTo2 outputs the channel control bits for streams LSTo2, 6, 10, 14, 18, 22, 26 and 30. LCSTo3 outputs the channel control bits for streams LSTo3, 7, 11, 15, 19, 23, 27 and 31.
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is presented in Table 2, LCSTo Allocation of Channel Control Bits to the Output Streams. As an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to Table 2:(1) The Channel Control Bit corresponding to Stream 0, Channel 0, LSTo0_Ch0, is transmitted on LCSTo0 and is advanced, relative to the Frame Boundary, by 10 periods of C16o. (2) The Channel Control Bit corresponding to Stream 28, Channel 0, LSTo28_Ch0, is transmitted on LCSTo0 in advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bits for LSTo29_Ch0, LSTo30_Ch0 and LSTo31_Ch0 are advanced relative to the Frame Boundary by three periods of C16o, on LCSTo1, LCSTo2 and LCSTo3, respectively.
The LCSTo0-3 outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for the individual output streams, LSTo0-31. Streams at data-rates lower than 16.384Mb/s will have the value of the respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192Mb/s streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel control bit is not repeated for 16.384Mb/s streams. Examples are presented, with reference to Table 2:(3) With stream LSTo4 selected to operate at a data-rate of 2.048Mb/s, the value of the Channel Control Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48. (4) With stream LSTo8 operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus mode) shows the channel control bits for LCSTo0, LCSTo1, LCSTo2 and LCSTo3 in one possible scenario which includes stream LSTo0 at a data-rate of 16.384Mb/s, LSTo1 at 8.192Mb/s, LSTo6 at 4.096Mb/s and LSTo7 at 2.048Mb/s. All remaining streams are operated at a data-rate of 16.384Mb/s.
20
Advance Information
4.1.2 LORS Set HIGH
MT90869
The Local Output Enable Bit (LE) of the Local Connection Memory has direct per-channel control on the highimpedance state of the Local Output streams, LSTo0-31. Programming a LOW state will set the stream output of the MT90869 to High Impedance for the duration of the channel period. See Section 12.3, Local Connection Memory Bit Definition, for programming details. The LCSTo0-3 outputs are held in a high-impedance state.
Allocated Stream No. C16o Period1 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 etc etc 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 4 8 4 8 4 LCSTo0 0 4
3-1 3-3
Channel No. 2 LCSTo3 3 7 11 15 19 23 27 31
3-2
LCSTo1 1 5 9 13 17 21 25 29
3-2
LCSTo2 2 6 10 14 18 22 26 30
3-2
16Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 3 Ch 3 Ch 3 etc etc Ch 254 Ch 254 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1
8Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 etc etc Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0
4Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc etc Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0
2Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc etc Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Frame Boundary
8 12 16 20 24 28
3-2
0
3-3
1 5 9 13 17 21 25 29 1 5 9 13 17 21 25 29 1 5 9 etc etc etc 29 1 5 9 13 17 21 25 29 1 5 9 13 17 21 25 29 1
2 6 10 14 18 22 26 30 2 6 10 14 18 22 26 30 2 6 10 etc etc etc 30 2 6 10 14 18 22 26 30 2 6 10 14 18 22 26 30 2
3 7 11 15 19 23 27 31 3 7 11 15 19 23 27 31 3 7 11 etc etc etc 31 3 7 11 15 19 23 27 31 3 7 11 15 19 23 27 31 3
8 12 16 20 24 28 0
3-3 3-4
12 16 20 24 28 0
3-3 3-4
etc etc etc 28 0 4 8 12 16 20 24 28 0 4 8 12 16 20 24 28 0
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams
21
MT90869
Allocated Stream No. C16o Period1 2048 1 2 3 etc LCSTo0 4 8 12 16 etc LCSTo1 5 9 13 17 etc LCSTo2 6 10 14 18 etc LCSTo3 7 11 15 19 etc 16Mb/s Ch 1 Ch 1 Ch 1 Ch 1 etc Channel No. 2 8Mb/s Ch 0 Ch 0 Ch 0 Ch 0 etc 4Mb/s Ch 0 Ch 0 Ch 0 Ch 0 etc
Advance Information
2Mb/s Ch 0 Ch 0 Ch 0 Ch 0 etc Frame Boundary
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams (continued)
Note 1: Clock Period count is referenced to Frame Boundary. Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream. Note 3-1 to 3-4: See Section 4.1.1 for examples of Channel Control Bit for streams of different data-rates.
FP8o C8o
Channel 0
Channel 255 bits 7-0 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
LSTo0 (16Mb/s)
1
0
7
6
5
LSTo1 (8Mb/s) LSTo6 (4Mb/s) LSTo7 (2Mb/s)
Chan 127 Bit 0
Chan 0 Bit 7
Chan 0 Bit 6
Chan 0 Bit 5
Chan 0 Bit 4
Chan 127 Chan 127 Chan 127 Chan 127 Bit 3 Bit 2 Bit 1 Bit 0
Chan 0 Bit 7
Chan 63 Bit 0 Chan 31 Bit 0
Chan 0 Bit 7
Chan 0 Bit 6
Chan 63 Bit 1
Chan 63 Bit 0
Chan 0 Bit 7 Chan 0 Bit 7
Channel 0 Bit 7
Channel 31 Bit 0
CH 0 LSTo12
CH 0 LSTo16
CH 0 LSTo20
CH 0 LSTo24
CH 0 LSTo28
CH 1 LSTo12
CH 1 LSTo16
CH 1 LSTo20
CH 1 LSTo24
CH 0 LSTo8
CH 1 LSTo0
CH 1 LSTo4
CH 1 LSTo0
CH 1 LSTo4
CH 1 LSTo8
CH 2 LSTo0
CH 1 LST04
CH 0 LSTo13
CH 0 LSTo17
CH 0 LSTo21
CH 0 LSTo25
CH 0 LSTo29
CH 1 LSTo8 CH 1 LSTo10 CH 1 LSTo11 CH 1 LSTo9
LCSTo0
CH 1 LSTo28
CH 1 LSTo13
CH 1 LSTo17
CH 1 LSTo21
CH 1 LSTo25
CH 0 LSTo9
CH 0 LSTo1
CH 0 LSTo1
CH 1 LSTo5
CH 1 LSTo9
CH 1 LSTo1
CH 0 LSTo10
CH 0 LSTo14
CH 0 LSTo18
CH 0 LSTo22
CH 0 LSTo26
CH 0 LSTo30
CH 1 LSTo10
CH 1 LSTo14
CH 1 LSTo18
CH 1 LSTo22
CH 1 LSTo26
CH 1 LSTo30
CH 0 LSTo11
CH 0 LSTo15
CH 0 LSTo19
CH 0 LSTo23
CH 0 LSTo27
CH 0 LSTo31
CH 1 LSTo11
CH 1 LSTo15
CH 1 LSTo19
CH 1 LSTo23
CH 1 LSTo27
CH 1 LSTo31
One C16o period
Figure 13 - Local Port External High Impedance Control Bit Timing (ST-Bus mode)
22
CH 1 LSTo15
CH 0 LSTo 7
CH 1 LSTo3
CH 1 LSTo3
CH 0 LSTo7
CH 1 LSTo3
CH 0 LSTo7
CH 0 LSTo7
LCSTo3
CH 1 LSTo14
CH 1 LSTo2
CH 1 LSTo2
CH 0 LSTo6
CH 1 LSTo2
CH 0 LSTo6
CH 0 LSTo6
LCSTo2
CH 1 LSTo5
CH 1 LSTo5
LCSTo1
CH 1 LSTo29
CH 1 LSTo13
CH 1 LSTo12
Advance Information
4.2 Backplane High Impedance Control
MT90869
The input pin, BORS, selects whether the Backplane output streams, BSTo0-31 are set to high impedance at the output of the MT90869 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the BCSTo0-3 signals. Setting BORS to a LOW state will configure the output streams, BSTo0-31, to transmit bistate channel data with per-channel high-impedance determined by external circuits under the control of the BCSTo0-3 outputs. Setting BORS to a HIGH state will configure the output streams, BSTo0-31, of the MT90869 to invoke a high-impedance output on a per-channel basis. The state of the BORS pin is detected and the MT90869 configured accordingly during a RESET operation, e.g. following power-up. The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. 4.2.1 BORS Set LOW, Non-32Mb/s Mode.
The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the Backplane Connection Memory, with a LOW state indicating the channel be set to High Impedance. Section 12.4, Backplane Connection Memory Bit Definition, refers. The BCSTo0-3 outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the per-channel high impedance state for specific streams. Eight output streams are allocated to each control line as follows:(See also Pin Description) * * * * BCSTo0 outputs the channel control bits for streams BSTo0, 4, 8, 12, 16, 20, 24 and 28. BCSTo1 outputs the channel control bits for streams BSTo1, 5, 9, 13, 17, 21, 25 and 29. BCSTo2 outputs the channel control bits for streams BSTo2, 6, 10, 14, 18, 22, 26 and 30. BCSTo3 outputs the channel control bits for streams BSTo3, 7, 11, 15, 19, 23, 27 and 31.
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is presented in Table 3, BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32Mb/s Mode). As an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to Table 3: (1) The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on BCSTo0 and is advanced, relative to the Frame Boundary, by 10 periods of C16o. (2) The Channel Control Bit corresponding to Stream 28, Channel 0, BSTo28_Ch0, is transmitted on BCSTo0 in advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bits for BSTo29_Ch0, BSTo30_Ch0 and BSTo31_Ch0 are advanced relative to the Frame Boundary by three periods of C16o, on BCSTo1, BCSTo2 and BCSTo3, respectively. The BCSTo0-3 outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for the individual output streams, BSTo0-31. Streams at data-rates lower than 16.384Mb/s will have the value of the respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192Mb/s streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel control bit is not repeated for 16.384Mb/s streams. Examples are presented, with reference to Table 3: (3) With stream BSTo4 selected to operate at a data-rate of 2.048Mb/s, the value of the Channel Control Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48. (4) With stream BSTo8 operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
23
MT90869
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Allocated Stream No. C16o Period1 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 etc etc 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 etc 4 8 4 8 4 BCSTo0 0 4
3-1 3-3
Advance Information
Channel No. 2 BCSTo3 3 7 11 15 19 23 27 31
3-2
BCSTo1 1 5 9 13 17 21 25 29
3-2
BCSTo2 2 6 10 14 18 22 26 30
3-2
16Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 2 Ch 3 Ch 3 Ch 3 etc etc Ch 254 Ch 254 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 255 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 etc
8Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 Ch 1 etc etc Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 127 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc
4Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc etc Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 63 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc
2Mb/s Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc etc Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 31 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 Ch 0 etc Frame Boundary Frame Boundary
8 12 16 20 24 28
3-2
0
3-3
1 5 9 13 17 21 25 29 1 5 9 13 17 21 25 29 1 5 9 etc etc etc 29 1 5 9 13 17 21 25 29 1 5 9 13 17 21 25 29 1 5 9 13 17 etc
2 6 10 14 18 22 26 30 2 6 10 14 18 22 26 30 2 6 10 etc etc etc 30 2 6 10 14 18 22 26 30 2 6 10 14 18 22 26 30 2 6 10 14 18 etc
3 7 11 15 19 23 27 31 3 7 11 15 19 23 27 31 3 7 11 etc etc etc 31 3 7 11 15 19 23 27 31 3 7 11 15 19 23 27 31 3 7 11 15 19 etc
8 12 16 20 24 28 0
3-3 3-4
12 16 20 24 28 0
3-3 3-4
etc etc etc 28 0 4 8 12 16 20 24 28 0 4 8 12 16 20 24 28 0 4 8 12 16 etc
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32Mb/s Mode)
Note 1: Clock Period count is referenced to Frame Boundary. Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream. Note 3-1 to 3-4: See Section 4.2.1 for examples of Channel Control Bit for streams of different data-rates.
24
Advance Information
MT90869
FP8o C8o
Channel 0
Channel 255 bits 7-0 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
BSTo0 (16Mb/s)
1
0
7
6
5
BSTo1 (8Mb/s) BSTo6 (4Mb/s) BSTo7 (2Mb/s)
Chan 127 Bit 0
Chan 0 Bit 7
Chan 0 Bit 6
Chan 0 Bit 5
Chan 0 Bit 4
Chan 127 Chan 127 Chan 127 Chan 127 Bit 3 Bit 2 Bit 1 Bit 0
Chan 0 Bit 7
Chan 63 Bit 0 Chan 31 Bit 0
Chan 0 Bit 7
Chan 0 Bit 6
Chan 63 Bit 1
Chan 63 Bit 0
Chan 0 Bit 7 Chan 0 Bit 7
Channel 0 Bit 7
Channel 31 Bit 0
CH 0 BSTo12
CH 0 BSTo16
CH 0 BSTo20
CH 0 BSTo24
CH 0 BSTo28
CH 1 BSTo12
CH 1 BSTo16
CH 1 BSTo20
CH 1 BSTo24
CH 0 BSTo8
CH 1 BSTo0
CH 1 BSTo4
CH 1 BSTo0
CH 1 BSTo4
CH 1 BSTo8
CH 2 BSTo0
CH 1 BST04
CH 0 BSTo13
CH 0 BSTo17
CH 0 BSTo21
CH 0 BSTo25
CH 0 BSTo29
CH 1 BSTo8 CH 1 BSTo10 CH 1 BSTo11 CH 1 BSTo9
BCSTo0
CH 1 BSTo28
CH 1 BSTo13
CH 1 BSTo17
CH 1 BSTo21
CH 1 BSTo25
CH 0 BSTo9
CH 0 BSTo1
CH 0 BSTo1
CH 1 BSTo5
CH 1 BSTo9
CH 1 BSTo1
CH 0 BSTo10
CH 0 BSTo14
CH 0 BSTo18
CH 0 BSTo22
CH 0 BSTo26
CH 0 BSTo30
CH 1 BSTo10
CH 1 BSTo14
CH 1 BSTo18
CH 1 BSTo22
CH 1 BSTo26
CH 1 BSTo30
CH 0 BSTo11
CH 0 BSTo15
CH 0 BSTo19
CH 0 BSTo23
CH 0 BSTo27
CH 0 BSTo31
CH 1 BSTo11
CH 1 BSTo15
CH 1 BSTo19
CH 1 BSTo23
CH 1 BSTo27
CH 1 BSTo31
One C16o period
Figure 14 - Backplane Port External High Impedance Control Bit Timing (Non-32Mb/s mode)
Figure 14, Backplane Port External High Impedance Control Bit Timing (Non-32Mb/s mode) shows the channel control bits for BCSTo0, BCSTo1, BCSTo2 and BCSTo3 in one possible scenario which includes stream BSTo0 at a data-rate of 16.384Mb/s, BSTo1 at 8.192Mb/s, BSTo6 at 4.096Mb/s and BSTo7 at 2.048Mb/s. All remaining streams are operated at a data-rate of 16.384Mb/s.
CH 1 BSTo15
CH 0 BSTo 7
CH 1 BSTo3
CH 1 BSTo3
CH 0 BSTo7
CH 1 BSTo3
CH 0 BSTo7
CH 0 BSTo7
BCSTo3
CH 1 BSTo14
CH 1 BSTo2
CH 1 BSTo2
CH 1 BSTo0
CH 1 BSTo2
CH 0 BSTo6
CH 0 BSTo6
BCSTo2
CH 1 BSTo5
CH 1 BSTo5
BCSTo1
CH 1 BSTo29
CH 1 BSTo13
CH 1 BSTo12
25
MT90869
4.2.2 BORS Set LOW, 32Mb/s Mode.
Advance Information
The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the Backplane Connection Memory, with a LOW state indicating the channel be set to High Impedance. Section 12.4, Backplane Connection Memory Bit Definition, refers. The BCSTo0-3 outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the per-channel high impedance state for specific streams. Four output streams are allocated to each control line as follows:(See also Pin Description) * * * * BCSTo0 outputs the channel control bits for streams BSTo0, 4, 8, and 12. BCSTo1 outputs the channel control bits for streams BSTo1, 5, 9, and 13. BCSTo2 outputs the channel control bits for streams BSTo2, 6, 10, and 14. BCSTo3 outputs the channel control bits for streams BSTo3, 7, 11, and 15.
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is presented in Table 4, BCSTo Allocation of Channel Control Bits to the Output Streams (32Mb/s Mode). The BCSTo0-3 outputs data at a constant data-rate of 16.384Mb/s and all output streams, BSTo0-15, operate at a data-rate of 32.768Mb/s. As an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to Table 4:(1) The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on BCSTo0 and is advanced, relative to the Frame Boundary, by six periods (clock period no. 2043) of C16o. (2) The Channel Control Bit corresponding to Stream 12, Channel 0, BSTo12_Ch0, is transmitted on BCSTo0 in advance of the Frame Boundary by three periods (clock period no. 2046) of output clock, C16o. Similarly, the Channel Control Bits for BSTo13_Ch0, BSTo14_Ch0 and BSTo15_Ch0 are advanced relative to the Frame Boundary by three periods of C16o, on BCSTo1, BCSTo2 and BCSTo3, respectively. (3) For stream BSTo4 the value of the Channel Control Bit for Channel 510 will be transmitted during the C16o clock period no. 2036 on BCSTo0. (4) For stream BSTo5 the value of the Channel Control Bit for Channel 4 will be transmitted during the C16o clock period no. 12 on BCSTo1.
26
Advance Information
MT90869
Allocated Stream No. Channel No. 2 BCSTo3 3 7 11 15 3 7 11 15
3-2
Figure 15, Backplane Port External High Impedance Control Timing (32Mb/s Mode) shows the channel control bits for BCSTo0, BCSTo1, BCSTo2 and BCSTo3.
C16o Period1 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 etc etc 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 1 2 3 etc
BCSTo0 0 4 8 12 0
3-1
BCSTo1 1 5 9 13 1 5 9 13
3-2
BCSTo2 2 6 10 14 2 6 10 14
3-2
32Mb/s Ch 511 Ch 511 Ch 511 Ch 511 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 2 Ch 2 Ch 2 Ch 2 Ch 3 Ch 3 Ch 3 Ch 3 Ch 4 Ch 4 Ch 4 Ch 4 Ch 5 Ch 5 Ch 5 etc etc Ch 508 Ch 508 Ch 509 Ch 509 Ch 509 Ch 509 Ch 510 Ch 510 Ch 510 Ch 510 Ch 511 Ch 511 Ch 511 Ch 511 Ch 0 Ch 0 Ch 0 Ch 0 Ch 1 Ch 1 Ch 1 Ch 1 Ch 2 etc Frame Boundary Frame Boundary
4 8 12
3-2
0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 etc etc etc 12 0 4 8 12 0 4 3-3 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 etc 5
1 5 9 13 1 5 9 13 1 5 9 13 1
3-4
2 6 10 14 2 6 10 14 2 6 10 14 2 6 10 14 2 6 10 etc etc etc 14 2 6 10 14 2 6 10 14 2 6 10 14 2 6 10 14 2 6 10 14 2 etc
3 7 11 15 3 7 11 15 3 7 11 15 3 7 11 15 3 7 11 etc etc etc 15 3 7 11 15 3 7 11 15 3 7 11 15 3 7 11 15 3 7 11 15 3 etc
9 13 1 5 9 etc etc etc 13 1 5 9 13 1 5 9 13 1 5 9 13 1 5 9 13 1 5 9 13 1 etc
Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32Mb/s Mode).
Note 1: Clock Period count is referenced to Frame Boundary. Note 2: The Channel Numbers presented relate to the specific stream operating at a data-rate of 32.768Mb/s. Note 3-1 to 3-4: See Section 4.2.2 for examples of Channel Control Bits. 27
MT90869
FP8o
Advance Information
C8o
BSTo0 (32Mb/s) BSTo1 (32Mb/s) BSTo2 (32Mb/s) BSTo3 (32Mb/s)
Channel 0 bits 7-0 Channel 0 bits 7-0
Channel 1 bits 7-0 Channel 1 bits 7-0
Channel 510 bits 7-0 Channel 510 bits 7-0
Channel 511 bits 7-0 Channel 511 bits 7-0
Channel 0 bits 7-0 Channel 0 bits 7-0
Channel 1 bits 7-0 Channel 1 bits 7-0
Channel 510 bits 7-0 Channel 510 bits 7-0
Channel 511 bits 7-0 Channel 511 bits 7-0
CH 511 BSTo12
CH 0 BSTo12
CH 1 BSTo12
CH 2 BSTo12
CH 511 BSTo13
CH 0 BSTo13
CH 1 BSTo13
CH 2 BSTo13
CH 511 BSTo10
CH 511 BSTo14
CH 0 BSTo10
CH 0 BSTo14
CH 1 BSTo10 CH 1 BSTo11
CH 1 BSTo10
CH 1 BSTo14
CH 2 BSTo10
CH 2 BSTo14
BCSTo3
CH 511 BSTo11 CH 511 BSTo15 CH 0 BSTo11 CH 0 BSTo15 CH 1 BSTo11 CH 1 BSTo15 CH 2 BSTo11 CH 2 BSTo15 CH 1 BSTo15 CH 0 BSTo3 CH 0 BSTo7 CH 1 BSTo3 CH 1 BSTo3 CH 1 BSTo7 CH 2 BSTo3 CH 2 BSTo7 CH 3 BSTo3 CH 3 BSTo7 CH 1 BSTo7
One C16o cycle
Figure 15 - Backplane Port External High Impedance Control Timing (32Mb/s Mode) 4.2.3 BORS Set HIGH
The Backplane Output Enable Bit (BE) of the Backplane Connection Memory has direct per-channel control on the high-impedance state of the Backplane Output streams, BSTo0-31 (for Non-32MB/s Mode) and BSTo0-15 (for 32Mb/s Mode). Programming a LOW state will set the stream output of the MT90869 to High Impedance for the duration of the channel period. See Section 12.4, Backplane Connection Memory Bit Definition, for programming details. The BCSTo0-3 outputs are held in a high-impedance state.
28
CH 1 BSTo14
BCSTo2
CH 1 BSTo2 CH 1 BSTo6
CH 0 BSTo2
CH 0 BSTo6
CH 1 BSTo2
CH 2 BSTo2
CH 2 BSTo6
CH 3 BSTo2
CH 3 BSTo6
CH 1 BSTo6
CH 1 BSTo13
CH 511 BSTo9
CH 0 BSTo1
CH 0 BSTo5
CH 0 BSTo9
CH 1 BSTo1
CH 1 BSTo5
CH 1 BSTo1
CH 1 BSTo5
CH 1 BSTo9
CH 2 BSTo1
CH 2 BSTo5
CH 1 BSTo9
CH 3 BSTo1
CH 3 BSTo5
CH 1 BSTo9
BCSTo1
CH 1 BSTo12
CH 511 BSTo8
CH 0 BSTo0
CH 0 BSTo4
CH 0 BSTo8
CH 1 BSTo0
CH 1 BSTo4
CH 1 BSTo0
CH 1 BSTo4
CH 1 BSTo8
CH 2 BSTo0
CH 2 BSTo4
CH 2 BSTo8
CH 3 BSTo0
CH 3 BSTo4
CH 1 BSTo8
BCSTo0
Advance Information
5.0 Data delay through the switching paths
MT90869
For all data rates, the received serial data is converted to parallel format and stored sequentially in the data memory. Each data memory location corresponds to an input stream and channel number. To provide constant delay and maintain frame integrity, the MT90869 utilizes four pages of data memory. Consecutive frames are written in turn to each page of memory. Reading is controlled to allow a channel data written in frame N to be read during frame N+3. A constant delay of three frames is applied to all switching paths irrespective of data-rate or channel number. See Figure 16, Constant Switch Delay: Examples of different stream rates and routing.
FP8o
Frame N Frames N+1 and N+2 Frame N+3 Frame N+4
Example showing Backplane to Backplane switching
BSTi0 CH CH CH (16Mb/s) 254 255 0 BSTo1 CH CH CH (16Mb/s) 254 255 0
CH 1 CH CH 254 255 CH 0 CH 1 CH CH 254 255 CH 0 CH 1
CH 1
CH CH 254 255
CH 0
CH 1
CH CH 254 255
CH 0
CH 1
Example showing backplane to local switching
BSTi0 (8Mb/s) LSTo1 (8Mb/s)
CH 127 CH 0 CH 127 CH 0 CH 127 CH 0
CH 127
CH 0
CH 127
CH 0
CH 127
CH 0
Example showing Local to Backplane switching
LSTi0 (8Mb/s) BSTo1 (4Mb/s)
CH 127 CH 0 CH 127 CH 0 CH 127 CH 0
CH 63
CH 0
CH 63
CH 0
CH 63
CH 0
Example showing Local to Local switching
LSTi0 (8Mb/s) LSTo1 (2Mb/s)
CH 127 CH 0 CH 127 CH 0 CH 127 CH 0
CH 31
CH 0
CH 31
CH 0
CH 31
CH 0
Example showing 32Mb/s mode, Backplane to Local switching
0 BSTi0 C C C C C C C C (32Mb/s) H H H H H H H H LSTo1 CH CH CH (16Mb/s) 254 255 0
CH 1
511
CCCC HHHH CCCC HHHH CCCCCCCC HHHHHHHH
CH CH 254 255
CH 0
CH 1
CH CH 254 255
CH 0
CH 1
Figure 16 - Constant Switch Delay: Examples of different stream rates and routing
29
MT90869
6.0 Connection Memory Description
Advance Information
The MT90869 incorporates two connection memories, Local Connection Memory and Backplane Connection Memory. 6.1 Local Connection Memory
The Local Connection Memory (LCM) is 16-bit wide with 8,192 memory locations to support the Local output port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane or the Local port and determines the Backplane-to-Local or Local-to-Local data routing. Bits [14:13] select the control modes of the Local output streams, namely the per-channel message and the per-channel high impedance output control modes. In Connection Mode (Bit14 = LOW), Bits [12:0] select the source stream and channel number as detailed in Table 5. In Message Mode (Bit14 = HIGH), Bits [12:8] are unused and Bits [7:0] contain the message byte to be transmitted. The Control Register bits MS2, MS1, and MS0 must be set to 000, respectively, to select the Local Connection Memory for the Write and Read operations via the microprocessor port. See Section 7, Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access.
Source Stream Bit Rate 2Mb/s 4Mb/s 8Mb/s 16Mb/s 32Mb/s (Backplane streams only)
Source Stream No. [12:8] legal values 0:31 [12:8] legal values 0:31 [12:8] legal values 0:31 [12:8] legal values 0:31 [12:9] legal values 0:15
Source Channel No. [7:0] legal values 0:31 [7:0] legal values 0:63 [7:0] legal values 0:127 [7:0] legal values 0:255 [8:0] legal values 0:511
Table 5 - Local and Backplane Connection Memory Configuration 6.2 Backplane Connection Memory
The Backplane Connection Memory (BCM) is 16-bit wide with 8,192 memory locations to support the Backplane output port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane or the Local port and determines the Local-to-Backplane or Backplane-to-Backplane data routing. Bits [14:13] select the control modes of the Backplane output streams, namely the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode (Bit14 = LOW), Bits [12:0] select the source stream and channel number as detailed in Table 5. In Message Mode (Bit14 = HIGH), Bits [12:8] are unused and Bits [7:0] contain the message byte to be transmitted. The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane Connection Memory for the Write and Read operations via the microprocessor port. See Section 7, Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access.
30
Advance Information
6.3 Connection Memory Block Programming
MT90869
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register (BPR) will be loaded into the connection memories. See Table 16 and Table 17 for details of the Control Register and Block Programming Register values, respectively. 6.3.1 * * Memory Block Programming Procedure
Set the MBP bit in the Control Register from LOW to HIGH. Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits, LBPD2-0, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively. of the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 6. 15 LBPD2 14 LBPD1 13 LBPD0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 6 - Local Connection Memory in Block Programming Mode The Backplane Block Programming data bits, BBPD2-0, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 7. 15 BBPD2 14 BBPD1 13 BBPD0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 7 - Backplane Connection Memory in Block Programming Mode The Block Programming Register bit, BPE will be automatically reset LOW within 125us, to indicate completion of memory programming. The Block Programming Mode can be terminated at any time prior to completion by setting the BPE bit of the Block Programming Register or the MBP bit of the Control Register to LOW. Note the default values (LOW) of LBPD2-0 and BBPD2-0 of the Block Programming Register, following a device reset, may be used. These settings shall set all output channels to High, or High-Impedance, in accordance with the LORS and BORS pin conditions, see Pin Description for further details. The Local Connection Memory shall be configured to select data from Channel 0 of Backplane input Stream 0 (BSTi0), and the Backplane Connection Memory shall be configured to select data from Channel 0 of Local input Stream 0 (LSTi0). Alternative conditions may be established by programming bits LBPD2-0 and BBPD2-0 of the Block Programming Register at the time of setting Bit BPE to HIGH. See Section 12.3, Local Connection Memory Bit Definition, Section 12.4, Backplane Connection Memory Bit Definition, and Section 13.2, Block Programming Register (BPR).
31
MT90869
7.0 Microprocessor Port
Advance Information
The MT90869 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit parallel data bus (D0-15), 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local Connection and Data memories. Each memory has 8,192 locations. See Table 8, Address Map for Data and Connection Memory Locations (A14=1), for the address mapping. Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only be read (but not written) from the microprocessor port. To prevent the bus 'hanging', in the event of the MT90869 not receiving a master clock, the microprocessor port shall complete the DTA handshake when accessed but any data read from the bus will be invalid.
8.0
8.1
Device Power-up, Initialization and Reset
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3V)to be established before the power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8V). The VDD_PLL and VDD_CORE supplies may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3V. All supplies may be powered-down simultaneously. 8.2 Initialization
Upon power up, the MT90869 should be initialized by applying the following sequence: 1 2 Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller. Set ODE pin to LOW. This configures the LCSTo0-3 output signals to LOW (i.e. to set optional external output buffers to high impedance), and sets the LSTo0-31 outputs to high or high impedance, dependent on the LORS input value, and sets the BCSTo0-3 output signals to LOW (i.e. to set optional external output buffers to high impedance), and sets the BSTo0-31 outputs to high or high impedance, dependent on BORS input value. Refer to Pin Description for details of the LORS and BORS pins. Reset the device by pulsing the RESET pin to zero for at least two cycles of the input clock, C8i. Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer to Section 6.3, Connection Memory Block Programming. Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will not occur at the serial stream outputs.
3 4 5
8.3
Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90869. It is synchronized to the internal clock and remains active for 50us following release (set HIGH) of the external RESET to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins LORS and BORS, the output streams LSTo0- 31 and BSTo0-31 are set to high or high impedance, and all internal registers and counters are reset to the default state. The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release.
32
Advance Information
MT90869
When a RESET is applied to the MT90869, the CS line is inhibited and the DTA line may become active through simultaneous microport activity. External gating of the DTA line with CS is recommended to avoid bus conflict in applications incorporating multiple devices with individual reset conditions.
9.0
Bit Error Rate Test
Independent Bit Error Rate (BER) test mechanisms are provided for the Local and Backplane ports. In both ports there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to allow either looped back, or uni-directional testing. The transmitter generates a 215-1 or 223-1 Pseudo Random Binary Sequence (PRBS), which may be allocated to a specific stream and a number of channels. This is defined by a stream number, a start channel number, and the number of consecutive channels following the start channel. The stream, channel number and the number of consecutive channels following the start channel are similarly allocated for the receiver and detection of the PRBS. Examples of a channel sequence are presented in Figure 17. When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved, by detection of a seed value, a bit by bit comparison takes place and each error shall increment a 16-bit counter. A counter 'roll-over' shall occur in the event of an error count in excess of 65535. The BER operations are controlled by registers as follows (refer to Section 13.3, Bit Error Rate Test Control Register (BERCR) for overall control, Section 13.10, Local Bit Error Rate (BER) Registers and Section 13.11, Backplane Bit Error Rate (BER) Registers for register programming details): * * * * * * BER Control Register (BERCR) - Independently enables BER transmission and receive testing for backplane and local ports. Local and Backplane BER Start Send Registers (LBSSR and BBSSR) - Defines the output stream and start channel for BER transmission. Local and Backplane Transmit BER Length Registers (LTXBLR and BTXBLR) - Defines, for transmit stream, how many consecutive channels to follow the start channel. Local and Backplane BER Start Receive Registers (LBSR and BBSR) - Define the input stream and channel from where the BER sequence will start to be compared. Local and Backplane Receive BER Length Registers (LRXBLR and BRXBLR) - Defines, for the receive stream, how many consecutive channels follow the start channel. Local and Backplane BER Count Registers (LBCR and BBCR) - Contain the number of counted errors.
The registers listed completely define the transmit stream and channels. When BER transmission is enabled for these channels, the source bits and the message mode bits, LSRC and LMM in the Local Connection Memory, and BSRC and BMM in the Backplane Connection Memory, are ignored. The enable bits (LE and BE) of the respective connection memories should be set to HIGH to enable the outputs for the selected channels.
33
MT90869
frame boundary FP8i 0 1 2 3 ...... ..... ..... ..... 254 255 0
Advance Information
Start Ch=0 Length=256
1
2
Start Ch=0 Length=3
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Start Ch=254 Length=4
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Channels containing PRBS sequence
Channels containing data (traffic)
Note: Length = Start Chan. + No. of Consecutive channels Once Started BER transmission continues until stopped by the BER control register:FP stream
Figure 17 - Examples of BER transmission channels
10.0
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is placed "out-of-service" or isolated from live traffic. The memory BIST mode is enabled either through the dedicated JTAG TAP controller port (Section 11, JTAG Port) or the microprocessor port (Section 13.14, Memory BIST Register). Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the JTAG TDO pin or the Memory BIST Register when controlled via the microprocessor interface.
11.0
JTAG Port
The MT90869 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. 11.1 Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows: * Test Clock Input (TCK) TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in Boundary-Scan Mode. Test Mode Select Input (TMS) The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V DD_IO when not driven from an external source.
*
34
Advance Information
*
MT90869
Test Data Input (TDI) Depending on the previously applied data to the TMS input, the serial input data applied to the TDI port is connected either to the Instruction Register or to a Test Data Register. Both registers are described in a Section 11.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to V DD_IO when not driven from an external source. Test Data Output (TDO) Depending on the previously applied sequence to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO output is set to a high impedance state. Test Reset (TRST) TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled to V DD_IO when not driven from an external source. TAP Registers
*
*
11.2
The MT90869 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an Instruction Register and three Test Data Registers.
35
MT90869
11.2.1 Test Instruction Register
Advance Information
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction Register from the TDI pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to define the serial Test Data Register path to shift data between TDI and TDO during data register scanning. 11.2.2 Test Data Registers
11.2.2.1 The Boundary-Scan Register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT90869 core logic. 11.2.2.2 The Bypass Register The Bypass register is a single stage shift register to provide a one-bit path from TDI to TDO. 11.2.2.3 The Device Identification Register
The JTAG device ID for the MT90869 is 0086915BH. Version, Bits <31:28>: 0000 Part No., Bits <27:12>: 0000 1000 0110 1001 Manufacturer ID, Bits <11:1>: 0001 0100 101 Header, Bit <0> (LSB): 1 11.3 Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface.
36
Advance Information
12.0 Memory Address Mappings
Description Selects memory or register access Stream address (0-31) Channel address (0-511)
MT90869
Address Bit A14 A13-A9 A8-A0
Notes: 1. Bit A14 must be high for accessing to data and connection memory positions. Bit A14 must be low for accessing registers. 2. Streams 0 to 15 are used when the backplane serial streams are at 32.768Mb/s. 3. Channels 0 to 31 are used when serial stream is at 2.048Mb/s. 4. Channels 0 to 63 are used when serial stream is at 4.096Mb/s. 5. Channels 0 to 127 are used when serial stream is at 8.192Mb/s. 6. Channels 0 to 255 are used when serial stream is at 16.384Mb/s. 7. Channels 0 to 511 are used when serial stream is at 32.768Mb/s. Table 8 - Address Map for Data and Connection Memory Locations (A14=1) The device contains two data memory blocks, one for received backplane data and one for received local data. For all data rates the received data is converted to parallel format by internal serial to parallel converters and stored sequentially in the relevant data memory. 12.1 Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 8,192 positions. The locations are associated with the backplane input streams and channels. The address bits (A13:0) of the microprocessor define the addresses of the streams and the channels. The BDM is configured as follows: Bit 15-8 7-0 Name Reserved BDM Set to a default value of 0 Backplane Data Memory Backplane Input Channel Data Table 9 - Backplane Data Memory (BDM) Bits 12.2 Local Data Memory Bit Definition Description
The 8-bit Local Data Memory (LDM) has 8,192 positions. The locations are associated with the local input streams and channels. The address bits of the microprocessor define the addresses of the streams and the channels. The LDM is configured as follows: Bit 15-8 7-0 Name Reserved LDM Set to a default value of 0 Local Data Memory Local Input Channel Data Table 10 - Local Data Memory (LDM) Bits Description
37
MT90869
12.3 Local Connection Memory Bit Definition
Advance Information
The Local Connection Memory (LCM) has 8,192 addresses of 16-bit words. Each address, accessed through bits A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition for each 16-bit word is presented in Table 11 for Local-to-Local and Backplane (Non-32MB/s Mode)to-Local connections, and in Table 12, for Local-to-Local and Backplane(32Mb/s Mode)-to-Local connections. Bit LSRC selects the switch configuration for Backplane-to-Local or Local-to-Local. When the per-channel Message Mode is selected (LMM = HIGH), the lower byte of the LCM word (LCAB7-0) will be transmitted as data on the output stream (LSTo0-31) in place of data defined by the Source Control, Stream and Channel Address bits.
.
Bit 15
Name LSRC
Description Source Control Bit When LOW, the source is from the Backplane input port (Backplane Data Memory). When HIGH, the source is from the Local input port (Local Data Memory). Ignored when LMM is set HIGH. Local Message Mode Bit When LOW, the channel is in Connection Mode. When HIGH, the channel is in Message Mode. Local Output Enable Bit When LOW the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the LORS pin. When HIGH the channel is active. Source Stream Address Bits The binary value of these 5 bits represents the input stream number. Ignored when LMM is set HIGH. Source Channel Address Bits The binary value of these 8 bits represents the input channel number when LMM is set LOW. Transmitted as data when LMM is set HIGH.
14
LMM
13
LE
12-8
LSAB4-0
7-0
LCAB7-0
Table 11 - LCM Bits for Local-to-Local and Backplane (Non-32Mb/s Mode)-to-Local Switching Bit 15 Name LSRC Description Source Control Bit. When LOW, the source is from the Backplane input port (Backplane Data Memory). When HIGH, the source is from the Local input port (Local Data Memory). Ignored when LMM is set HIGH. Local Message Mode Bit When LOW, the channel is in Connection Mode. When HIGH, the channel is in Message Mode. Local Output Enable Bit When LOW, the channel may be high impedance, either at the device output or set by an external buffer, dependent upon the LORS pin. When HIGH, the channel is active. Source Stream Address Bits. The binary value of these 4 bits represents the input stream number. Ignored when LMM is set HIGH. Channel Address Bits. The binary value of these 9 bits represents the input channel number, when LMM is LOW. Bits LCAB7-0 transmitted as data when LMM is set HIGH.
14
LMM
13
LE
12-9
LSAB3-0
8-0
LCAB8-0
Table 12 - LCM Bits for Backplane(32Mb/s Mode)-to-Local Switching
38
Advance Information
12.4 Backplane Connection Memory Bit Definition
MT90869
The Backplane Connection Memory (BCM) has 8,192 addresses of 16-bit words. Each address, accessed through bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit definition for each 16-bit word is presented in Table 13 for Local-to- Backplane(Non-32MB/s Mode) and Backplane-to-Backplane(Non-32MB/s Mode) connections, and in Table 14, for Local-toBackplane(32MB/s Mode) and Backplane-to-Backplane(32Mb/s Mode) connections. Bit BSRC selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the perchannel Message Mode is selected (BMM = HIGH), the lower byte of the BCM word (BCAB7-0) will be transmitted as data on the output stream (BSTo0-31) in place of data defined by the Source Control, Stream Address and Channel Address bits. Bit 15 Name BSRC Description Backplane Source Control Bit. When LOW, the source is from the local input port (Local Data Memory). When HIGH, the source is from the backplane input port (Backplane Data Memory). Ignored when BMM is set HIGH. Backplane Message Mode Bit. When LOW, the channel is in Connection Mode. When HIGH, the channel is in Message Mode. Backplane Output Enable Bit. When LOW the channel may be high impedance, either at the device output or set by an external buffer, dependent upon the BORS pin. When HIGH the channel is active. Backplane Source Stream Address Bits. The binary value of these 5 bits represents the input stream number. Ignored when BMM is set HIGH. Source Channel Address Bits. The binary value of these 8 bits represents the input channel number when BMM is set LOW. Transmitted as data when BMM is set HIGH.
14
BMM
13
BE
12-8
BSAB4-0
7-0
BCAB7-0
Table 13 - BCM Bits for Local-to-Backplane and Backplane-to-Backplane Switching (Non-32Mb/s Mode) Bit 15 Name BSRC Description Backplane Source Control Bit. When LOW, the source is from the local input port (Local Data Memory). When HIGH, the source is from the backplane input port (Backplane Data Memory). Ignored when BMM is set HIGH. Backplane Message Mode Bit. When LOW, the channel is in Connection Mode. When HIGH, the channel is in Message Mode. Backplane Output Enable Bit. When this bit is low the channel may be high impedance, either at the device output or set by an external buffer, dependent upon the BORS pin. When the bit is high the channel is active. Backplane Source Stream Address Bits. The binary value of these 4 bits represents the input stream number. Ignored when BMM is set HIGH. Source Channel Address Bits. The binary value of these 9 bits represents the input channel number, when BMM is LOW.Bits BCAB7-0 transmitted as data when BMM is set HIGH.
14
BMM
13
BE
12-9
BSAB3-0
8-0
BCAB8-0
Table 14 - BCM Bits for Backplane-to-Backplane Switching (32Mb/s mode)
39
MT90869
12.5 Internal Register Mappings A14 - A0 0000H 0001H 0002H 0003H - 0022H 0023H - 0042H 0043H - 0062H 0063H - 0082H 0083H - 00A2H 00A3H - 00C2H 00C3H 00C4H 00C5H 00C6H 00C7H 00C8H 00C9H 00CAH 00CBH 00CCH 00CDH - 00ECH 00EDH - 010CH 010DH - 012CH 012DH - 014CH 014DH 1FFFH Control Register, CR Block Programming Register, BPR BER Control Register, BERCR Register
Advance Information
Local Input Channel Delay Register 0, LCDR0 - Register 31, LCDR31 Local Input Bit Delay Register 0, LIDR0 - Register 31, LIDR31 Backplane Input Channel Delay Register 0, BCDR0 - Register 31, BCDR31 Backplane Input Bit Delay Register 0, BIDR0 - Register 31, BIDR31 Local Output Advancement Register 0, LOAR0 - Register 31, LOAR31 Backplane Output Advancement Register 0, BOAR0 - Register 31, BOAR31 Local BER Start Send Register, LBSSR Local Transmit BER Length Register, LTXBLR Local Receive BER Length Register, LRXBLR Local BER Start Receive Register, LBSRR Local BER Count Register, LBCR Backplane BER Start Send Register, BBSSR Backplane Transmit BER Length Register, BTXBLR Backplane Receive BER Length Register, BRXBLR Backplane BER Start Receive Register, BBSRR Backplane BER Count Register, BBCR Local Input Bit rate Register 0, LIBRR0 - Register 31, LIBRR31 Local Output Bit rate Register 0, LOBRR0 - Register 31, LOBRR31 Backplane Input Bit rate Register 0, BIBRR0 - Register 31, BIBRR31 Backplane Output Bit rate Register 0, BOBRR0 - Register 31, BOBRR31 Memory BIST Register, MBISTR Revision control register, RCR Table 15 - Address Map for Register (A14 = 0)
40
Advance Information
13.0 Detailed Register Description
MT90869
This section describes the registers that are used in the device. 13.1 Control Register (CR)
Address 0000h. The control register defines which memory is to be accessed. It initiates the memory block programming mode and selects the backplane data rate mode. The Control Register (CR) is configured as follows: Bit 15-9 8 Name Reserved FPW Reset 0 0 Reserved. Frame Pulse Width When LOW, an input frame pulse width of 122ns shall be applied to FP8i. When HIGH, an input frame pulse width of 244ns shall be applied to FP8i. 32MHz Mode When LOW, Backplane streams (BSTi0-31 and BSTo0-31) may be individually programmed for data-rates of 2, 4, 8, or 16Mb/s. When HIGH, the Backplane streams (BSTi0-15 and BSTo0-15) operate in 32Mb/s mode. 8MHz Input Clock Polarity The frame boundary is aligned to the clock falling or rising edge. When set LOW, the frame boundary is aligned to the clock falling edge. When set HIGH, the frame boundary is aligned to the clock rising edge. Output Clock Polarity When set LOW, the output clock is the same polarity as the input clock. When set HIGH, the output clock is inverted. This applies to both 8MHz (C8o)and 16MHz (C16o) output clocks. Memory Block Programming When LOW, the memory block programming mode is disabled. When HIGH, the connection memory block programming mode is ready to program the Local Connection Memory (LCM), and the Backplane Connection Memory (BCM). Output Stand By This bit enables the BSTo0 - 31 and the LSTo0 - 31 serial outputs.
ODE Pin 0 1 1 OSB bit X 0 1 BSTo0 - 31, LSTo0 - 31 Disable Disable Enable
Description
7
MODE32
0
6
C8IPOL
0
5
COPOL
0
4
MBP
0
3
OSB
0
Output Control with ODE pin and OSB bit When LOW, the BSTo0-31 and LSTo0-31 are driven high or high impedance, dependent on the BORS and LORS pin settings respectively, and BCSTo0-3 and LCSTo0-3 are driven low. When HIGH, the BSTo0-31, LSTo0-31, BCSTo0-3 and LCSTo0-3 are enabled. 2-0 MS(2:0) 0 Memory Select Bits. These three bits select the connection or data memory for subsequent micro-port memory access operations: 000, Local Connection Memory (LCM) is selected for Read or Write operations. 001, Backplane Connection Memory (BCM) is selected for Read or Write operations. 010, Local Data Memory is selected for Read-only operation. 011, Backplane Data Memory is selected for Read-only operation. Table 16 - Control Register Bits
41
MT90869
Frame Boundary
(a) Frame Pulse Width = 122ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 0
Advance Information
C8i_b FP8i_b
(b) Frame Pulse Width = 122ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 1
C8i_b FP8i_b
(c) Frame Pulse Width = 244ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 0
C8i_b FP8i_b
(d) Frame Pulse Width = 244ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 1
C8i_b FP8i_b
Figure 18 - Frame Boundary Conditions, ST- BUS Operation
42
Advance Information
MT90869
Frame Boundary
(e) Pulse Width = 122ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 0
C8i_b FP8i_b
(f) Pulse Width = 122ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 1
C8i_b FP8i_b
(g) Pulse Width = 244ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 0
C8i_b FP8i_b
(h) Pulse Width = 244ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 1
C8i_b FP8i_b
Figure 19 - Frame Boundary Conditions, GCI - BUS Operation
43
MT90869
13.2 Block Programming Register (BPR)
Advance Information
Address 0001h. The block programming register stores the bit patterns to be loaded into the connection memories when the Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must be defined in the same write operation. The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame period and may be instigated at any time within a frame.The BPE bit returns to LOW to indicate the block programming function has completed. When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except to abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the Control Register bit, MBP, to LOW. The BPR register is configured as follows.
.
Bit 15-7 6-4
Name Unused BBPD(2:0)
Reset 0 0 Set LOW.
Description
Backplane Block Programming Data. These bits refer to the value loaded into the Backplane Connection Memory (BCM) when the Memory Block Programming feature is activated. When the MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM. Bits 12-0 of the BCM are set LOW Local block Programming Data. These bits refer to the value loaded into the Local Connection Memory (LCM), when the Memory Block Programming feature is activated. When the MBP bit in the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM. Bits 12-0 of the LCM are set LOW Block Programming Enable. A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125us, upon completion of programming. Set LOW to abort the programming operation. Table 17 - Block Programming Register Bits
3-1
LBPD(2:0)
0
0
BPE
0
44
Advance Information
13.3 Bit Error Rate Test Control Register (BERCR)
MT90869
Address 0002h. The BER control register controls backplane and local port BER testing. It independently enables and disables transmission and reception. It is configured as follows: Bit 15-12 11 Name Reserved LOCKB RESET 0 0 Reserved. Backplane Lock (READ ONLY). This bit is automatically set HIGH when the receiver has locked to the incoming data sequence. The bit is reset by a LOW to HIGH transition on SBERRXB. PBER Reset for Backplane. A LOW to HIGH transition initializes the backplane BER generator to the seed value. Clear Bit Error Rate Register for Backplane. A LOW to HIGH transition in this bit resets the backplane internal bit error counter and the backplane bit error (BBERR) register to zero. Start Bit Error Rate Receiver for Backplane. A LOW to HIGH transition enables the Backplane BER receiver. The receiver monitors incoming data for reception of the seed value. When detected, the LOCK state is indicated (LOCKB) and the receiver compares the incoming bits with the reference generator for bit equality and increments the Backplane Bit error Register (BBCR) on each failure. When set LOW, bit comparison is disabled and the error count is frozen. The error count is stored in the Backplane Bit Error Register (BBCR). Start Bit Error Rate Transmitter for Backplane. A LOW to HIGH transition starts the BER transmission. When set LOW, transmission is disabled. BER Mode Select for Backplane. When set HIGH, a PRBS sequence of length 223-1 is selected for the Backplane port. When set LOW, a PRBS sequence of length 215-1 is selected for the Backplane port. Local Lock (READ ONLY). This bit is automatically set HIGH when the receiver has locked to the incoming data sequence. The bit is reset by a LOW to HIGH transition on SBERRXL PBER Reset for Local. A LOW to HIGH transition initializes the local BER generator to the seed value. Clear Bit Error Rate Register for Local. A LOW to HIGH transition resets the local internal bit error counter and the local bit error (LBERR) register to zero. Description
10
PRSTB
0
9
CBERB
0
8
SBERRX B
0
7
SBERTX B PRBSB
0
6
0
5
LOCKL
0
4 3
PRSTL CBERL
0 0
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits
45
MT90869
Bit 2 Name SBERRX L RESET 0 Description
Advance Information
Start Bit Error Rate Receiver for Local. A LOW to HIGH transition enables the Local BER receiver. The receiver monitors incoming data for reception of the seed value. When detected, the LOCK state is indicated (LOCKL) and the receiver compares the incoming bits with the reference generator for bit equality and increments the Local Bit error Register (LBCR) on each failure. When set LOW, bit comparison is disabled and the error count is frozen. The error count is stored in the Local Bit Error Register (LBCR). Start Bit Error Rate Transmitter for Local. A LOW to HIGH transition enables the Local BER transmission. When set LOW, transmission is disabled. BER Mode Select for Local. When set HIGH, a PRBS sequence of length 223-1 is selected for the Local port. When set LOW, a PRBS sequence of length 215-1 is selected for the Local port.
1
SBERTXL
0
0
PRBSL
0
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits (continued) 13.4 Local Input Channel Delay Registers (LCDR0 to LCDR31)
Address 0003h to 0022h. Thirty-two local input channel delay registers (LCDR0 to LCDR31) allow users to program the input channel delay for the local input data streams LSTi0-31. The possible adjustment is 255 channels and the LCDR0 to LCDR31 registers are configured as follows:
:
LCDRn Bit
(where n = 0 to 31)
Name Reserved LCD(7:0)
Reset 0 0 Reserved
Description
15-8 7-0
Local Channel Delay Register The binary value of these bits refers to the channel delay value for the local input stream.
Table 19 - Local Channel Delay Register (LCDRn) Bits
46
Advance Information
13.4.1 Local Channel Delay Bits 7-0 (LCD7 - LCD0)
MT90869
These eight bits define the delay, in channel numbers, the serial interface receiver take to store the channel data from the Local stream input pins. The input channel delay can be selected to 255 (16Mb/s streams), 127 (8Mb/s streams), 63 (4Mb/s streams) or 31 (2Mb/s streams) from the frame boundary. Corresponding Delay Bits LCD7-LCD0 0 Channel (Default) 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... ... 253 Channels 254 Channels 255 Channels 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 ... ... 1111 1101 1111 1110 1111 1111
Input Stream Channel Delay
Table 20 - Local Input Channel Delay Programming Table
47
MT90869
13.5 Local Input Bit Delay Registers (LIDR0 to LIDR31)
Advance Information
Address 0023h to 0042h. Thirty-two local input delay registers (LIDR0 to LIDR31) allow users to program the input bit delay for the local input data streams LSTi0-31. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a resolution of 1/4 of the data rate. The data rate can be either 2Mb/s, 4Mb/s, 8Mb/s or 16Mb/s. The LIDR0 to LIDR31 registers are configured as follows:
LIDRn Bit
(where n = 0 to 31)
Name Reserved LIDn(4:0)
Reset 0 0 Reserved
Description
15-5 4-0
Local Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the local input stream
Table 21 - Local Channel Delay Register (LIDRn) Bits 13.5.1 Local Input Delay Bits 4-0 (LID4 - LID0)
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit delay adjustment can range up to 73/4 bit periods forward, with resolution of 1/4 bit period. This can be described as: LIDn(4:0) = (no. of bits delay) / 4 For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4. Table 22, "Local Input Bit Delay Programming Table," on page 48, illustrates the bit delay selection. Corresponding Delay Bits Data Rate 0 (Default) 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 3 1/2 LID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 LID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 LID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 LID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Table 22 - Local Input Bit Delay Programming Table
48
Advance Information
Corresponding Delay Bits Data Rate 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 LID4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LID3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LID2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
MT90869
LID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 22 - Local Input Bit Delay Programming Table (continued) 13.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR31)
Address 0043h to 0062h Thirty-two backplane input channel delay registers (BCDR0 to BCDR31) allow users to program the input channel delay for the backplane input data streams BSTi0-31. The possible adjustment is 511 channels and the BCDR0 to BCDR31 registers are configured as follows: BCDRn Bit
(where n = 0 to 31 for non-32Mb/s mode, n = 0 to 15 for 32Mb/s mode)
Name
Reset
Description
15-9 8-0
Reserved BCD(8:0)
0 0
Reserved Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the backplane input stream
Table 23 - Backplane Channel Delay Register (BCDRn) Bits
49
MT90869
13.6.1 Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0)
Advance Information
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the Local input pins. The input channel delay can be selected to 511 (32Mb/s streams), 255 (16Mb/s streams), 127 (8Mb/s streams), 63 (4Mb/s streams) or 31 (2Mb/s streams) from the frame boundary. Corresponding Delay Bits BCD8-BCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ... ... 1 1111 1101 1 1111 1110 1 1111 1111
Input Stream Channel Delay 0 Channel (Default) 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... ... 509 Channels 510 Channels 511 Channels
Table 24 - Backplane Input Channel Delay (BCD) Programming Table
50
Advance Information
13.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
MT90869
Address 0063h to 0082h Thirty-two backplane input delay registers (BIDR0 to BIDR31) allow users to program the input bit delay for the backplane input data streams BSTi0-31. The possible adjustment is 7 3/4 of the data rate, in step of 1/4 of the data rate. The data rate can be either 2Mb/s, 4Mb/s, 8Mb/s, 16Mb/s, or 32Mb/s. The BIDR0 to BIDR31 registers are configured as follows: BIDRn Bit
(where n = 0 to 31 for Non-32Mb/s Mode, n = 0 to15 for 32Mb/s Mode)
Name Reserved BID(4:0)
Reset 0 0 Reserved
Description
15-5 4-0
Backplane Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the backplane input stream
Table 25 - Backplane Input Bit Delay Register (BIDRn) Bits 13.7.1 Backplane Input Delay Bits 4-0 (BID4 - BID0)
These five bits define how long in the cycle the serial interface receiver takes to recognize and stores the bit 0 from the BSTi input pins: i.e., start assuming a new frame. Input bit delay adjustment can range up to 73/4 bit periods forward with resolution of 1/4 bit period. This can be described as BIDn(4:0) = (no. of bits delay) / 4 For example, if BID(4:0) is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
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MT90869
Table 26 illustrates the bit delay selection. Corresponding Delay Bits Data Rate 0 (Default) 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 BID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Advance Information
BID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 26 - Backplane Input Bit Delay Programming Table
52
Advance Information
13.8 Local Output Advancement Registers (LOAR0 to LOAR31)
MT90869
Address 0083h to 00A2h. Thirty-two local output advancement registers (LOAR0 to LOAR31) allow users to program the output advancement for output data streams LSTo0 to LSTo31. The possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072MHz). The LOAR0 to LOAR31 registers are configured as follows: LOARn Bit
(where n = 0 to 31)
Name Reserved LOA(1:0)
Reset 0 0 Reserved
Description
15-2 1-0
Local Output Advancement Register
Table 27 - Local Output Advancement Register (LOARn) Bits 13.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When the advancement is 0, the serial output stream has the normal alignment with the local frame pulse. Local Output Advancement Clock Rate 131.072MHz 0 (Default) -2 cycle -4 cycles -6 cycles Corresponding Advancement Bits LOA1 0 0 1 1 LOA0 0 1 0 1
Table 28 - Local Output Advancement (LOAR) Programming Table
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MT90869
13.9 Backplane Output Advancement Registers (BOAR0 - 31)
Advance Information
Address 00A3h to 00C2h Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output advancement for output data streams BSTo0 to BSTo31. For 2Mb/s, 4Mb/s, 8Mb/s and 16Mb/s stream operation the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072MHz). For 32Mb/ s stream operation the possible adjustment is -1, -2 or -3 cycles of the internal system clock (131.072MHz). The BOAR0 to BOAR3 registers are configured as follows: BOARn Bit
(where n = 0 to 31 for non-32Mb/s mode, n = 0 to 15 for 32Mb/s mode)
Name Reserved BOA(1:0)
Reset 0 0 Reserved
Description
15-2 1:0
Backplane Output Advancement Register
Table 29 - Backplane Output Advancement Register (BOAR) Bits 13.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When the advancement is 0, the serial output stream has the normal alignment with the backplane frame pulse. Backplane Output Advancement For 2Mb/s, 4Mb/s, 8Mb/s & 16Mb/s clock Rate 131.072 MHz 0 (Default) -2 cycle -4 cycles -6 cycles Backplane Output Advancement For 32Mb/s clock Rate 131.072 MHz 0 (Default) -1 cycle -2 cycle -3 cycle Corresponding Advancement Bits BOA1 0 0 1 1 BOA0 0 1 0 1
Table 30 - Backplane Output Advancement (BOAR) Programming Table
54
Advance Information
13.10 13.10.1 Local Bit Error Rate (BER) Registers Local BER Start Send Register (LBSSR)
MT90869
Address 00C3h. Local BER Start Send Register defines the output channel and the stream in which the BER sequence starts to be transmitted. The LBSSR register is configured as follows: Bit 15-13 12-8 Name Reserved LBSSA(4:0) Reset 0 0 Reserved. Local BER Send Stream Address Bits. The binary value of these bits refers to the local output stream which carries the BER data. Local BER Send Channel Address Bits. The binary value of these bits refers to the local output channel in which the BER data starts to be sent. Description
7-0
LBSCA(7:0)
0
Table 31 - Local BER Start Send Register (LBSSR) Bits 13.10.2 Local Transmit BER Length Register (LTXBLR)
Address 00C4h Local BER Transmit Length Register (LTXBLR) defines how many channels the BER sequence will be transmitted during each frame. The LTXBLR register is configured as follows: Bit 15-8 7-0 Name Reserved LTXBL(7:0) Reset 0 0
Reserved.
Description
Local Transmit BER Length Bits The binary value of these bits define the number of channels in addition to the Start Channel that the BER data will be transmitted on. (i.e. Total Channels = Start Channel + LTXBL value)
Table 32 - Local BER Length Register (LTXBLR) Bits 13.10.3 Local Receive BER Length Register (LRXBLR)
Address 00C5h Local BER Receive Length Register (LRXBLR) defines how many channels the BER sequence will be received during each frame. The LRXBLR register is configured as follows: Bit 15-8 7-0 Name Reserved LRXBL(7:0) Reset 0 0 Reserved. Local Receive BER Length Bits The binary value of these bits define the number of channels in addition to the Start Channel allocated for the BER receiver. (i.e. Total Channels = Start Channel + LRXBL value) Description
Table 33 - Local Receive BER Length Register (LRXBLR) Bits
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MT90869
13.10.4 Local BER Start Receive Register (LBSRR) Address 00C6h
Advance Information
Local BER Start Receive Register defines the Input Stream and Start Channel and the stream in which the BER sequence shall be received. The LBSRR register is configured as follows: Bit 15-13 12-8 Name Reserved LBRSA(4:0) Reset 0 0 Reserved. Local BER Receive Stream Address Bits The binary value of these bits refers to the local input stream to receive the BER data. Local BER Receive Channel Address Bits The binary value of these bits refers to the local input channel in which the BER data starts to be compared. Description
7-0
LBRCA(7:0)
0
Table 34 - Local BER Start Receive Register (LBSRR) Bits 13.10.5 Local BER Count Register (LBCR)
Address 00C7h Local BER Count Register contains the number of counted errors. This register is read only. The LBCR register is configured as follows: Bit 15-0 Name LBC(15:0) Reset 0 Description Local Bit Error Rate Count The binary value of the bits define the Local Bit Error count.
Table 35 - Local BER Count Register (LBCR) Bits
56
Advance Information
13.11 13.11.1 Backplane Bit Error Rate (BER) Registers Backplane BER Start Send Register (BBSSR)
MT90869
Address 00C8h Backplane BER Start Send Register defines the output channel and the stream in which the BER sequence is transmitted. The BBSSR register is configured as follows: Bit 15-14 13-9 Name Reserved BBSSA(4:0) Reset 0 0 Reserved. Backplane BER Send Stream Address Bits The binary value of these bits define the backplane output stream to transmit the BER data. Backplane BER Send Channel Address Bits The binary value of these bits define the backplane output Start Channel in which the BER data is transmitted. Description
8-0
BBSCA(8:0)
0
Table 36 - Backplane BER Start Send Register (BBSSR) Bits 13.11.2 Backplane Transmit BER Length Register (BTXBLR)
Address 00C9h Backplane Transmit BER Length Register (BTXBLR) defines how many channels in each frame the BER sequence will be transmitted. The BTXBLR register is configured as follows: Bit 15-9 8-0 Name Reserved BTXBL(8:0) Reset 0 0 Reserved. Backplane Transmit BER Length Bits The binary value of these bits define the number of channels in addition to the Start Channel allocated for the BER Transmitter. (i.e. Total Channels = Start Channel + BTXBL value) Description
Table 37 - Backplane Transmit BER Length (BTXBLR) Bits
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MT90869
13.11.3 Backplane Receive BER Length Register (BRXBLR) Address 00CAh
Advance Information
Backplane Receive BER Length Register (BRXBLR) defines how many channels in each frame the BER sequence will be transmitted. The BRXBLR register is configured as follows: Bit 15-9 8-0 Name Reserved BRXBL(8:0) Reset 0 0 Reserved. Backplane Receive BER Length Bits The binary value of these bits define the number of channels in addition to the Start Channel allocated for the BER receiver. (i.e. Total Channels = Start Channel + BRXBL value) Description
Table 38 - Backplane Receive BER Length (BRXBLR) Bits 13.11.4 Backplane BER Start Receive Register (BBSRR)
Address 00CBh Backplane BER Start Receive Register defines the Input Stream and the Start Channel in which the BER sequence shall be received. The BBSRR register is configured as follows: Bit 15-14 13-9 Name Reserved BBRSA(4:0) Reset 0 0 Reserved. Backplane BER Receive Stream Address Bits The binary value of these bits defines the backplane input stream that receives the BER data. Backplane BER Receive Channel Address Bits The binary value of these bits define the backplane input start channel in which the BER data will be received. Description
8-0
BBRCA(8:0)
0
Table 39 - Backplane BER Start Receive Register (BBSRR) Bits 13.11.5 Backplane BER Count Register (BBCR)
Address 00CCh Backplane BER Count Register contains the number of counted errors. This register is read only. The BBCR register is configured as follows: Bit 15-0 Name BBC(15:0) Reset 0 Description Backplane Bit Error Rate Count The binary value of these bits define the Backplane Bit Error count.
Table 40 - Backplane BER Count Register (BBCR) Bits
58
Advance Information
13.12 13.12.1 Local Bit Rate Registers Local Input Bit Rate Registers (LIBRR0-31)
MT90869
Address 00CDh to 00ECh Thirty-two Local Input Bit Rate Registers allow the bit rate for each individual stream, to be set to 2, 4, 8 and 16 Mb/s. The LIBRR registers are configured as follows: LIBRn
(for n=0 to 31)
Name Reserved LIBR(1:0)
Reset 0 0 Reserved Local Input Bit Rate
Description
15-2 1-0
Table 41 - Local Input Bit Rate Register (LIBRRn) Bits
LIBR1 0 0 1 1
LIBR0 0 1 0 1
Bit rate for stream n 2Mb/s 4Mb/s 8Mb/s 16Mb/s
Table 42 - Local Input Bit Rate (LIBR) Programming Table 13.12.2 Local Output Bit Rate Resisters (LOBRR0-31)
Address 00EDh to 010Ch thirty-two Local Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 and 16 Mb/s. The LOBRR registers are configured as follows: LOBRn Bit
(where n = 0 to 31)
Name Reserved LOBR(1:0)
Reset 0 0 Reserved Local Output Bit Rate
Description
15-2 1-0
Table 43 - Local Output Bit Rate Register (LOBRRn) Bits LOBR1 0 0 1 1 LOBR0 0 1 0 1 Bit rate for stream n 2Mb/s 4Mb/s 8Mb/s 16Mb/s
Table 44 - Output Bit Rate (LOBR) Programming Register
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13.13 13.13.1 Backplane Bit Rate Registers Backplane Input Bit Rate Registers (BIBRR0-31)
Advance Information
Address 010Dh to 012Ch Thirty-two Backplane Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 and 16 Mb/s. These registers may be overridden by setting 32Mb/s mode in the control register, in which case, backplane streams 0-15 will operate at 32Mb/s and backplane streams 16-31 will be unused. The BIBRR registers are configured as follows: BIBRn Bit (for n=0 to 31) 15-2 1-0 Name Reserved BIBR(1:0) Reset 0 0 Reserved Backplane Input Bit Rate Description
Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits
BIBR1 0 0 1 1
BIBR0 0 1 0 1
Bit rate for stream n 2Mb/s 4Mb/s 8Mb/s 16Mb/s
Table 46 - Backplane Input Bit Rate (BIBR) Programming Table 13.13.2 Backplane Output Bit Rate Registers (BOBRR0-31)
Address 012Dh to 014Ch Thirty-two Backplane Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 and 16 Mb/s.These registers may be overridden by setting 32Mb/s mode in the control register, in which case, backplane streams 0-15 will operate at 32Mb/s and backplane streams 16-31 will be unused. The BOBRR registers are configured as follows: BOBRn Bit
(for n=0 to 31)
Name Reserved BOBR(1:0)
Reset 0 0 Reserved
Description
15-2 1-0
Backplane Output Bit Rate
Table 47 - Backplane Output Bit Rate Register (BOBRRn) Bits
60
Advance Information
BOBR1 0 0 1 1 BOBR0 0 1 0 1 Bit rate for stream n 2Mb/s 4Mb/s 8Mb/s 16Mb/s
MT90869
Table 48 - Backplane Output Bit Rate (BOBRR) Programming Table 13.14 Memory BIST Register
Address 014Dh The Memory BIST register enables the self-test of chip memory. Two consecutive write operations are required to start MBIST. The first with only Bit 12 (LV_TM) set High (i.e. 1000h), the second with Bit 12 maintained High but with the required start bit(s) set High. The MBISTR register is configured as follows: Bit 15-13 12 11 10 9 Name Reserved LV_TM BISTSDB BISTCDB BISTPDB Reset 0 0 0 0 0 Reserved. MBIST Test enable. High for MBIST mode, Low for scan mode. Backplane Data Memory Start BIST sequence. Sequence enabled on LOW to HIGH transition. Backplane Data Memory BIST sequence completed. (Read only). High indicates completion of Memory BIST sequence. Backplane Data Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence. A LOW indicates Pass, a HIGH indicates Fail. Local Data Memory Start BIST sequence. Sequence enabled on LOW to HIGH transition. Local Data Memory BIST sequence completed. (Read only). High indicates completion of Memory BIST sequence. Local Data Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence. A LOW indicates Pass, a HIGH indicates Fail. Backplane Connection Memory Start BIST sequence. Sequence enabled on LOW to HIGH transition. Backplane Connection Memory BIST sequence completed. (Read only). High indicates completion of Memory BIST sequence. Backplane Connection Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence. A LOW indicates Pass, a HIGH indicates Fail. Table 49 - Memory BIST Register (MBISTR) Bits Description
8 7 6
BISTSDL BISTCDL BISTPDL
0 0 0
5 4 3
BISTSCB BISTCCB BISTPCB
0 0 0
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Bit 2 1 0 Name BISTSCL BISTCCL BISTPCL Reset 0 0 0 Description Local Connection Memory Start BIST sequence. Sequence enabled on LOW to HIGH transition.
Advance Information
Local Connection Memory BIST sequence completed. (Read only). High indicates completion of Memory BIST sequence. Local Connection Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence. A LOW indicates Pass, a HIGH indicates Fail.
Table 49 - Memory BIST Register (MBISTR) Bits (continued) 13.15 Revision Control Register
Address 1FFFh The revision control register stores the binary value of the silicon revision number. This register is read only. The RCR register is configured as follows: Bit 15-4 3-0 Name Reserved RC(3:0) Reset Value 0 defined by silicon Reserved. Revision Control Bits. Description
Table 50 - Revision Control Register (RCR) Bits
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Advance Information
DC Electrical Characteristics
Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 8 Core Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Voltage (non-5V tolerant inputs) Input Voltage (5V tolerant inputs) Continuous Current at digital outputs Package power dissipation Storage temperature Symbol VDD_CORE VDD_IO VDD_PLL VI VI_5V Io PD TS - 55 Min -0.5 -0.5 -0.5 -0.5 -0.5
MT90869
Max 2.5 5.0 2.5 VDD_IO +0.5 7.0 15 2 +125
Units V V V V V mA W C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions Characteristics 1 2 3 4 5 6 Operating Temperature Positive Supply Positive Supply Positive Supply Input Voltage Input Voltage on 5V Tolerant Inputs Sym TOP VDD_IO VDD_CORE VDD_PLL VI VI_5V Min -40 3.0 1.62 1.62 0 0 Typ 25 3.3 1.8 1.8 3.3 5 Max +85 3.6 1.98 1.98 VDD_IO 5.5 Units C V V V V V
Voltages are with respect to ground (VSS) unless otherwise stated.
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MT90869
DC Electrical Parameters
Characteristics 1a I 1b N 1c 1d P U T 2 3 4 S Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Weak Pullup Current 5 6 7 8 9 10 O U T P U T S Weak Pulldown Current Input Pin Capacitance Output High Voltage Output Low Voltage High Impedance Leakage Output Pin Capacitance VIH VIL IIL IBL IPU IPD CI VOH VOL IOZ CO 2.4 0.4 5 5 2.0 0.8 5 5 -200 200 5 Supply Current Supply Current Supply Current IDD_Core IDD_IO IDD_IO 160 200 100 110 Supply Current Sym IDD_Core Min Typ Max 4
Advance Information
Units mA mA A mA
Test Conditions Static IDD_Core and PLL current Applied clock C8i = 8.192 MHz Static IDD_IO IAV with all output streams at max. data-rate
V V A A A A pF V V A pF IOH = 10mA IOL = 10mA 0 < V < VDD_IO 0 < V < VDD_IO Input at 0V Input at VDD_IO
Voltages are with respect to ground (Vss) unless otherwise stated.
AC Electrical Characteristics
Characteristics 1 2 3 CMOS Threshold Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low
Timing Parameter Measurement: Voltage Levels
Sym VCT VHM VLM
Level 0.5VDD_IO 0.7VDD_IO 0.3VDD_IO
Units V V V
Conditions
64
Advance Information
Backplane and Local Clock Timing
Characteristic 1 Backplane Frame Pulse Width Sym tBFPW244 tBFPW122 tBGFPW tBFPS244 tBFPS122 tBGFPS tBFPH244 tBFPH122 tBGFPH tBCP8 tBCH8 tBCL8 trBC8i, tfBC8i tLFBOS tLFPW8 tGFPW8 tLFODF8 tGFPS8o tLFODR8 tGFPH8o tLCP8 tLCH8 tLCL8 trLC8o, tfLC8o tFPW16 tFODF16 tFODR16 tLCP16 tLCH16 tLCL16 trLC16o, tfLC16o 117 117 56 56 59 59 117 56 59 3 62 -29 30 62 29 30 0 122 122 Min 210 10 10 5 5 5 5 5 5 120 50 50 0 122 61 61 2 Typ 244 122 122 Max 350 220 220 110 110 110 110 110 110 124 70 70 3 7.5 127 127 68 56 61 61 127 68 61 7 66 -36 33 66 36 33 5
MT90869
Units ns Notes
2
Backplane Frame Pulse Setup Time before C8i clock falling edge Backplane Frame Pulse Hold Time from C8i clock falling edge C8i Clock Period C8i Clock Pulse Width High C8i Clock Pulse Width Low C8i Clock Rise/Fall Time Local Frame Boundary Offset FP8o Width FP8o Output Delay from edge to Local Frame Boundary FP8o Output Delay from Local Frame Boundary to Edge C8o Clock Period C8o Clock Pulse Width High C8o Clock Pulse Width Low C8o Clock Rise/Fall Time FP16o Width FP16o Output Delay from Falling edge to Local Frame Boundary FP16o Output Delay from Local Frame Boundary to Rising edge C16o Clock Period C16o Clock Pulse Width High C16o Clock Pulse Width Low C16o Clock Rise/Fall Time
ns
3
ns
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
ns ns ns ns ns ns CL=60pF ns ns ns ns ns ns ns ns ns ns ns ns ns CL=60pF CL=60pF CL=60pF
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MT90869
Advance Information
tBFPW244 FP8i (244ns) tBFPS244 tBFPW122 tBFPH244
FP8i (122ns) tBFPS122 tBCL8 C8i tBCH8
tBFPH122 tBCP8
trBC8i
tfBC8i
CK_int *
tLFBOS tLFPW8_244
FP8o (244ns) tFODF8_244
tFODR8_244
tLFPW8
FP8o (122ns) tLFODF8 tLCL8 C8o trLC8o tFPW16 FP16o tFODF16 tLCL16 C16o trLC16o * CK_int is the internal clock signal of 131.072MHz tfLC16o tLCH16 tFODR16 tLCP16 tfLC8o tLCH8 tLFODR8 tLCP8
Figure 20 - Backplane and Local Clock Timing Diagram for ST-BUS
66
Advance Information
MT90869
tBGFPW FP8i
tBGFPS tCP8i tBCH8
tBGFPH
tBCL8
C8i tfBCi trBCi
CK_int* tLFBOS tGFPW8 FP8o tGFPS8o tLCL8 C8o tFPW16 tLCH8 tGFPH8o tLCP8
trLC8o
tfLC8o
FP16o tFRS16o tLCH16 tLCL16 tFRH16o tLCP16
C16o * CK_int is the internal clock signal of 131.072MHz trLC16o tfLC16o
Figure 21 - Backplane and Local Clock Timing for GCI-BUS
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Backplane Data Timing
Characteristic 1 Backplane Input data sampling point Sym tBIDS32 tBIDS16 tBIDS8 tBIDS4 tBIDS2 tBSIS32 tBSIS16 tBSIS8 tBSIS4 tBSIS2 tBSIH32 tBSIH16 tBSIH8 tBSIH4 tBSIH2 tBSOD32 tBSOD16 tBSOD8 tBSOD4 tBSOD2 Min 18 41 87 178 361 2.1 2.1 2.1 2.1 2.1 3 3 3 3 3 Typ 23 46 92 183 366
Advance Information
Max 28 51 97 188 371 5 5 5 5 5 5 5 5 5 5 15 15 15 15 15
Units ns
Notes With zero offset.
2
Backplane Serial Input Set-up Time
ns
3
Backplane Serial Input Hold Time
ns
4
Backplane Serial Output Delay
ns
CL=50pF
FP8i C8i CK_int * tBIDS8 tBSIS8 tBSIH8 BSTi0 - 31 8.192Mb/s
1 0 7 6 5 4 3 2 1
tBSOD8 BSTo0 - 31 8.192Mb/s
Bit1 Ch127 Bit0 Ch127 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0
tBIDS4
tBSIS4 tBSIH4
BSTi0 - 31 4.096Mb/s
Bit0 Ch63
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
tBSOD4 BSTo0 - 31 4.096Mb/s
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
tBIDS2 tBSIS2 tBSIH2 BSTi0 - 31 2.048Mb/s BSTo0 - 31 2.048Mb/s
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
tBSOD2
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
* CK_int is the internal clock signal of 131.072MHz
Figure 22 - ST-BUS Backplane Data Timing Diagram (8Mb/s, 4Mb/s, 2Mb/s)
68
Advance Information
MT90869
FP8i C8i CK_int * tBIDS32 tBSIS32 tBSIH32 BSTi0 - 15 32.768Mb/s
2 1 0 7 6 5 4 3 2
tBSOD32 BSTo0 - 15 32.768Mb/s
Bit1 Ch511 Bit1 Ch511 Bit0 Ch511 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0
tBIDS16
tBSIS16 tBSIH16
BSTi0 - 31 16.384Mb/s
Bit1 Ch255
Bit0 Ch255
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
tBSOD16 BSTo0 - 31 16.384Mb/s
Bit0 Ch255 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0
* CK_int is the internal clock signal of 131.072MHz
Figure 23 - ST-BUS Backplane Data Timing Diagram (32Mb/s, 16Mb/s)
69
MT90869
Advance Information
FP8i C8i CK_int * tBIDS8 tBSIS8 tBSIH8 BSTi0 - 31 8.192Mb/s
1 0 7 6 5 4 3 2 1
tBSOD8 BSTo0 - 31 8.192Mb/s
Bit1 Ch127 Bit0 Ch127 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0
tBIDS4
tBSIS4 tBSIH4
BSTi0 - 31 4.096Mb/s
Bit0 Ch63
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
tBSOD4 BSTo0 - 31 4.096Mb/s
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
tBIDS2 tBSIS2 tBSIH2 BSTi0 - 31 2.048Mb/s BSTo0 - 31 2.048Mb/s
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
tBSOD2
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
* CK_int is the internal clock signal of 131.072MHz
Figure 24 - GCI BUS Backplane Data Timing Diagram (8Mb/s, 4Mb/s, 2Mb/s)
70
Advance Information
MT90869
FP8i C8i CK_int * tBIDS32 tBSIS32 tBSIH32 BSTi0 - 15 32.768Mb/s
2 1 0 7 6 5 4 3 2
tBSOD32 BSTo0 - 15 32.768Mb/s
Bit1 Ch511 Bit1 Ch511 Bit0 Ch511 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0
tBIDS16
tBSIS16 tBSIH16
BSTi0 - 31 16.384Mb/s
Bit1 Ch255
Bit0 Ch255
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
tBSOD16 BSTo0 - 31 16.384Mb/s
Bit0 Ch255 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0
* CK_int is the internal clock signal of 131.072MHz
Figure 25 - GCI BUS Backplane Data Timing Diagram (32Mb/s, 16Mb/s)
Local Clock Data Timing
Characteristic 1 2 Local Frame Boundary Offset Input data sampling point Sym tLFBOS tLIDS16 tLIDS8 tLIDS4 tLIDS2 tLSIS16 tLSIS8 tLSIS4 tLSIS2 tLSIH16 tLSIH8 tLSIH4 tLSIH2 tLSOD16 tLSOD8 tLSOD4 tLSOD2 41 87 178 361 2.1 2.1 2.1 2.1 3 3 3 3 46 92 183 366 Min Typ Max 7.5 51 97 188 371 5 5 5 5 5 5 5 5 15 15 15 15 Units ns ns With zero offset. Notes
3
Local Serial Input Set-up Time
ns
4
Local Serial Input Hold Time
ns
5
Local Serial Output Delay
ns
CL=50pF
71
MT90869
FP8i C8i tLFBOS CK_int *
Advance Information
tLIDS16
tLSIS16 tLSIH16
LSTi0 - 31 16.384Mb/s
Bit1 Ch255
Bit0 Ch255
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
tLSOD16 LSTo0 - 31 16.384Mb/s
Bit0 Ch255 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0
* CK_int is the internal clock signal of 131.072MHz
Figure 26 - ST-BUS Local Timing Diagram (16Mb/s)
72
Advance Information
MT90869
FP8o
C8o
tLFBOS
CK_int * tLIDS8 tLSIS8 tLSIH8 LSTi0 - 31 8.192Mb/s
1 0 7 6 5 4 3 2 1
tLSOD8 LSTo0 - 31 8.192Mb/s
Bit1 Ch127 Bit0 Ch127 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0
tLIDS4
tLSIS4 tLSIH4
LSTi0 - 31
4.096Mb/s
Bit0 Ch63
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
tLSOD4 LSTo0 - 31 4.096Mb/s
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
tLIDS2 tLSIS2 tLSIH2 LSTi0 - 31 2.048Mb/s LSTo0 - 31 2.048Mb/s
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
tLSOD2
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
* CK_int is the internal clock signal of 131.072MHz
Figure 27 - ST-BUS Local Data Timing Diagram (8Mb/s, 4Mb/s, 2Mb/s)
Backplane and Local Output High-Impedance Timing
Characteristic 1 2 STo delay - Active to High-Z - High-Z to Active Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Sym tDZ tZD tODE tODZ Min Typ Max 4 4 15 14 Unit s ns ns ns ns Test Conditions RL=1K, CL=50pF, See Note 1
RL=1K, CL=50pF, See Note 1 RL=1K, CL=50pF, See Note 1
Note 1: High Impedance is measured by pulling to mid-rail with R L,= 1k//1k potential divider, with timing corrected for C L.
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MT90869
CLK tDZ STo Valid Data tZD STo HiZ Valid Data VTT HiZ VTT VTT
Advance Information
Figure 28 - Serial Output and External Control
VTT ODE tODE tODZ VTT
STo
Hi-Z
Valid Data
Hi-Z
Figure 29 - Output Driver Enable (ODE)
Non-Multiplexed Microprocessor Port Timing
Characteristics 1 2 3 4 5 6 7 8 9 10 11 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup from DTA Low on Read Data hold on read Data setup on write Data hold on write Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Acknowledgment Hold Time Sym tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tWDS tDHW tAKD 85 70 tAKH 12 ns ns ns CL=60pF CL=60pF CL=60pF, RL=1K, Note 1 8 8 Min 0 8 8 0 8 8 14 30 Typ Max Unit s ns ns ns ns ns ns ns ns ns ns CL=60pF CL=60pF, RL=1K Note 1 Test Conditions
12
Note1: High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L.
74
Advance Information
MT90869
VTT
DS tCSS CS tRWS R/W tADS A0-A14
VALID ADDRESS
tCSH
VTT tRWH VTT tADH VTT tDHR
D0-D15 READ tWDS D0-D15 WRITE
VALID READ DATA
VTT
tDHW
VALID WRITE DATA
VTT
tDDR
DTA
VTT tAKD tAKH
Figure 30 - Motorola Non-Multiplexed Bus Timing
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MT90869
76
D D1
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
14.0
A1 CORNER
b
E1 E
Package and Pin Information
e
J
A B C D E F G H J K L M N P R T U V W Y
TOP VIEW
A A2
I
e
BOTTOM VIEW
bbb C C
A1
SIDE VIEW
SEATING PLANE
The MT90869 is available in a 272-PBGA (Plastic Ball Grid Array) package, body size 27mm x 27mm with 1.27mm ball-pitch. The assembly incorporates a centered 4x4 array of grounded balls for thermal management.
Figure 31 - The MT90869 272-PBGA (Plastic Ball Grid Array) Package
NOTE: 1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982. 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER. 3. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSION A A1 A2 D D1 E E1 I J b e N
MIN. MAX. 1.92 2.32 0.50 0.70 1.12 1.22 26.80 27.20 --24.70 26.80 27.20 --24.70 1.44 REF. 1.44 REF. 0.60 0.90 1.27 BSC 272
Advance Information
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