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NT7701
160 Output LCD Segment/Common Driver
Features
(Segment mode) ! Shift Clock frequency : 14 MHz (Max.) (VDD = 5V 10%) 8 MHz (Max.) (VDD = 2.5V - 4.5V) ! Adopts a data bus system ! 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in the chip select mode, causes the internal clock to be stopped by automatically counting 160 bits of input data (Common mode) ! Shift clock frequency: 4.0MHz (Max.) ! Built-in 160-bits bidirectional shift register (divisible into 80-bits x 2) ! Available in a single mode (160-bits shift register) or in a dual mode (80-bits shift register x 2) 1. Y1 Y160 Single mode 2. Y160 Y1 Single mode 3. Y1 Y80, Y81 Y160 Dual mode 4. Y160 Y81, Y80 Y1 Dual mode The above 4 shift directions are pin-selectable (Both segment mode and common mode) ! Supply voltage for LCD drive: 15.0 to 30.0V ! Number of LCD driver outputs: 160 ! Low output impedance ! Low power consumption ! Supply voltage for the logic system: +2.5 to +5.5V ! COMS process ! Package : 190pin TCP (Tape Carrier Package) ! Not designed or rated as radiation hardened
General Description
The NT7701 is a 160-bit output segment/common driver LSI suitable for driving the large scale dot matrix LCD panels used by PDA's, personal computers and work stations for example. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7701 is good as both a segment driver and a common driver, and a low power consuming, high-precision LCD panel display can be assembled using the NT7701. In the segment mode, the data input is selected 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable.
Pin Configuration
D U M M Y D U M M Y Y 1 6 0 Y 1 5 9 Y 1 5 8 Y 1 5 7 Y 1 5 6 Y 1 5 5 Y 8 3 Y 8 2 Y 8 1 Y 8 0 Y 7 9 Y 7 8 Y 6 Y 5 Y 4 Y 3 Y 2 DD UU MM YMM 1YY
190 189 188 187 186 185
113 112 111 110 109 108
36 35 34 33 32 31
NT7701
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DVVVVVLVSEDDDDDDDDXDLEFMTTVVVVVD U0 1 45S / D / I 01 2 34 5 67C I P I RDEES5 4 1OU ML23LSRDCO KS O SSSR32RM M M P LL 2 1 TT RR Y Y O 12 F F
1
V2.0
NT7701
Pad Configuration
199 200 54 53
NT7701
216 1 36 37
Block Diagram
V0R V12R V43R V5R
Y1 Y2 Y159 Y160
FR Level Shifter
DISPOFF
V5L
160 Bits 4 Level Driver
/160
V43L V12L
160 Bits Level Shifter
EIO1 EIO2
/16
V0L
V5R Active Control
/160
160 Bits Line Latch/Shift Register
/16 /16 /16 /16 /16 /16 /16 /16 /16
LP XCK
8Bits x 2 Data Latch Control Logic
Data Latch Control
L/R MD S/C
/8
SP Conversion & Data Control (4 to 8 or 8 to 8)
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDD
VSS
VSS
2
NT7701
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - 190 Designation V0L V12L V43L V5L VSS L/R VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR MD TEST1 TEST2 VSS V5R V43R V12R V0R Y1 - Y160 I/O P P P P P I P I I/O I I I I I I/O I I I I P P P P P O Description Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these two pads must be connected to each other Display data shift direction selection Power supply for the logic system (+2.5 to +5.5V) Segment mode / common mode selection Input / output for chip select or data of shift register Display data input for segment mode Display data input for Segment mode / Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input/shift clock input for the shift register Input / output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Mode selection input Test pin, no connection for user Test pin, no connection for user Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output
3
NT7701
Pad Description
Pad No. 1, 2 3, 4 5, 6 7, 8 9,10 - 21, 22 23, 24 25, 26 27, 28 29, 30 31, 32 33, 34 35, 36 37, 38, 39, 40 41, 42 43, 44 45, 46 47 - 206 207, 208 209, 210 211, 212 213, 214 215, 216 Designation L/R VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR MD VSS V5R V43R V12R V0R Y1 - Y160 V0L V12L V43L V5L VSS I/O I P I I/O I I I I I I/O I I P P P P P O P P P P P Description Display data shift direction selection Power supply for the logic system (+2.5 to + 5.5V) Segment mode/common mode selection Input/output for chip select or data of shift register Display data input for segment mode Display data input for Segment mode / Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input / shift clock input for the shift register Input/output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Mode selection input Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these two pads must be connected to each other
4
NT7701
Input / Output Circuits
VDD
I
Input Signal
VSS Input Circuit (1)
Applicable Pins L/R, S/C, D0 - D6, DISPOFF , LP, FR, MD
VDD
I Control Signal
Input Signal
Applicable Pins D7, XCK
VSS
VSS Input Circuit (2)
5
NT7701
VDD
Input Signal Control Signal
VSS VDD
VSS Output Signal
I/O
Control Signal
VSS Input / Output Circuit
Applicable Pins EIO1, EIO2
V0
V12
Control Signal 1 O Control Signal 3
Control Signal 2
Control Signal 4
Applicable Pins Y1 to Y160
V43 VSS V5
LCD Driver Output circuit
6
NT7701
Pad Description
Segment mode Symbol VDD VSS VOR, VOL V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias # Normally, the bias voltage used is set by a resistor divider # Ensure that the voltages are set such that VSS V5 < V43 < V12 < V0 # To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43) Input pin for display data # In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD # In 8-bit parallel input mode, input data into the 8 pins D0 - D7 Clock input pin for taking display data # Data is read on the falling edge of the clock pulse Latch pulse input pin for display data # Data is latched on the falling edge of the clock pulse Direction selection pin for reading display data # When set to VSS level "L", data is read sequentially from Y160 to Y1 # When set to VDD level "H", data is read sequentially from Y1 to Y160 Control input pin for output deselect level # The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD driver circuit # When set to VSS level "L", the LCD driver output pins (Y1 - Yl60) are set to level V5 DISPOFF # While DISPOFF is set to "L", the contents of the line latch are reset, but the display data in the data latch are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, can not output the reading data correctly AC signal input for LCD driving waveform # The input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD driver circuit # Normally inputs a frame inversion signal The LCD driver output pin's output voltage level can be set to the line latch output signal and the FR signal Mode selection pin # When set to VSS level "L", 4-bit parallel input mode is set # When set to VDD level "H", 8-bit parallel input mode is set
D0 - D7 XCK LP L/R
FR
MD
7
NT7701
Segment mode continued Symbol S/C Function Segment mode/common mode selection pin # When set to VDD level "H", segment mode is set. # When set to VSS level "L", common mode is set. Input/output pin for chip selection # When L/R input is at VSS level "L", EIO1 is set for output, and EIO2 is set for input. # When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output. # During output, it is set to "H" while LP* XCK is "H" and after 160-bits of data have been read, it is set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H" # During input, after the LP signal is input, the chip is selected while EI is set to "L". After 160-bits of data have been read, the chip is deselected LCD driver output pins These corresponding directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output
EIO1, EIO2
Y1 - Y160
Common mode Symbol VDD VSS V0R, V0L V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias. # Normally, the bias voltage used is set by a resistor divider # Ensure that the voltages are set such that VSS V5 EIO1
EIO2
LP L/R
8
NT7701
Common mode continued Symbol Function Control input pin for output deselect level # The input signal is level-shifted from the logic voltage level to the LCD driver voltage level and it controls the LCD driver circuit # When set to VSS level "L", the LCD driver output pins (Y1 - Y160) are set to level V5 DISPOFF # While set to "L", the contents of the shift resister are reset and not reading data. When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V34), and the shift data is read on the falling edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, the shift data is not reading correctly AC signal input for LCD driving waveform # The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit # Normally, inputs a frame inversion signal The LCD driver output pin's output voltage level can be set using the shift register output signal and the FR signal Mode selection pin # When set to VSS level "L", Single Mode operation is selected. When set to VDD level "H", Dual Mode operation is selected Dual Mode data input pin # According to the data shift direction of the data shift register, data can be input starting from the 81st bit When the chip is used as Dual Mode, D7 will be pulled-down When the chip is used as Single Mode, D7 won't be pulled-down Segment mode/common mode selection pin # When set to VSS level "L", common mode is set Not used # Connect D0-D6 to VSS or VDD. Avoiding floating Not used # XCK is pulled-down in common mode, so connect to VSS or open LCD driver output pins # These corresponding directly Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and output
FR
MD
D7
S/C D0 - D6 XCK Y1 - Y160
9
NT7701
Functional Description
1. Block description 1.1. Active Control In the case of segment mode, controls the selection or deselection of the chip. Following a LP signal input, and after the select signal is input, a select signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a select signal for cascade connection is output, and the ship is deselected. In the case of common mode, controls the input/output data of bidirectional pins. 1.2. SP Conversion & Data Control In the case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of XCK at 8-bit parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. 1.3. Data Latch Control In the case of the segment mode, it selects the state of the data latch, which reads in the data bus signals. The shift direction is controlled by the control logic and for every 16 bits of data read in, the selection signal shifts one bit, based on the state of the control circuit. 1.4. Data Latch In the case of the segment mode, it latches the data on the data bus. The latched state of each LCD driver output pin is controlled by the control logic and the data latch control 160 bits of data are read in 20 sets of 8 bits. 1.5. Line Latch / Shift Register In the case of the segment mode, all 160 bits which have been read into the data latch, are simultaneously latched on to the falling edge of the LP signal, and output to the level shift block. In the case of the common mode, shifts data from the data input pin on to the falling edge of the LP signal. 1.6. Level Shifter The logic voltage signal is level-shifted to the LCD driver voltage level, and output to the driver block. 1.7. 4-Level Driver It drives the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, VSS) based on the S/C, FR and DISPOFF signals. 1.8. Control Logic It controls the operation of each block. In the case of the segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 160 bits of data are read in, and the chip is deselected. In the case of the common mode, it controls the direction of the data shift.
10
NT7701
2. LCD Driver Output Voltage Level The relationship amongst the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table below: 2.1. Segment Mode FR L L H H X Latch Data L H L H X DISPOFF H H H H L Driver Output Voltage Level (Y1 - Y160) V43 V5 V12 V0 V5
Here, VSS V5 < V43 < V12 Here, VSS V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular voltage, which assigned by specification for each power pin. That time "Don't care" should be fixed to "H" or "L", avoiding floating.
11
NT7701
3. Relationship between the Display Data and Driver Output Pins 3.1. Segment Mode: (a) 4-bit Parallel Mode MD L/R EIO1 EIO2 Data Input D0 D1 D2 D3 D0 D1 D2 D3 40clock Y1 Y2 Y3 Y4 Y160 Y159 Y158 Y157 39clock Y5 Y6 Y7 Y8 Y156 Y155 Y154 Y153 Number of Clock 38clcok ~ 3clock ~ Y9 Y149 ~ Y10 Y150 ~ Y11 Y151 ~ Y12 Y152 ~ Y152 Y12 ~ Y151 Y11 ~ Y150 Y10 ~ Y149 Y9 2clock Y153 Y154 Y155 Y156 Y8 Y7 Y6 Y5 1clock Y157 Y158 Y159 Y160 Y4 Y3 Y2 Y1
L
L
Output Input
L
H
Input Output
(b) 8-bit Parallel Mode MD L/R EIO1 EIO2 Data Input D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 20clock Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 19clock Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Number of Clock 18clcok ~ 3clock Y17 ~ Y137 Y18 ~ Y138 Y19 ~ Y139 Y20 ~ Y140 Y21 ~ Y141 Y22 ~ Y142 Y23 ~ Y143 Y24 ~ Y144 Y144 ~ Y24 Y143 ~ Y23 Y142 ~ Y22 Y141 ~ Y21 Y140 ~ Y20 Y139 ~ Y19 Y138 ~ Y18 Y137 ~ Y17 2clock Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 1clock Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1
H
L
Output Input
H
H
Input Output
12
NT7701
3.2. Common Mode MD L (Single) L/R L (shift to left) H (shift to right) L (shift to left) H (Dual) H (shift to right) Data Transfer Direction Y160 to Y1 Y1 to Y160 Y160 to Y81 Y80 to Y1 Y1 to Y80 Y81 to Y160 EIO1 Output Input Output EIO2 Input Output Input D7 X X Input
Input
Output
Input
Here, L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care Note: "Don't care" should be fixed to "H" or "L", avoiding floating.
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NT7701
4. Connection Examples of Segment Drivers 4.1. Case of L/R = "L"
first data (data taking flow) Y160 ---------------------->Y1 Y160 ---------------------->Y1 Y160 ---------------------->Y1 last data
EIO2
EIO1 L/R DI0~DI7
EIO2
EIO1 L/R DI0~DI7
EIO2
EIO1 L/R DI0~DI7
XCK
XCK
XCK
MD
MD
MD
FR
FR
XCK LP MD FR D0 - D7 VSS /8
4.2 Case of L/R = "H"
VDD D0 - D7 FR MD LP XCK /8
MD
MD
XCK
XCK
MD
FR
LP
LP
LP
DI0 - DI7
DI0 - DI7
L/R VSS EIO1 EIO2
L/R EIO1 EIO2
L/R EIO1 EIO2
Y1 ---------------------->Y160 (data taking flow) first data
Y1 ---------------------->Y160
Y1 ---------------------->Y160
DI0 - DI7
last data
14
XCK
FR
FR
FR
LP
LP
LP
NT7701
5. Timing Waveform of 4-Device Cascade Connection of Segment Drivers.
FR
LP
XCK
First data D0 - D7 n12 device A EI (device A) n12 device B n12 device C n12 device D
Last data n12
H L
EO (device A)
EO (device B)
EO (device C) n: 4-bit parallel mode 40 8-bit parallel mode 20
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NT7701
6. Connection Examples for Common Drivers
First Last
Y160
Y1
Y160
Y1
Y160
Y1
D
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
MD
EIO1
L/R
L/R
L/R
MD
MD
MD
FR
FR
D7
D7
LP VSS(VDD) VSS VSS DISPOFF FR
Single Mode (Shifting towards the left)
FR CS DISPOFF VDD VSS VSS(VDD) LP
CS
D7
LP
LP
LP
DISPOFF
FR
L/R
DI7 Y160 Last
FR
EIO2 LP
MD
DISPOFF
DISPOFF
L/R
L/R
DI7
MD
CS
CS
FR
FR
DI7
LP
LP
DI
EIO1
EIO2
EIO1
EIO2
EIO1
Y1
Y160
Y1
Y160
Y1
First
Single Mode (Sifting towards the right)
16
NT7701
First1 Last1 First2 Last2
Y160
Y1
Y160
Y81
Y80
Y1
Y160
Y1
D1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
L/R
L/R
L/R
MD
MD
MD
FR
FR
D7
D7
LP D2 VSS (VDD) VDD VSS DISPOFF FR
Dual mode (Shifting towards the left)
FR DISPOFF VDD VDD VSS (VDD) D2 LP
MD
MD
D7
LP
LP
LP
MD
D7
D7
D7
LP
LP
FR
L/R
L/R
DISPOFF
DISPOFF
D1
EIO1
EIO2
EIO1
EIO2
EIO1
DISPOFF
L/R
FR
FR
FR
EIO2
Y1
Y160
Y1
Y80
Y81
Y160
Y1
Y160
First1
Last1 First2
Last2
Dual mode (Shifting towards the right)
17
LP
NT7701
7. Precaution Be careful when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur, if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows: ! ! When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. We recommend that you connect a serial resistor (50-100) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value for the resistor in consideration of the LCD display grade.
In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore connect the LCD driver power supply after resetting logic condition of this LSI inside on DISPOFF function. After that, the DISPOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level VSS on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown.
VDD VSS VDD
DISPOFF
VDD
VSS V0
V0 VSS
18
NT7701
Absolute Maximum Rating*
DC Supply Voltage VDD . . . . . . . . . . . . -0.3V to +7.0V DC Supply Voltage V0 . . . . . . . . . . . . . -0.3V to +30V Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Ambient Temperature . . . . -30C to +85C Storage Temperature . . . . . . . . . . . . .-45C to +125C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
DC Characteristics Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85C, unless otherwise noted) Parameter Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Input leakage current 2 Symbol VDD V0 VIH VIL VOH VOL IIH IIL Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. 1.0 1.5 Max. 5.5 30 0.2 VDD +0.4 +1 -1 1.5 2.0 5 2.0 8.0 1.0 Unit V V V V V V A A D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins, VI = VSS V0 = +30.0V V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 VDD pin, Note 3 V0 pin, Note 4 Y1 - Y160 pins, V O N = 0.5V Condition
Output resistance Stand-by current Consumed current (1) (Deselection) Consumed current (2) (Selection) Consumed current Note:
RON ISB IDD1 IDD2 I0
k A mA mA mA
1. VDD = +5.0V, V0 = +30V, VI = VSS 2. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load, EI = VDD The input data is turned over by the data taking clock (4-bit parallel input mode) 3. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load. EI = VSS The input data is turned over by the data taking clock (4-bit parallel input mode) 4. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load The input data is turned over by the data taking clock (4-bit parallel-input mode)
19
NT7701
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85C, unless otherwise noted) Parameter Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Input leakage current 2 Symbol VDD V0 VIH VIL VOH VOL IIH IIL Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. 1.0 1.5 Max. 5.5 30 0.2 VDD +0.4 +10.0 -10.0 1.5 2.0 50 80 160 Unit V V V V V V A A D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 6, LP, L/R, FR, MD, S/C and DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2 and DISPOFF pins, VI = VSS V0 = +30.0V V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 V0 pin, Note 2 Y1 - Y160 pins, V O N = 0.5V Condition
Output resistance Stand-by current Consumed current (1) Consumed current (2) Note:
RON ISB IDD I0
k A A A
1. VDD = +5.0V, V0 = +30V, fLP = 0 - 41.6kHz 2. VDD = +5.0V, V0 = +30V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load
20
NT7701
AC Characteristics Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30, and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock rise time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Note 1. Take the cascade connection into consideration. 2. (Tck - tWCKII - twckl)/2 is the maximum in the case of high speed operation. Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 21 100 1.2 Min. 71 23 23 10 20 23 0 25 25 25 Typ. 40 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
21
NT7701
Segment Mode 2 (VSS = V5 = 0V, VDD = 2.5 - 4.5V, V0 = 15 to 30, and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Note 1. Take the cascade connection into consideration. 2. (tCK - tWCKII - tWCKL)/2 is the maximum in the case of high speed operation. Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 36 100 1.2 Min. 125 51 51 30 40 51 0 51 51 51 Typ. 78 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 11ns, Note 1
22
NT7701
Timing waveform of the Segment Mode
tWLPH
LP
tLD tLS
tSL
tLH tWCKH
tWCKL
XCK
tr
tr tWCK
tDS
tDH
D0 - D7
LAST DATA
TOP DATA
tWDL
tSD
DISPOFF
LP XCK EI
tD 1 tS 2 n
EO
n: 4-bit parallel mode 40 8-bit parallel mode 20
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y160
23
NT7701
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Data setup time Data hole time Input signal rise time Input signal fall time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWLP tWLPH tSU tH tr tf tSD tWDL tDL tpd1, tpd2 tpd3 100 1.2 Min. 250 15 30 30 50 Typ. Max. 50 50 200 1.2 1.2 Unit ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Condition tr, tf 20ns VDD = +5.0V 10% VDD = +2.5 - +4.5V
24
NT7701
Timing Characteristics of Common Mode
tWLP
LP
tr
tWLPH tSU
tf tH
EIO2 (D7)
tDL
EIO1
tWDL tSD
DISPOFF
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y160 L/R = "L"
25
NT7701
Application Circuit (for reference only)
SEG640 SEG639
Y1~Y160
FR LP DISPOFF XCK
EIO1 MD S/C L/R D0~D7 EIO2 EIO1 MD FR LP DISPOFF S/C L/R D0~D7 EIO2 EIO1 MD FR LP DISPOFF XCK S/C L/R D0~D7 EIO2 EIO1 MD FR LP DISPOFF XCK S/C L/R D0~D7 EIO2
Y1~Y160
640*480 DOT MATRIX LCD PANEL
XCK
Y1~Y160
Y1~Y160
SEG3 SEG2 SEG1 C O M 4 7 9 C O M 4 8 0
C O M 1
C O M 2
C O M 3
Y1~Y160
Y1~Y160
XCK
XCK
Y1~Y160
DISPOFF
DISPOFF
NT7701*3
D0~D7
D0~D7
D0~D7
EIO1
EIO2
EIO1
EIO2
EIO1
DISPOFF
EIO2
S/C
S/C
S/C
L/R
L/R
L/R
MD
MD
MD
XCK
LP
LP
FR
FR
FR
LP
50~100
(case of 1/n bias)
DISPOFF
XCK
YD
FR
LP
R
R
(n-4)R
R
R
LCD controller
VEE
V0
V1
V2
V3
V4
V5
VDD
VSS
26
XD0~XD7
NT7701*4
/8
/5 /5
/8
NT7701
Bonding Diagram
7664um
199 200 54 53
Y
NT7701
(0,0)
ALK_L
X
ALK_R
986um
216 1 36
37
Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Designation LR LR VDD VDD SC SC EIO2 EIO2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 XCK XCK DISPOFF DISPOFF LP LP X -3600 -3440 -3280 -3120 -2000 -1840 -1680 -1520 -1360 -1200 -1040 -880 -720 -560 -400 -240 -80 80 240 400 560 720 880 1040 1200 1360 1520 1680 1840 2000 Y -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Designation EIO1 EIO1 FR FR MD MD GND GND V5R V5R V43R V43R V12R V12R V0R V0R Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 X 2160 2320 2480 2640 2800 2960 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3779 3635 3575 3525 3475 3425 3375 3325 Y -440 -440 -440 -440 -440 -440 -410 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 410 440 440 440 440 440 440 440
27
NT7701
Pad Location (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 X 3275 3225 3175 3125 3075 3025 2975 2925 2875 2825 2775 2725 2675 2625 2575 2525 2475 2425 2375 2325 2275 2225 2175 2125 2075 2025 1975 1925 1875 1825 1775 1725 1675 1625 1575 1525 1475 1425 1375 1325 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 X 1275 1225 1175 1125 1075 1025 975 925 875 825 775 725 675 625 575 525 475 425 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -225 -275 -325 -375 -425 -475 -525 -575 -625 -675 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440
28
NT7701
Pad Location (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Designation Y95 Y96 Y97 Y98 Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 X -725 -775 -825 -875 -925 -975 -1025 -1075 -1125 -1175 -1225 -1275 -1325 -1375 -1425 -1475 -1525 -1575 -1625 -1675 -1725 -1775 -1825 -1875 -1925 -1975 -2025 -2075 -2125 -2175 -2225 -2275 -2325 -2375 -2425 -2475 -2525 -2575 -2625 -2675 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 Pad No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 Designation Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 V0L V0L V12L V12L V43L V43L V5L V5L GND GND ALK_L ALK_R X -2725 -2775 -2825 -2875 -2925 -2975 -3025 -3075 -3125 -3175 -3225 -3275 -3325 -3375 -3425 -3475 -3525 -3575 -3635 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3779 -3438 3438 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 410 350 300 250 200 150 100 50 0 -50 -100 -150 -200 -250 -300 -350 -410 -323 -323
29
NT7701
Dummy Pad Location (Total: 10 pin)
NO 0 1 2 X -2960 -2800 -2640 Y -440 -440 -440 NO 3 4 5 X -2480 -2320 -2160 Y -440 -440 -440 NO 6 7 8 X 3120 3280 3440 Y -440 -440 -440 NO 9 X 3600 Y -440
30
NT7701
Package Information
A1 A2 n3 n2 m3 D3 m3 n2A n2B D1 n2 15x n2x J fef f e f D3 m3 C1 n3 C2 B D2 37x m1x B H m1 n1 H m3 n3 C1 D3 m2 m2 m2 n2A n2B n2A m2 r m2 n2 15x n2x J D1 D3 144x m2x D1 n3 m3 D3 D3 A1 A2
C1
n3
C2 m3
n3
C1
NT7701
n2B m2
Chip Outline Dimensions
Symbol A1 A2 B C1 C2 D1 D2 D3 m1 m2 m3 Dimensions in m 197 53 232 83 53 50 160 60 54 32 52 Symbol n1 n2 n2A n2B n3 r e f H J Dimensions in m 56 67 35 32 60 35 24 23 120 202
unit: m
31
NT7701
TCP Pin Layout
DUMMY DUMMY Y1 Y2 Y3 Y5 Y4 Y6 31 32 33 34 35 36
DUMMY 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V0R V12R V43R V5R VSS TEST2 TEST1 MD FR EIO1 LP DISPOFF XCK D7 D6 D5 D4 D3 D2 D1 D0 EIO2 S/C VDD L/R VSS V5L V43L V12L V0L DUMMY
Y78 Y79 Y80 Y81 Y82 Y83
108 109 110 111 112 113
Y155 Y156 Y157 Y158 Y159 Y160 DUMMY DUMMY
185 186 187 188 189 190
(COPPER SIDE VIEW)
NT7701
32
NT7701
External view of TCP pins
33
NT7701
Cautions concerning storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere. 2. Storage conditions : Storage state Storage conditions Temperature: 5 to 30; humidity: 80%RH or less unopened (less than 90 days) 3. 4. 5. 6. After seal of broken (less than 30 days) Room temperature, dry nitrogen atmosphere Don't store in a location exposed to corrosive gas or excessive dust. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. Don't store the product such that it is subjected to an excessive load weight, such as by stacking. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use.
34
NT7701
Tray Information
f
Y
e
c
X
X
W1
W2
T2 T1
d
Y
g h
W1 W2 a g h T2 T1 b e f
SECTION X-X
Symbol a b c d e f
Dimensions in mm 1.46 2.04 8.16 9.50 1.60 1.40
Symbol g h W1 W2 T1 T2
SECTION Y-Y
7*33
Dimensions in mm 0.84 4.20 76.0 68.0 71.0 68.3
35
NT7701
Ordering Information
Part No. NT7701H-BDT NT7701H-TABF3 Package Au bump on chip tray TCP Form
36
NT7701
Product Spec. Change Notice
NT7701 Specification Revision History Version 2.0 1.0 Content Chip size modified ( Due to scribe-line modified, change 7720m x 1030m to 7664m x 986m , Page 27 ) Gold bump size modified ( Page 31 ) Formal version release Date Jul. 2002 Oct. 2000
37

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