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| INTEGRATED CIRCUITS PR31700 32-bit RISC microprocessor Preliminary specification Supersedes data of 1997 Dec 15 1998 May 13 Philips Semiconductors Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 GENERAL DESCRIPTION The PR31700 is a single-chip digital ASSP (Application Specific Stand Product) used in HPCs (Handheld Personal Computers), Palm-size PCs, Screenphones, Smartphones, and other vertical market applications in the mobile computing and communication markets. The PR31700 consists of system support logic, integrated with the PR3901 Processor Core designed by Philips Semiconductors. * Built-in peripheral circuit - Clock generator with built-in eightfold-frequency phase-locked loop (PLL) - Four-stage write buffer - A high performance and flexible Bus Interface Unit - Multiple DMA channels - Memory controller for DRAM, HDRAM, SDRAM, SRAM, ROM, Flash Memory and PCMCIA - Power management unit - Big / Little endian FEATURES * R3000A-based PR3901 Processor Core - RISC architecture developed by MIPS Technologies, Inc. - Philips has added its own multiply-add and branch-likely instructions. - A single-cycle multiply/accumulate module to allow integrated DSP functions, such as a software modem for high-performance standard data and fax protocols - Instruction cache: 4K bytes; data cache: 1K bytes - On-chip Translation Lookaside Buffer (TLB) with 3264-bit wide entries, each of which maps 4KByte page Max 75MHz operation * Low power dissipation - 3.3V operation - Standby Current 10A(typ) - CPU clock stop mode - Power down modes for individual internal peripheral modules * Plastic LQFP 208-pin package The information contained herein is subject to change without notice. Philips is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing Philips products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a Philips product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that Philips products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the Philips Semiconductor Reliability Handbook The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by Philips for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Philips or others. R3000A is a trademark of MIPS Technologies, Inc. 1998 May 13 2 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 SYSTEM CONFIGURATION 1-2 PCMCIA SLOTS 32KHZ 3.3V REAL-TIME CLOCK PCMCIA/ROM/I/F TIMERS SYSCLK I-CACHE/ RAM TLB DRAM/SDRAM INTERFACE PR3901 RISC CPU CORE PR31700 1-64 MBYTES ROM 32-BIT BUS INTERFACE SERIAL I/F (208-PIN PQFP) RAM LCD IR 1-32 MBYTES(S) DRAM ISDN OR OTHER PERIPHERALS HIGH SPEED SERIAL PORT I-CACHE/ LCD ID ROM POWER SUPPLY AC ADAPTER MAIN BACKUP (LITHIUM) THERMISTOR T TOUCHSCREEN (RESISTIVE) 3.3V BETTY UCB1200 (ANALOG ASIC) 44-PIN QFP PHONE JACK DAA OR DAA SN00183 Figure 1. System Block Diagram 1998 May 13 3 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 DATA ICACHE 4 KBYTE ADDR BUS INTERFACE UNIT (BIU) MODULE DATA (S) DRAM/PCMCIA/ROM PR3901 RISC CUP CORE ADDR DATA TO MEMORY ADDR DATA DCACHE 1 KBYTE MAC ADDR CONTROL R3901 PROCESSOR CORE SYSTEM INTERFACE UNIT (SIU) MODULE ARBITRATION/ DMA/ADR DECODE DATA TO BETTY SIB MODULE CHI MODULE TO HIGH SPEED SERIAL ADDR TO LCD VIDEO MODULE IR MODULE TO IR UART MODULE (DUAL UART) TO GENERAL PURPOSE I/O IO MODULE SPI MODULE TO UART TO POWER SUPPLY 32 KHZ TIMER MODULE (+ RTC) POWER MODULE SYSCLK CLOCK MODULE INTERRUPT MODULE SYSTEM INTERFACE MODULE (SIM) SN00184 Figure 2. PR31700 Block Diagram 1998 May 13 4 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 MEMORY CONNECTIONS BANK0 PR31700 D[31] PIN NO. 133 D[31] CAS1* D[24] D[23] 145 D[24] 146 D[23] CAS0* CASHI* CASLO* DATA D(15:0) 16BIT DRAM D[16] D[15] 159 D[16] 27D[16] RASO* WE* A(12:0) RAS* WE* ADDR D[8] D[7] 16 D[8] 14 D[7] D[0] 2 D[0] BANK1 CAS3* CAS HI* CAS MH* CAS ML* CAS LO* DATA D(31:0) 32BIT CAS3* CAS2* CAS1* CAS0* RAS0* 195 CAS3* CAS2* 197 CAS2* CAS1* 198 CAS1* 199 CAS0* 194 RAS0* RAS0* RAS* WE* ADDR CAS0* WE* A[12:0] 169 WE* A[12:0] WE* A(12:0) BIG ENDIAN SN00185 Figure 3. Memory Connections 1998 May 13 5 AAAAAAA A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAA A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAA AAAAAAAAAAAAAAAAAAAAAA AAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAA AAAAAAAAAAAAAAAAAAAAAA AAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A AA PIN ASSIGNMENTS 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor NO. 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 I/O I/O I/OAAAAAAA MIOX[1] I/O I/O I/O I/O I/O I/O I/O I/O I/OAAAAAAA D[7] I/O I/O I/O I/O I/O I/O I/O I/O O O O I I SIBSYNC SIBSCLK VSS SIBMCLK VDD VDD NC VSS NC RSRV1 ENDIAN VDD D[15] D[14] VSS D[13] D[12] VDD D[11] VSS D[10] D[9] VDD D[8] VSS VSS D[6] D[5] VDD D[4] VSS D[3] VDD D[2] D[1] VSS D[0] VDD SIGNAL NAME NO. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O I I I I I I I I I I I I C32KOUT C32KlN VDD BC32K VCC3 VSS TESTAIU VIDDONE TESTIN TESTCPU VDD SPIOUT SPIIN SPICLK VSS IO[2] IO[3] RXPWR CARDET VDD VSS IROUT IRIN NC IO[4] TXD RXD VDD CHIDOUT CHIDIN CHIFS CHICLK VSS IO[5] IO[6] MIOX[0] SIBIRQ VDD SIBDOUT SIBDIN SIGNAL NAME 6 NO. 120 109 108 107 106 105 104 103 102 101 100 119 118 117 116 115 114 113 112 110 111 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/O I/O I/O O O O O O O O O O O O O O O O O O O O I I I I I I I MCS31 VSS VSS VSS CP DF VSS NC VSS VDD IO[0] VDD IO[1] VDD LOAD VDD PON1 CARD1CSH* CARD1CSL* CARDDIR* VDD (PLL) VSS (PLL) VDAT[3] VDAT[2] VDAT[1] VDAT[0] FRAME DISPON CPURES* ONBUTN PWROK PWRlNT PWRCS CARDREG* CARD2CSL* CARDIORD* CARD2CSH* CARD1WAIT* CARDIOWR* CARD2WAIT8 SIGNAL NAME Preliminary specification PR31700 AAAAAAA A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAAAAA A A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAA AAAAAAAAAAAAAAAAAAAAAA AAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A AA PIN ASSIGNMENTS (Continued) 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor NO. 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 I/O I/O I/O I/O I/O I/OAAAAAAA D[21] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O - - - - - - - - - - - - - - - - I VDD D[16] VSS D[17] VDD D[18] VSS D[19] D[20] VDD VSS D[22] VDD D[23] D[24] VDD D[25] VSS D[26] VSS D[27] D[28] VDD D[29] VSS D[30] D[31] VDD VSS VSS SYSCLKOUT SYSCLKIN VDD CS12 CS22 CS32 MCS02 MCS12 MCS22 SIGNAL NAME NO. 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O - - - - - - - - - - - - - - I VSS CAS08 (CAS3*) CAS1* (CAS28) CAS2* (CAS1*) VDD CAS3* (CAS0*) RAS0* RAS18 DCS0* VSS VSS A[0] A[1] VDD A[2] A[3] VSS A[4] VDD A[5] A[6] VSS A[7] A[8] VDD A[9] A[10] VSS A[11] A[12] VDD WE* ALE DREQ* DGRNT* VDD VSS RD* CS0* NC SIGNAL NAME 7 NO. 208 207 206 205 204 203 202 201 I/O O O O O I SIGNAL NAME DCLKOUT DCLKIN Preliminary specification DQMH DCKE VDD VDD VSS DQML PR31700 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 PIN FUNCTIONS NAME Memory Pins D(31:0) I/O These pins are the data bus for the system. 8-bit SDRAMs should be connected to bits 7:0 and 16-bit SDRAMs and DRAMs should be connected to bits 15:0. All other 16-bit ports should be connected to bits 31:16. Of course, 32-bit ports should be connected to bits 31:0. These pins are normally outputs and only become inputs during reads, thus no resistors are required since the bus will only float for a short period of time during bus turn-around. These pins are the address bus for the system. The address lines are multiplexed and can be connected directly to SDRAM and DRAM devices. To generate the full 26-bit address for static devices, an external latch must be used to latch the signals using the ALE signal. For static devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly connected from PR31700's address bus) are held afterward by PR31700 processor for the remainder of the address bus cycle. This pin is used as the address latch enable to latch A(12:0) using an external latch, for generating the upper address bits 25:13. This pin is used as the read signal for static devices. This signal is asserted for reads from /MCS3*-0*, /CS3*-0*, /CARD2CS* and /CARD1CS* for memory and attribute space, and for reads from PR31700 processor accesses if SHOWPOSEIDON is enabled (for debugging purposes). This pin is used as the write signal for the system. This signal is asserted for writes to /MCS3*-0*, /CS3*-0*, /CARD2CS* and /CARD1CS* for memory and attribute space, and for writes to DRAM and SDRAM. This pin is used as the CAS signal for SDRAMs, the CAS signal for D(7:0) for DRAMs, and the write enable signal for D(7:0) for static devices. This pin is used as the CAS signal for D(15:8) for DRAMs and the write enable signal for D(15:8) for static devices. This pin is used as the CAS signal for D(23:16) for DRAMs and the write enable signal for D(23:16) for static devices. This pin is used as the CAS signal for D(31:24) for DRAMs and the write enable signal for D(31:24) for static devices. This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs. This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1 DRAMs. This pin is used as the chip select signal for Bank0 SDRAMs. This pin is used as the clock enable for SDRAMs. This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data input when reading from SDRAM and DRAM devices. This pin is the (nominal) 73.728 MHz clock for the SDRAMs. This pin is the upper data mask for a 16-bit SDRAM configuration. This pin is the lower data mask for a 16-bit SDRAM or 8-bit SDRAM configuration. These pins are the Chip Select 3 through 0 signals. They can be configured to support either 32-bit or 16-bit ports. These pins are the Memory Card Chip Select 3 through 0 signals. They only support 16-bit ports. These pins are the Chip Select signals for PCMCIA card slot 2. These pins are the Chip Select signals for PCMCIA card slot 1. This pin is the /REG* signal for the PCMCIA cards. This pin is the /IORD* signal for the PCMCIA IO cards. This pin is the /IOWR* signal for the PCMCIA IO cards. This pin is used to provide the direction control for bi-directional data buffers used for the PCMCIA slot(s). This signal will assert whenever /CARD2CSH* or /CARD2CSL* or /CARD1CSH* or /CARD1CSL* is asserted and a read transaction is taking place. This pin is the card wait signal from PCMCIA card slot 2. This pin is the card wait signal from PCMCIA card slot 1. I/O FUNCTIONS A(12:0) O ALE RD* O O WE* CAS0* (/WE0)* CAS* (/WE1)* CAS2* (/WE2)* CAS3* (/WE3)* RAS0* RAS1* (/DCS1)* DCS0* DCKE DCLKIN DCLKOUT DQMH DQML CS3-0* MCS3-0* CARD2CSH*,L* /CARD1CSH*,L* CARDREG* CARDIORD* CARDIOWR* CARDDIR* O O O O O O O O O I O O O O O O O O O O O CARD2WAIT* CARD1WAIT* *Active-low signal I I 1998 May 13 8 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 NAME Bus Arbitration Pins DREQ* I/O FUNCTIONS I This pin is used to request external arbitration. If the TESTSIU signal is high and the TESTSIU function has been enabled, then once /DGRNT* is asserted, external logic can initiate reads or writes to PR31700 processor registers by driving the appropriate input signals. If the TESTSIU signal is low or the TESTSIU function has not been enabled, then PR31700 memory transactions are halted and certain memory signals will be tri-stated when /DGRNT* is asserted in order to allow an external master to access memory. This pin is asserted in response to /DREQ* to inform the external test logic or bus master that it can now begin to drive signals. DGRNT* *Active-low signal NAME Clock Pins SYSCLKIN SYSCLKOUT C32KIN C32KOUT BC32K O I/O FUNCTIONS I O I O O This pin should be connected along with SYSCLKOUT to an external crystal which is the main PR31700 clock source. This pin should be connected along with SYSCLKIN to an external crystal which is the main PR31700 clock source. This pin along with C32KOUT should be connected to a 32.768 KHz crystal. This pin along with C32KIN should be connected to a 32.768 KHz crystal. This pin is a buffered output of the 32.768 KHz clock. NAME CHI Pins CHIFS I/O FUNCTIONS I/O This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes. As an output, this pin allows PR31700 to be the master CHI sync source. As an input, this pin allows an external peripheral to be the master CHI sync source and the PR31700 CHI module will slave to this external sync. This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output, this pin allows PR31700 to be the master CHI clock source. As an input, this pin allows an external peripheral to be the master CHI clock source and the PR31700 CHI module will slave to this external clock. This pin is the CHI serial data output signal. This pin is the CHI serial data input signal. CHICLK I/O CHIDOUT CHIDIN O I NAME IO Pins IO(6:0) I/O FUNCTIONS I/O These pins are general purpose input/output ports. Each port can be independently programmed as an input or output port. Each port can generate a separate positive and negative edge interrupt. Each port can also be independently programmed to use a 16 to 24 msec debouncer. These pins are multi-function input/output ports. Each port can be independently programmed as an input or output port, or can be programmed for multi-function use to support test signals (for debugging purposes only). Each port can generate a separate positive and negative edge interrupt. Note that 30 other multi-function pins are available for usage as multi-function input/output ports. These pins are named after their respective standard/normal function and are not listed here. MIO(1:0) I/O NAME Reset Pins /CPURES* I/O FUNCTIONS I This pin is used to reset the CPU core. This pin should be connected to a switch for initiating a reset in the event that a software problem might hang the CPU core. The pin should also be pulled up to VSTANDBY* through an external pull-up resistor. This pin serves as the Power On Reset signal for PR31700. This signal must remain low when VSTANDBY is asserted until VSTANDBY[ is stable. Once VSTANDBY is asserted, this signal should never go low unless all power is lost in the system. /PON* I [VSTANDBY--This signal provides power for the PR31700 and other components in the system that must never lose power. This signal should always be asserted if there is eithr a good Main Backup Battery, or if a Battery Charger is plugged in. 1998 May 13 9 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 NAME Power Supply Pins ONBUTN I/O FUNCTIONS I This pin is used as the On Button for the system. Asserting this signal will cause PWRCS to set to indicate to the System Power Supply to turn power on to the system. PWRCS will not assert if the PWROK signal is low. This pin is used as the chip select for the System Power Supply. When the system is off, the assertion of this signal will cause the System Power Supply to turn VCCDRAM[[ and VCC3 on to power up the system. The Power Supply will latch SPI commands on the falling edge of PWRCS. This pin provides a status from the System Power Supply that there is a good source of power in the system. This signal typically will be asserted if there is a Battery Charger supplying current or if the Main Battery is good and the Battery Door is closed. If PWROK is low when the system is powered off, PWRCS will not assert as a result of the user pressing the ONBUTN or an interrupt attempting to wake up the system. If the device is on when the PWROK signal goes low, the software will immediately shut down the system since power is about to be lost. When PWROK goes low, there must be ample warning so that the software can shut down the system before power is actually lost. This pin is used by the System Power Supply to alert the software that some status has changed in the System Power Supply and the software should read the status from the System Power Supply to find out what has changed. These will be low priority events, unlike the PWROK status, which is a high priority emergency case. This pin provides the status of the power supply for the ROM, UCB1200, system buffers, and other transient components in the system. This signal will be asserted by the System Power Supply when PWRCS is asserted, and will always be turned off when the system is powered down. PWRCS O PWROK I PWRINT I VCC3 I [[VCCDRAM: This signal provides power for the DRAM and/or SDRAM. The supply must be off when VSTANDBY is first asserted, andremain off until the system is powered up by the assertion of PWRCS. When the software subsequently powers down the system it may choose to keep this supply on to preserve the contents of memory. NAME SIB Pins SIBDIN SIBDOUT SIBSCLK SIBSYNC I O O O This pin contains the input data shifted from UCB1200 and/or external codec device. This pin contains the output data shifted to UCB1200 and/or external codec device. This pin is the serial clock sent to UCB1200 and/or external codec device. The programmable SIBSCLK rate is derived by dividing down from SIBMCLK. This pin is the frame synchronization signal sent to UCB1200 and/or external codec device. This frame sync is asserted for one clock cycle immediately before each frame starts and all devices connected to the SIB monitor SIBSYNC to determine when they should transmit or receive data. This pin is a general purpose input port used for the SIB interrupt source from UCB1200. This interrupt source can be configured to generate an interrupt on either a positive and/or negative edge. This pin is the master clock source for the SIB logic. This pin is available for use in one of two modes. First, SIBMCLK can be configured as a high-rate output master clock source required by certain external codec devices. In this mode all SIB clocks are synchronously slaved to the main PR31700 system clock CLK2X. Conversely, SIBMCLK can be configured as an input slave clock source. In this mode, all SIB clocks are derived from an external SIBMCLK oscillator source, which is asynchronous with respect to CLK2X. Also, for this mode, SIBMCLK can still be optionally used as a high-rate master clock source required by certain external codec devices. I/O FUNCTIONS SIBIRQ SIBMCLK I I/O NAME SPI Pins SPICLK SPIOUT SPIIN I/O FUNCTIONS O O I This pin is used to clock data in and out of the SPI slave device. This pin contains the data that is shifted into the SPI slave device. This pin contains the data that is shifted out of the SPI slave device. NAME UART and IR Pins TXD RXD 1998 May 13 I/O FUNCTIONS O I This pin is the UART transmit signal from the UART A module. This pin is the UART receive signal to the UART A module. 10 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 NAME IROUT IRIN RXPWR CARDET I/O O I O I FUNCTIONS This pin is the UART transmit signal from the UART B module or the Consumer IR output signal if Consumer IR mode is enabled. This pin is the UART receive signal to the UART B module. This pin is the receiver power output control signal to the external communication IR analog circuitry. This pin is the carrier detect input signal from the external communication IR analog circuitry. NAME Video Pins FRAME I/O FUNCTIONS O This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to return it's pointers to the top of the display. The Video Module asserts FRAME after all the lines of the LCD have been shifted and transferred, producing a full frame of display. This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected to a DC voltage, the DF signal is used by the LCD to alternate the polarity of the row and column voltages used to turn the pixels on and off. The DF signal can be configured to toggle on every frame or can be configured to toggle every programmable number of LOAD signals. This pin is the line synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to transfer the contents of it's horizontal line shift register to the LCD panel for display. The Video Module asserts LOAD after an entire horizontal line of data has been shifted into the LCD. This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of CP and sampled by the LCD on the falling edge of CP. These pins are the data for the LCD. These signals are directly connected to the LCD for 4-bit non-split displays. For 4-bit split and 8-bit non-split displays, an external register is required to demultiplex the 4-bit data into the desired 8 parallel data lines needed for the LCD. This pin is the display-on enable signal for the LCD. This pin is used to externally synchronize events to periods whenthe vido is not shifting. DF O LOAD O CP VDAT(3:0) O O DISPON VIDDONE O O NAME Endian Pin ENDIAN I/O FUNCTIONS I This pin is used to select the endianess of the PR31700. The "1" level input sets the endianess to the big endian, while the "0" level input tot he little endian. NAME Test Pins TESTSIU I/O FUNCTIONS I This pin allows external logic to initiate read or write transactions to PR31700 registers. The TESTSIU mode is enabled by toggling this signal after the device has powered up. Once the function is enabled, if the TESTSIU pin is high when the bus is arbitrated (using /DREQ and /DGRNT), then external logic can initiate read and write transactions to PR31700 registers. This pin is used for debugging purposes only. This pin allows numerous internal CPU core signals to be brought to external PR31700 pins, in place of the normal signals assigned to these pins. The CPU core signals assigned to their respective pins during TESTCPU mode are vendor-dependent. The TESTCPU mode is enabled by asserting this TESTCPU signal, and this function is provided for generating test vectors for the CPU core. This pin is used for debugging purposes only. This pin is reserved for vendor-dependent use. This pin is used for debugging purposes only. This signal is used to synchronize UCB1200 to read touchscreen input, when there is no video data shifted into LCD panel. TESTCPU I TESTIN VIDDONE I O NAME Spare Pins NC5-1 RSRV1 I/O FUNCTIONS No Connect I These pins are reserved for future use and should be left unconnected. These pins are reserved for future use and should be connected to ground. 1998 May 13 11 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 NAME Power Supply Pins VDD (33 each) VSS (33 each) I/O FUNCTIONS V G These pins are the power pins for PR31700 and should be connected to the digital +3.3V power supply VSTANDBY. These pins are the ground pins for PR31700 and should be connected to digital ground. NOTE: For some vendor-dependent implementations of PR31700, pin 131 may be used for a filter capacitor for the SYSCLK oscillator (capacitor connected between pin 131 and digital ground). This pin is the analog power pin for the PR31700. Keep away from other VDD. This pin is the analog ground pin for the PR31700. Keep away from other VSS. Vdd (for PLL) VSS (for PLL) V G 1998 May 13 12 AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Table 1. PR31700 Standard and Multi-Function Pin Usage This section contains tables summarizing various aspects of the pin usage for the PR31700. Table 1 lists the standard versus multi-function usage for each PR31700 pin, if applicable. Those signal names shown in parentheses are test signals for debugging purposes only. The column showing the multi-function select signal FRAME DF LOAD CP VDAT[0] VDAT[1] VDAT[2] VDAT[3] BC32K C32KOUT C32KlN SYSCLKOUT SYSCLKIN DGRNT* DREQ* DQML DQMH DCLKOUT DCLKIN DCKE DCS0* RAS1* (DCS1*) RAS0* CAS3* (WE3*) CAS2* (WE2*) CAS1* (WE1*) CAS0* (WE0*) WE* RD* ALE A[12:0] D[31:0] PR31700 pin FRAME (O) DF (O) LOAD (O) CP (O) VDAT[0] (O) VDAT[1] (O) VDAT[2] (O) VDAT[3] (O) BC32K(O) C32KOUT (O) C32KIN (I) SYSCLKOUT (O) SYSCLKIN (I) DGRNT* (O) DREQ* (I) DQML (O) DQMH (O) DCLKOUT (O) DCLKIN (I) DCKE (O) DCS0* (O) RAS1* (O) RAS0* (O) CAS3* (O) CAS2* (O) CAS1* (O) CAS0* (O) WE* (O) RD* (O) ALE (O) A[12:0] (I/O) D[31:0] (I/O) Standard Function (I = input, O = output) Multi-function (IRQHIGH) (IRQLow) MIO[25] MIO[26] MIO[27] (BERR) Multi-function select (Reset State: 1 = multi-function mode selected; 0 = standard function & mode selected) MIOSEL[25] (1) MIOSEL[26] (0) MIOSEL[27] (0) IRQTEST (0) IRQTEST (0) IRQTEST (0) Bus Arb State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1998 May 13 PIN USAGE INFORMATION Philips Semiconductors 32-bit RISC microprocessor 13 and reset state indicates the internal control signal used to select the multi-function mode, as well as the default configuration of each multi-function pin during reset. The "Bus Arb State" column shows which pins are tri-stated whenever the DGRNT* signal is asserted in response to a DREQ*(external bus arbitration request). Preliminary specification PR31700 AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA Table 1. PR31700 Standard and Multi-Function Pin Usage (Continued) SIBMCLK SIBDIN SIBDOUT SIBSYNC SPIIN SPIOUT SPICLK IO0 IO1 IO2 IO3 IO4 IO5 IO6 VCC3 CHIDIN CHIDOUT CHICLK CHIFS MCS3* MCS2* MCS1* MCS0* CS3* CS2* CS1* CS0* RXD TXD PON* CPURES* ONBUTN PWROK PWRINT PWRCS DISPON 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor PR31700 pin SIBMCLK (I/O) SIBDIN (I) SIBDOUT (O) SIBSYNC (O) SPIIN (I) SPIOUT (O) SPICLK (O) IO0 (I/O) IO1 (I/O) IO2 (I/O) IO3 (I/O) IO4 (I/O) IO5 (I/O) IO6 (I/O) VCC3 (I) CHIDIN (I) CHIDOUT (O) CHICLK (I/O) CHIFS (I/O) MCS3* (O) MCS2* (O) MCS1* (O) MCS0* (O) CS3* (O) CS2* (O) CS1* (O) CS0* (O) RXD (I) TXD (O) PON* (I) CPURES* (I) ONBUTN (I) PWROK (I) PWRINT (I) PWRCS (O) DISPON (O) Standard Function (I = input, O = output) 14 Multi-function MIO[12] MIO[13] MIO[14] MIO[15] MIO[28] MIO[29] MIO[30] MIO[31] MIO[16] MIO[17] MIO[18] MIO[19] MIO[20] MIO[21] MIO[22] MIO[23] MIO[24] Multi-function select (Reset State: 1 = multi-function mode selected; 0 = standard function & mode selected) MIOSEL[12] (0) MIOSEL[13] (0) MIOSEL[14] (0) MIOSEL[15] (0) MIOSEL[28] (1) MIOSEL[29] (1) MIOSEL[30] (1) MIOSEL[31] (1) MIOSEL[16] (1) MIOSEL[17] (1) MIOSEL[18] (1) MIOSEL[19] (1) MIOSEL[20] (0) MIOSEL[21] (0) MIOSEL[22] (0) MIOSEL[23] (0) MIOSEL[24] (0) Preliminary specification PR31700 Bus Arb State Hi-Z AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA Table 1. PR31700 Standard and Multi-Function Pin Usage (Continued) VSS-34 pins VDD-34 pins RSRV1 NC[5:1] ENDIAN MIOX[0] MIOX[1] CARDDIR* CARD2WAIT* CARD1WAIT* CARD2CSH* CARD2CSL* CARD1SCH* CARD1CSL* CARDIORD* CARDIOWR* CARDREG* VIDDONE TESTIN TESTCPU TESTAIU IRIN IROUT CARDET RXPWR SIBIRQ SIBSCLK 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor PR31700 pin GND + 3.3 V SPARE (I) SPARE ENDIAN (I) (INSFETCH*) (MASTER) CARDDIR* (O) CARD2WAIT* (I) CARD1WAIT* (I) CARD2CSH* (O) CARD2CSL* (O) CARD1CSH* (O) CARD1CSL* (O) CARDIORD* (O) CARDIOWR* (O) CARDREG*(O) (SHOWDINO / CS*) VIDDONE (O) TESTIN (I) TESTCPU (I) TESTAIU (I) IRIN (I) IROUT (O) CARDET (I) RXPWR (O) SIBIRQ (I) SIBSCLK (O) Standard Function (I = input, O = output) 15 Multi-function MIOX[0] MIOX[1] MIOX[2] MIO[10] MIO[11] MIO[3] MIO[4] MIO[5] MIO[6] MIO[7] MIO[8] MIO[9] Multi-function select (Reset State: 1 = multi-function mode selected; 0 = standard function & mode selected) MIOSEL[10] (1) MIOSEL[11] (1) MIOSEL[0] (1) MIOSEL[1] (1) MIOSEL[2] (1) MIOSEL[3] (1) MIOSEL[4] (1) MIOSEL[5] (1) MIOSEL[6] (1) MIOSEL[7] (1) MIOSEL[8] (1) MIOSEL[9] (1) Preliminary specification PR31700 Bus Arb State Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 Table 2 lists various power-down states and conditions for each PR31700 pin. The "Power-Down Control" column shows the conditions which trigger a power-down for each respective pin. This column also shows the reset state for each of these conditions. The "PON* state" column defines the state of each pin at power-on reset (PON*). This condition is defined as initial power up of the PR31700, whereby the PR31700 is initialized and the PR31700 pins are reset to the state shown in the table. This state is entered after power is applied for the very first time (VSTANDBY is turned on but VCC3 is still turned off). The "1st-time power-up state" column defines the state of each pin after power-up mode (RUNNING STATE) is executed for the first time. This mode is defined as VCC3 applied to the entire system and is initiated by the user pressing the ONBUTN while in the power-on reset (PON*) state. Note that the defined state of various pins for 1st-time power-up may depend on the configuration of external devices attached to these pins. After 1st-time power-up, the software could change the state of various pins to be different from those shown in the table. Thereafter, subsequent transitions from SLEEP STATE to RUNNING STATE might result in different states for these pins. The "power-down state" column defines the state of each pin during power-down mode (SLEEP STATE). This mode is defined as VCC3 turned off to the entire system, except for the PR31700 (RTC and interrupts alive) and any persistent memory. 1998 May 13 16 A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA Table 2. PR31700 Power-Down Pin Usage MBUSCLK PON* CPURES* ONBUTN PWROK PWRINT PWRCS DISPON FRAME DF LOAD CP VDAT[0] VDAT[1] VDAT[2] VDAT[3] BC32K C32KOUT C32KIN SYSCLKOUT SYSCLKIN DGRNT* DREQ* DQML DQMH DCLKOUT DCLKIN DCKE DCS0* RAS1* (DCS1*) RAS0* CAS3* (WE3*) CAS2* (WE2*) CAS1* (WE1*) CAS0* (WE0*) WE* RD* ALE A[12:0] D[31:0] 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor PR31700 pin MODULE DISABLE MODULE DISABLE MODULE DISABLE MODULE DISABLE MODULE DISABLE MODULE DISABLE MODULE DISABLE MODULE DISABLE MODULE DISABLE MODULE DISABLE POWERDOWN & MIOPD[25] (1) POWERDOWN POWERDOWN POWERDOWN & MIOPD[26] (0) POWERDOWN & MIOPD[27] (1) MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN POWERDOWN MEMPOWERDOWN MEMPOWERDOWN Power-Down Control powerdown = (vccon & vcc3)* (reset state) 17 PON* state Pull-Down Pull-Down Out Low OSC on OSC on OSC off OSC off Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low 1st time power-up state Out Low OSC on OSC on OSC on OSC on Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Hi Hi Hi In In Preliminary specification PR31700 power-down state Selectable Selectable Selectable Out Low OSC on OSC on OSC off OSC off Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low AAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA 1998 May 13 VIDDONE TESTIN TESTCPU TESTAIU IRIN IROUT CARDET RXPWR SIBIRQ SIBSCLK SIBMCLK SIBDIN SIBDOUT SIBSYNC SPIIN SPIOUT SPICLK IO0 IO1 IO2 IO3 IO4 IO5 IO6 VCC3 CHIDIN CHIDOUT CHICLK CHIFS MCS3* MCS2* MCS1* MCS0* CS3* CS2* CS1* CS0* RXD TXD MBUSINT Table 2. PR31700 Power-Down Pin Usage (Continued) Philips Semiconductors MBUSDATA 32-bit RISC microprocessor PR31700 pin MODULE DISABLE POWERDOWN POWERDOWN POWERDOWN POWERDOWN POWERDOWN POWERDOWN POWERDOWN & MIOPD[12] (1) POWERDOWN POWERDOWN POWERDOWN POWERDOWN & MIOPD[13] (1) POWERDOWN & MIOPD[14] (0) POWERDOWN & MIOPD[15] (0) POWERDOWN & IOPD[0] (1) POWERDOWN & IOPD[1] (1) POWERDOWN & IOPD[2] (1) POWERDOWN & IOPD[3] (1) POWERDOWN & IOPD[4] (1) POWERDOWN & IOPD[5] (1) POWERDOWN & IOPD[6] (1) POWERDOWN POWERDOWN & MIOPD[28] (1) POWERDOWN & MIOPD[29] (1) POWERDOWN & MIOPD[30] (1) POWERDOWN & MIOPD[31] (1) POWERDOWN & MIOPD[16] (0) POWERDOWN & MIOPD[17] (0) POWERDOWN & MIOPD[18] (0) POWERDOWN & MIOPD[19] (0) POWERDOWN & MIOPD[20] (1) POWERDOWN & MIOPD[21] (1) POWERDOWN & MIOPD[22] (1) POWERDOWN POWERDOWN & MIOPD[23] (1) POWERDOWN & MIOPD[24] (0) MODULE DISABLE Power-Down Control powerdown = (vccon & vcc3)* (reset state) 18 PON* state Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Out Low Low Low Low Low Low Low Low Low Low In In In In 1st time power-up state Out Low Low Low Low Low Low Low Low Low Low IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Hi Hi Hi Hi In Preliminary specification PR31700 power-down state Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Out Low Low Low Low Low Low Low A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA Table 2. PR31700 Power-Down Pin Usage (Continued) VSS-34 EACH VDD-34 EACH RSRV1 NC[5:1] ENDIAN MIOX[0] MIOX[1] CARDDIR* CARD2WAIT* CARD1WAIT* CARD2CSH* CARD2CSL* CARD1CSH* CARD1CSL* CARDIORD* CARDIOWR* CARDREG* 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor PR31700 pin POWERDOWN & MIOPD[0] (0) POWERDOWN & MIOPD[1] (0) POWERDOWN & MIOPD[2] (1) POWERDOWN & MIOPD[3] (1) POWERDOWN & MIOPD[4] (1) POWERDOWN & MIOPD[5] (1) POWERDOWN & MIOPD[6] (1) POWERDOWN & MIOPD[7] (1) POWERDOWN & MIOPD[8] (1) POWERDOWN & MIOPD[9] (1) POWERDOWN & MIOPD[10] (1) POWERDOWN & MIOPD[11] (1) Power-Down Control powerdown = (vccon & vcc3)* (reset state) 19 PON* state Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down IN IN 1st time power-up state IN IN IN IN IN IN IN IN IN IN IN IN Preliminary specification PR31700 power-down state Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Selectable Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 FUNCTION SPECIFICATIONS OUTLINE The PR31700 consists of system support logic, integrated with the PR3901 Processor Core designed by Philips. For details of the system support logic and the PR3901 Processor Core, refer to the PR31700 User's Manual. * Status register - Holds the operating mode status (user mode or kernel mode), interrupt masking status, diagnosis status and other such information. * BadVAddr (Bad Virtual Address) register - Holds the most recent virtual address for which a virtual address translation error occurred. PR3901 PROCESSOR CORE The PR3901 is a Philips-developed microprocessor core based on the R3000A RISC architecture developed by MIPS Technologies, Inc. INSTRUCTIONS All PR3901 Processor Core instructions are 32-bit instructions. Apart from some coprocessor instructions, the instructions are upwardly compatible with the R3000A. The PR3901 Processor Core instructions can be classified into six types. * Load and store instructions - Transfer data between memory and general-purpose registers. * PRId register - Shows the revision number of the PR3901 Processor Core. - Cache register - Controls the instruction cache (reserved) and the data cache auto-lock bits. * Debug register - Control software debug exception. * DEPC - Program counter for software debug exception. MEMORY MANAGEMENT The PR3901 Processor Core has a 4G-byte memory address space. The 4G-byte memory space consists of a 2G-byte user area and a 2G-byte kernel area. The kernel area contains a cache area and an uncache area.The PR3901 Processor Core provides a full-featured memory management unit (MMU) utilizing an on-chip Translation Lookaside Buffer (TLB). The on-chip TLB majur characteristics are : * 32 x 64-bit wide entries * Computational instructions - These include arithmetic, logical, shift, multiply, divide, and multiply-add instructions. The multiply-add instructions are extensions to the R3000A. The multiply instructions can also be used as three-operand instructions. * Special instructions - Used for system call or break point. * Jump and branch instructions - Change the control flow of a program. The Branch-Likely instruction is provided as an extension to the R3000A. * Coprocessor instructions - Perform operations for coprocessors. The R3000A LWCz and SWCz instructions are reserved instructions in the PR3901 Processor Core. Attempting execution generates a reserved instruction exception. Note that the COPz, CTCz and MTCz instructions are no-operation instructions, the CFCz and MFCz instructions load undefined data to general purpose registers (rt) in the PR31700. * fully associative * 2 entry micro TLB for instruction address translation * instruction address translation accesses full TL after micro-TLB miss * data address translation accesses full TLB PIPELINE The PR3901 Processor Core pipeline consists of five stages. The pipeline configuration enables the PR3901 Processor Core to execute nearly all instructions in one clock. CACHE The PR31700 incorporates a 4K-byte instruction cache and a 1K-byte data cache. The instruction cache is direct-mapped with a block size of 16 bytes. The data cache uses two-way set-associative mapping with a block size of four bytes. The data cache has a lock function that locks data in one direction. The write-through method is used to write data back to memory. DSP FUNCTION The PR3901 Processor Core has a high-speed multiplier/accumulator and supports 32-bit multiplier operations, with 64-bit accumulator in one cycle. * System control coprocessor instructions - Perform operations on the CP0 registers to manipulate the memory management and exception handling functions of the processor. REGISTERS The PR3901 Processor Core has following registers. * 32 general purpose registers (32-bit) * HI/LO registers - Hold the result of multiply and divide operation * PC (Program Counter) * Cause register - Indicates the nature of the most recent exception * EPC (Exception Program Counter) register - Holds the program counter at the time the exception occurred, indicating the address where processing is to resume after the exception processing is completed. 1998 May 13 20 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 PERIPHERAL FUNCTIONS CLOCK GENERATOR The PR31700 uses an internal PLL and an external crystal oscillator to generate a clock with eight times the input clock frequency. The PLL oscillation can be halted externally to reduce power dissipation. WRITE BUFFER The PR31700 incorporates a four-stage write buffer. BUS INTERFACE UNIT (BIU) MODULE The PR31700 has a Bus Interface Unit with the following features. * supports 2 Banks of SDRAM and/or DRAM / HDRAM - 8-bit or 16-bit SDRAM configuration - 16-bit or 32-bit DRAM configuration - 16-bit or 32-bit HDRAM configuration - 4 Mbit, 16 Mbit and 64 Mbit parts supported - page mode reads and writes supported - independent refresh counters for each bank - self refreshing parts supported to retain memory when system is powered down CONCENTRATION HIGHWAY INTERFACE (CHI) MODULE The PR31700 has a CHI Module with the following features. * high-speed serial Concentration Highway Interface (CHI) contains logic for interfacing to external full-duplex serial time-division-multiplexed (TDM) communication peripherals * supports * CHI ISDN line interface chips and other PCM/TDM serial devices interface is programmable (number of channels, frame rate, bit rate, etc.) to provide support for a variety of formats 4.096 Mbps for CHI receive and transmit * supports data rates up to * independent DMA support INTERRUPT MODULE The PR31700 has an Interrupt Module with the following features. * contains logic for individually enabling, reading, and clearing all PR31700 interrupt sources * interrupts generated from internal PR31700 modules or from edge transitions on external signal pins *4 general purpose chip selects (CS3*-CS0*) - 16-bit or 32-bit ports - programmable wait states - read page mode *4 general purpose chip selects (MCS3*-MCS0*) IO MODULE The PR31700 has an IO Module with the following features. * contains support for reading and writing the 7 bi-directional general purpose IO pins and the 32 bi-directional multi-function IO pins - 16-bit ports - programmable wait states - read page mode * each IO port can generate a separate positive and negative edge interrupt * independently *2 full PCMCIA slots configurable IO ports allow the PR31700 to support a flexible and wide range of system applications and configurations - 16-bit ports - IORD and IOWR provided to support I/O cards - WAIT signal supported SYSTEM INTERFACE UNIT (SIU) MODULE The PR31700 has a System Interface Unit with the following features. * multi-channel 32-bit DMA controller IR MODULE The PR31700 has an IR Module with the following features. * IR consumer mode - allows control of consumer electronic devices such as stereos, TVs, VCRs, etc. - programmable pulse parameters - external analog LED circuitry * independent DMA controller for video, SIB to/from BETTY audio/telecom codecs, high-speed serial port, IR, UART, and general purpose UART * IRDA communication mode - not compatible with General Magic Cap Devices - allows communication with other IRDA devices such as FAX machines, copiers, printers, etc. - supported by the UART module within the PR31700 - external analog receiver preamp and LED circuitry - data rate = up to 115 kbps at 1 meter * address decoding for the internal registers CLOCK MODULE The PR31700 has a Clock Module with the following features. * The PR31700 supports system-wide single crystal configuration, besides the 32 kHz RTC XTAL (reduces cost, power, and board space) * IR FSK communication mode - compatible with GeneraI Magic Cap Devices - supported by the UART module within the PR31700 - external analog IR chip(s) perform frequency modulation to generate the desired IR communication mode protocol - data rate = up to 36000 bps at 3 meters * common crystal rate divided to generate clock for CPU, video, sound, telecom, UARTs, etc. enabling or disabling of individual clocks under software control, for power management * independent * carrier detect state machine - periodically enables IR receiver to check if a valid carrier is present 1998 May 13 21 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 POWER MODULE The PR31700 has a Power Module with the following features. * power-down modes for individual internal peripheral modules TIMER MODULE The PR31700 has a Timer Module with the following features. * Real Time Clock (RTC) and Timer * serial (SPI port) power supply control interface supported * power management state machine has 3 states: RUNNING, DOZING and SLEEP SERIAL INTERCONNECT BUS (SIB) MODULE The PR31700 has a SIB Module with the following features. * The PR31700 contains holding and shift registers to support the serial interface to the UCB1200 ASIC and/or other optional codec devices * 40-bit * 40-bit * 16-bit counter (30.517 s granularity); maximum uninterrupted time = 388.36 days alarm register (30.517 s granularity) periodic timer (0.868 s granularity); maximum timeout = 56.8 ms on alarm, timer, and prior to RTC roll-over * interrupts * synchronous, frame-based protocol * The PR31700 always master source * each UART MODULE The PR31700 has a UART Module with the following features. * 2 independent full-duplex UARTs of clock and frame frequency and phase; programmable clock frequency SIB frame consists of 128 clock cycles, further divided into 2 subframes or words of 64 bits each (supports up to 2 devices simultaneously) DMA support for audio receive and transmit, telecom receive and transmit * programmable baud rate generator * UART A port used for serial control module interface to external IR * independent * UART B * UART A port used for general purpose serial control interface and UART B DMA support for receive and transmit * supports 8-bit or 16-bit mono telecom formats * supports 8-bit or 16-bit mono or stereo audio formats * independently programmable audio and telecom sample rates * CPU read/write registers for subframe control and status SERIAL PERIPHERAL INTERFACE (SPI) MODULE The PR31700 has an SPI Module with the following features. * provides interface to SPI peripherals and devices VIDEO MODULE The PR31700 has a Video Module with the following features. * bit-mapped graphics * supports monochrome, grey scale, or color modes * time-based dithering algorithm for gray scale and color modes * full-duplex, synchronous serial data transfers (data in, data out, and clock signals) supplies dedicated chip select and interrupt for an SPI interface serial power supply data word lengths for the SPI interface SPI baud rate * The PR31700 * supports multiple screen sizes * supports split and non-split displays * variable size and relocatable video buffer * DMA support for fetching image data from video buffer * 8-bit or 16-bit * programmable 1998 May 13 22 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS VSS = 0 V (GND) SYMBOL VDD VIN Tstg Pd Power supply voltage Input voltage Storage temperature range Maximum dissipation (Tamb = 70C) PARAMETER LIMITS VSS - 0.5 to 4.5 VSS - 0.5 to VDD + 0.5 -55 to +125 1 UNIT V V C W NOTE: 1. Using an LSI at specifications higher than the maximum ratings can cause permanent damage to the LSI. For normal operation, use under the recommended operating conditions. Exceeding the recommended operating conditions may affect the reliability of the LSI. RECOMMENDED OPERATING CONDITIONS VSS = 0 V (GND) SYMBOL VDD Topr Power supply voltage Operating temperature range PARAMETER LIMITS MIN 3.0 0 TYP 3.3 - MAX 3.6 70 UNIT V C 1998 May 13 23 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 DC CHARACTERISTICS (Tamb = 0C to 70C, VDD = 3.3V"0.3V) SYMBOL IDD IDDS,P PARAMETER Operating current Static current CONDITIONS VIN = VDD or VSS; VDD = MAX IOH = IOL = 0 VIN = VDD or VSS; VDD = MAX IOH = IOL = 0 mA SLEEP mode & RTC stop mode VIN = VDD or VSS; VDD = MAX IOH = IOL = 0 mA SLEEP mode & RTC running mode Input leakage current Input voltage1 Input voltage1 Input voltage2 Input voltage2 Output voltage3 Output voltage3 Output voltage4 Output voltage4 Output voltage5 Output voltage5 Output voltage6 Output voltage6 Input current (Pull-down resister) VIN = VDD or VSS VDD = 3.6V VDD = 3.0V VDD = 3.6V VDD = 3.0V VDD = 3.0V; IOH = -4mA VDD = 3.0V; IOL = 4mA VDD = 3.0; IOH = -8mA VDD = 3.0; IOL = 8mA VDD = 3.0; IOH = -16mA VDD = 3.0; IOL = 16mA VDD = 3.0; IOH = -24mA VDD = 3.0; IOL = 24mA VDD = MAX; VIN = VDD LIMITS MIN - - TYP 110 10 MAX 130 100 UNIT mA A IDDS,Q IIN VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 IIHP - -10 VDD x 0.8 -0.3 2.4 -0.3 VDD - 0.6 - VDD - 0.6 - VDD - 0.6 - VDD - 0.6 - 20 20 - - - - - - - - - - - - - - 120 10 VDD + 0.3 VDD x 0.2 VDD + 0.3 0.6 - VDD + 0.4 - VDD + 0.4 - VDD + 0.4 - VDD + 0.4 120 A A V V V V V V V V V V V V A NOTES: 1. SYSVLKIN 2. Other inputs 3. D[31:0], RAS0*, RAS1*, DCS0*, DCKE*, DQMH, DQML, DREQ*, DGRNT*, BC32K, VDAT[3:0], CP, LOAD, DF, FRAME, DISPON, VIDDONE, PWRCS, TXD, RXD, CS3O*,CHIFS, CHICLK, CHIDOUT, CHIDIN, IO[6;0], SPICLK, SPIOUT, SPIIN, SIBSYNC, SIBDOUT, SIBMCLK, SIBCLK, RWPWR, IROUT, CARD1WAIT*, CARD2WAIT*, MIOX[2;0] 4. A[12:], ALE, RD*, WE* CAS3O*, CARDREG*, CARDIOWR*, CARD1CSL*, CARD1CSH*, CARD2CSL*, CARD2CSH* 5. DCLKOUT 6. MBUSCLK, MBUSDATA 1998 May 13 24 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 CRYSTAL OSCILLATOR CHARACTERISTICS PR31700 SYSCKIN SYSCLKOUT RECOMMENDED 9.216MHz CRYSTAL NIHON DEMPA KOGYO CO., LTD: AT-51 CIN X1TAL COUT SN00191 Figure 4. 10MHz Crystal RECOMMENDED VALUE SYMBOL fIN CIN, COUT PARAMETER MIN. Crystal Oscillator frequency External capacitors 8 25 8.25 10 MAX. 10 33 MHz pF UNIT PR31700 C32KIN C32KOUT RECOMMENDED 32.768kHz CRYSTAL KYOCERA CORPORATION: KF-38G CIN X1TAL COUT SN00192 Figure 5. 32 kHz Crystal RECOMMENDED VALUE SYMBOL CIN, COUT External capacitors PARAMETER MIN. 10 MAX. 33 pF UNIT 1998 May 13 25 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A A AA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAA A A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA Parameter Symbol Condition MIN. TYP. MAX. 10 Unit ms Crystal stabilization time 9.216MHz Crystal stabilization time 32.768kHz TSTA-10M f = 8.25MHz10MHz X'tal : AT-51 Cin = Cout = 10pF-33pF TSTA-32k f = 32kHz X'tal : KF-38G Cin = Cout = 10pF-33pF 2 s ELECTRICAL SPECIFICATIONS (VSS = 0V, VDD = 3.3V) PR31700 TIMING 0.8V DELAY 2.0V OUTPUTS 2.2V 0.8V SETUP 0.8VCC HOLD 2.2V 0.8V INPUTS 0.2VCC 2.2V 0.8V SN00165 Figure 6. Definition of AC Specification 1998 May 13 26 AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A The following operating conditions apply to all values specified in this section. Tamb = 0C to 70C, VDD = 3.3 0.3V, External Capacitance = 40pF 1998 May 13 AC CHARACTERISTICS Philips Semiconductors Memory Interface 32-bit RISC microprocessor Item 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 2 1 D[31 : 16] to DCLKIN Setup time Delay DCLKOUT to MCS3-0* Delay DCLKOUT to MCS3-0* Delay DCLKOUT to DCKE Delay DCLKOUT to DCKE Delay DCLKOUT to DCS0* Delay DCLKOUT to DCS0* Delay DCLKOUT to DQMH/L Delay DCLKOUT to DQMH/L Delay DCLKOUT to RAS1* Delay DCLKOUT to RAS1* Delay DCLKOUT to RAS0* Delay DCLKOUT to RAS0* Delay DCLKOUT to CARDIOWR* Delay DCLKOUT to CARDIOWR* Delay DCLKOUT to CARDIORD* Delay DCLKOUT to CARDIORD* Delay DCLKOUT to CARDREG* Delay DCLKOUT to CARDREG* Delay DCLKOUT to CARDDIR* Delay DCLKOUT to CARDDIR* Delay DCLKOUT to CARDxCSx* Delay DCLKOUT to CARDxCSx* Delay DCLKOUT to CAS3-0* Delay DCLKOUT to CAS3-0* Delay DCLKOUT to WE* Delay DCLKOUT to WE* Delay DCLKOUT to RD* Delay DCLKOUT to RD* Delay DCLKOUT to CS3-0* Delay DCLKOUT to CS3-0* Delay DCLKOUT to D[15:0] Delay DCLKOUT to D[31:16] Delay DCLKOUT to A[12:0] Delay DCLKOUT to ALE Delay DCLKOUT to ALE DCLKOUT period DCLKOUT low time DCLKOUT high time Parameter 27 Rising / Falling Fallmng Fatting Falling Falling Falling Falling Falling Falling Falljng Falling Falling Falling Falling Falling Falling Falling Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising MIN. 13.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 5.4 5.4 1 MAX. Preliminary specification 2.5 2.5 10 10 10 10 12 10 10 11 8 8 6 7 9 8 9 8 6 6 9 9 9 9 8 9 4 5 7 8 8 8 8 3 4 - PR31700 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A Item 6 5 6 7 Parameter Rising / Falling MIN. 2 0 MAX. Unit ns ns ns ns D[31 : 16] to DCLKIN Hold time D[15:0] to DCLKIN Setup time D[15:0] to DCLKIN Hold time 2.5 0 DCLKOUT to DCLKIN Board Delay time 3 1 2 DCLKOUT MEMORY OUTPUTS 3 4 SN00168 Figure 7. Memory Output and Clock Timing DCLKIN MEMORY INPUTS 5 6 SN00169 Figure 8. Memory Input Timing DCLKOUT 7 DCLKIN SN00170 Figure 9. DCLKOUT to DCLKIN 1998 May 13 28 AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A CHI CHARACTERISTICS 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor Item 9 8 6 5 9 8 6 5 9 8 6 5 7 7 4 4 7 7 4 4 7 7 4 4 7 7 4 4 3 2 1 CHIDIN to CHICLK Falling Hold time(Slave) CHIDIN to CHICLK Falling Setup time(Slave) CHIDIN to CHICLK Rising Hold time(Slave) CHIDIN to CHICLK Rising Setup time(Slave) CHIFS to CHICLK Falling Hold time(Slave) CHIFS to CHICLK Falling Setup time(Slave) CHlFS to CHICLK Rising Hold time(Slave) CHIFS to CHICLK Rising Setup time(Slave) CHIDIN to CHICLK Falling Hold time(Master) CHIDIN to CHICLK Falling Setup time(Master) CHIDIN to CHICLK Rising Hold time(Master) CHIDIN to CHICLK Rising Setup time(Master) Delay CHICLK Falling to CHIFS(Slave) Delay CHICLK Falling to CHIFS(Slave) Delay CHICLK Rising to CHIFS(Slave) Delay CHICLK Rising to CHIFS(Slave) Delay CHICLK Falling to CHIDOUT(Slave) Delay CHICLK Falling to CHIDOUT(Slave) Delay CHICLK Rising to CHIDOUT(Slave) Delay CHICLK Rising to CHIDOUT(Slave) Delay CHICLK Falling to CHIFS(Master) Delay CHICLK Falling to CHIFS(Master) Delay CHICLK Rising to CHIFS(Master) Delay CHICLK Rising to CHIFS(Master) Delay CHICLK Falling to CHIDOUT(Master) Delay CHICLK Falling to CHIDOUT(Master) Delay CHICLK Rising to CHIDOUT(Master) Delay CHICLK Rising to CHIDOUT(Master) CHICLK period CHICLK low time CHICLK high time Parameter 29 Rising / Falling Falling Falling Falling Falling Falling Falling Falling Falling Rising Rising Rising Rising Rising Rising Rising Rising MIN. 225 100 100 20 20 20 20 20 20 20 20 20 20 20 20 Preliminary specification MAX. PR31700 15 15 15 15 15 15 15 15 5 5 5 5 5 5 5 5 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 1 2 CHICLK CHI OUTPUTS 3 4 SN00171 Figure 10. CHI Output and Clock Timing (CHITXEDGE=1) CHICLK CHI INPUTS 5 6 SN00172 Figure 11. CHI Input Timing (CHIRXEDGE=1) CHICLK CHI OUTPUTS 7 SN00173 Figure 12. CHI Output and Clock Timing (CHITXEDGE=0) CHICLK CHI INPUTS 8 9 SN00174 Figure 13. CHI Input Timing (CHIRXEDGE=0) 1998 May 13 30 AAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A SIB CHARACTERISTICS 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor Item 8 7 6 6 6 6 5 4 3 2 1 SIBDIN to SIBSCLK Rising Hold time SIBDIN to SIBSCLK Rising Setup time Delay SIBSCLK Rising to SIBDOUT Delay SIBSCLK Rising to SIBDOUT Delay SIBSCLK Rising to SIBSYNC Delay SIBSCLK Rising to SIBSYNC Delay SIBMCLK (Master) to SIBSCLK Delay SIBMCLK (Master) to SIBSCLK SIBMCLK period SIBMCLK low time SIBMCLK high time SIB OUTPUTS SIBSCLK SIBDIN SIBMCLK SIBSCLK Parameter 4 Figure 14. 1 Figure 15. 3 SIB CLK Timing 31 SIB Timing 2 Rising / Falling 7 Falling Falling Falling Rising Rising Rising - - - - - 8 6 5 MIN. 20 50 20 20 0 - - - - - - SN00176 MAX. Preliminary specification SN00175 2 2 2 2 5 5 - PR31700 Unit ns ns ns ns ns ns ns ns ns ns ns AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A SPI CHARACTERISTICS 1998 May 13 Philips Semiconductors 32-bit RISC microprocessor Item 6 5 9 8 7 7 4 4 3 2 1 SPIIN to SPICLK Falling Hold time SPIIN to SPICLK Falling Setup time SPIIN to SPICLK Rising Hold time SPIIN to SPICLK Rising Setup time Delay SPICLK Falling to SPIOUT Delay SPICLK Falling to SPIOUT Delay SPICLK Rising to SPIOUT Delay SPICLK Rising to SPIOUT SPICLK period SPICLK low time SPICLK high time SPIIN SPIOUT SPICLK SPIOUT SPICLK SPIIN Parameter Figure 17. Figure 16. 1 8 5 SPI Timing (PHAPOL = 0) SPI Timing (PHAPOL = 1) 3 32 9 6 2 Rising / Falling Falling Falling Rising Rising - - - - - - - 7 4 MIN. 250 120 120 15 15 15 15 - - - - MAX. SN00177 SN00178 Preliminary specification 5 5 5 5 - PR31700 Unit ns ns ns ns ns ns ns ns ns ns ns Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 VIDEO CHARACTERISTICS AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A Item 1 2 3 4 5 6 7 Parameter Rising / Falling MIN. 100 100 100 100 MAX. 1600 3200 3200 3200 5 Unit ns ns ns ns ns ns ns LOAD Pule width Delay LOAD Falling to FRAME Delay LOAD Falling to DF Delay LOAD Falling to CP Delay CP Rising to VDAT[3:0] VDAT to CP Rising Setup VDAT to CP Rising Hold 15 15 25 25 NOTE: 1. Values shown assume a 75MHz clock for the CPU. Min and Max values are programmable using Video Control Registers. 2 FRAME 3 DF LOAD 1 4 CP VDAT[3:0] 5 SN00179 Figure 18. Video Timing, 4-Bit Non-Split LCD CP VDAT[3:0] 6 7 SN00180 Figure 19. Video Data Timing, 4-Bit Split LCD and 8-Bit Non-Split LCD 1998 May 13 33 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 AAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A Item 1 2 Parameter Rising / Falling MIN. 50 2 MAX. Unit ms s VSTANDBY to PON* Rising VSTANDBY to ONBUTN delay time VSTANDBY 1 /PON 2 ONBUTN POWER CHARACTERISTICS SN00181 Figure 20. Power On Timing Diagram CPU RESET CHARACTERISTIC AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A 1 CPURES* low time 10 ns 1 CPURES* Item Parameter Rising / Falling MIN. MAX. Unit SN00182 Figure 21. CPU Reset Timing Diagram 1998 May 13 34 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 LQFP208: 208-PIN PLASTIC LOW PROFILE QUAD FLAT PACKAGE 1998 May 13 35 Philips Semiconductors Preliminary specification 32-bit RISC microprocessor PR31700 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 750 03867 Philips Semiconductors 1998 May 13 36 |
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