View W99682BCD_196559.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W99682BCD Data Sheet DIGITAL IMAGE PROCESSOR
Table of Contents1. 2. 3. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 SYSTEM OVERVIEW ................................................................................................................. 5 3.1 3.2 4. 5. 6. 7. 4.1 5.1 Operation Modes ............................................................................................................ 5 Address Mapping............................................................................................................ 5 System Camera Device .................................................................................................. 6 Power-on Reset Initialization ........................................................................................ 12
APPLICATION ............................................................................................................................ 6 PIN DESCRIPTION..................................................................................................................... 7 PIN CONFIGURATION ............................................................................................................. 13 ELECTRICAL CHARACTERISTICS......................................................................................... 14 7.1 7.2 7.3 Absolute Maximum Ratings .......................................................................................... 14 DC Characteristics........................................................................................................ 14 DAC DC Characteristics ............................................................................................... 15
8. 9.
PACKAGING DIMENSION ....................................................................................................... 16 REVISION HISTORY ................................................................................................................ 17
-1-
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
1. GENERAL DESCRIPTION
The W99682BCD is a high performance and highly-integrated DSC (Digital Still Camera) processor that it can preview, capture, compress, store, and display the digital still images or a short period of live video. In addition to processing still images, if connected to the PC through the USB, the W99682BCD based DSC can act as a PC camera, which captures real-time video (30 fps) to the PC. An on-chip USB controller is deployed for data transfer between the W99682BCD based DSC and the PC. The compressed pictures on flash memory (or SDRAM) can be up-loaded to the PC through the USB, and also the compressed pictures on the PC can be downloaded to the DSC through the USB. In addition to transfer image data, the W99682BCD allows to download the programs of micro controller through the USB to update the external flash program ROM, which allows for end users with firmware upgrades through the Internet. W99682BCD supports CCD and CMOS image sensors with high performance DSP functions including missing color interpolation, AE (Auto Exposure), AWB (Auto White Balance), Gamma Correction, edge enhancement, contrast stretching, hue and saturation adjusting etc. W99682BCD has built-in the baseline JPEG codec for image compression and decompression, which corresponds to the ISO/IEC international standard 10918-1, with YCbCr4:2:2 or YCbCr4:2:0 components in interleaved scan. W99682BCD also supports the Exchangeable Image File format (EXIF) to ensure data compatibility and exchangeability. W99682BCD implements full-speed USB controller complying with USB Spec. Rev. 1.1. It includes six endpoints in which one Control transfer for control data, two isochronous transfer for video and audio data, two programmable bulk transfer for compressed image data and one interrupt transfer for status or event. W99682BCD includes an 8032 compatible CPU core, a 6K-byte SRAM and two 16-bit programmable timers. The internal 8032 can be optional to disable and connects with external microcontroller for software development. W99682BCD supports a flexible flash memory interface and can directly connect to CompactFlash and NAND type flash. It also supports the DMA data transfer between SDRAM, USB and flash memory. W99682BCD integrates a TV encoder to support both NTSC and PAL output.
2. FEATURES
Host Interface * Support UART / USB Bus Host Interface. * Easy for host to develop Camera function through UART or USB Command set protocol. Sensor Interface * Direct connect to CMOS and CCD image sensor: * CMOS Image Sensor: AGILENT, HYUNDAI, IC MEDIA, MOTOROLA, OMNIVITION, PHOTOBIT, PIXART and TOSHIBA * Supports real-time video resolutions up to 640X480 and still image resolutions up to 2048X2048 * High performance sensor DSP functions (includes black level compensation, color Interpolation, false color suppression, edge enhancement, color correction, gamma correction, AEC, AWB, contrast stretching, hue and saturation adjusting) -2-
W99682BCD
* Supports universal serial interface to program CMOS or CCD image sensor. Audio Interface * Support I2S and AC-97 audio codec interface for audio record or playback. Frame Memory Interface * Supports 16Mb and 64Mb SDRAM with Self Refresh mode * 16-bit DRAM data bus in 2 Mbytes (1-1Mx16 SDRAM), 4 Mbytes (2-1Mx16 SDRAM), 8 Mbytes (1-4Mx16 SDRAM), or 16 Mbytes (2-4Mx16 SDRAM) configuration Flash Memory Interface * Directly connect to CompactFlash (CF) and NAND type flash memory * Supports DMA data transfer between SDRAM and flash memory PC Interface * Compliant with USB Spec. Rev. 1.1 specification * Supports six USB pipes including control pipe, isochronous-in pipe for video, isochronous-in pipe for audio, bulk-in pipe, bulk-out pipe, and interrupt pipe User Interface * Built-in 8-bit 8032 compatible uC with internal 6K bytes data RAM * Supports external 64K bytes program ROM or flash-ROM * Supports external microcontroller mode to connect with In-Circuit-Emulator (ICE) for software development JPEG CODEC for Image Compression and Decompression * Fully compliant with ISO/IEC 10918-1 international JPEG standard * JPEG compression and decompression for still images * Real-time motion JPEG (MJPEG) compression with advanced bit rate control for live video * JPEG baseline sequential mode in interleaved scan YCbCr4:2:2 or YCbCr4:2:0 format * Two programmable quantization tables for image/video quality control and bit-rate control. * Support Exchangeable Image File format (EXIF). Display Interface * Integrated TV encoder to support both NTSC and PAL output * Support OSD function to display the user interface message on TV Power Management * Advanced power management including Power-down, Stand-by, and Operating modes. Engines are only active when they are needed * USB power management including Startup, Operating, and Suspend modes
-3-
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
Operation Modes * Preview Mode: Display the incoming video on TV * Record Mode: Compressed images and audio are stored into the flash memory * Transfer Mode: Transfer image/audio data between PC and W99682BCD through USB * Playback Mode: Decode the compressed image to display on TV * PC Camera Mode: Real-time video/audio to the PC through USB with snapshot Built-in Two PLL (Phase-Locked Loops) Clock Synthesizers 2.5V Core, 3.3V I/O, 5 V Input Tolerant W99682BCD is packaged in a 128 pins LQFP Package
-4-
W99682BCD
3. SYSTEM OVERVIEW
Frame Memory
1M/4Mx16 SDRAM
Lens
CMOS/CCD Sensor TV
Image
Data
Control
W99682BCD
Single-Chip DSC Processor
USB User I/F & Status LCD uC F/W (ROM / Flash ROM)
Flash Control Audio Audio Codec (AC97/I2S)
I2S
Flash Memory
CompactFlash / SmartMedia / MultiMediaCard
Figure 3.1 W99682BCD Based DSC System Diagram
3.1 Operation Modes
The W99682BCD provides seven operation modes: * * * * * * * Preview Mode: Real-time capture and display the images (video) on TV. Record Mode: Capture/compress/store a still image (or video) on flash memory or SDRAM Playback Mode: Restore/decompress/display the stored images (single-image or thumbnails) on the TV Transfer Mode: Upload or download the flash memory or SDRAM to/from PC through the USB Download Mode: Download firmware from PC through the USB to external flash program ROM PCCam Mode: Real-time capture, compress, and transfer the video to PC through the USB Power Down: System enters power down mode to reduce the power consumption. It can be waked up from power down mode by reset or INT1_ event.
3.2 Address Mapping
C ADDRESS 0000H - 17FFH 1800H - F7FFH F800H -- FFFFH DESCRIPTION 6K Bytes Data RAM Reserved (Not Used) Control and Status Registers
-5-
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
4. APPLICATION
4.1 System Camera Device
* Host Interface
o o Support UART / USB Bus Host Interface. Easy for host to develop Camera function through UART or USB Command set protocol.
* * * * *
Support RGB/YUV CMOS, Video Processor or CCD interface. Built-in TV encoder supports NTSC, PAL Composite Video Standards JPEG CODEC for Image Compression and Decompression. Support OSD function to display the user interface message on TV/LCD screen Audio record or playback interface I2S and AC-97 Application for Modem Cam. , IP Cam. or Home security...etc.
*
RGB/YUV CMOS Sensor 8 bit uC W78LE516 YUV CCD Sensor W99682BCD TV out USB Convert UART UART Interface USB Interface TV SDRAM Video Processo W99682 Camera Module YUV 2MB/8MB
-6-
W99682BCD
5. PIN DESCRIPTION
The following signal types are used in these descriptions. I IS B BR BU O A P G # Input pin Input pin with Schmitt trigger Bi-directional input/output pin Bi-directional input/output pin with repeater Bi-directional input/output pin with internal pull-up Output pin Analog input/output pin Power supply pin Ground pin Active low
USB Interface (3 pins) PIN NAME DM PIN NUMBER 46 TYPE A DESCRIPTION Data Minus line of differential USB upstream port. Data Plus line of differential USB upstream port. DP 45 A Note: provide an external 1.5 K pull-up resistor at DP so the device indicates to the host that it is a full-speed device. USB Cable Power
VBUS
49
IS
SDRAM Interface (39 pins) PIN NAME MD[15:0] PIN NUMBER 93, 91, 89, 86, 84, 82, 80, 77, 78, 81, 83, 85, 87, 90, 92, 94 TYPE BR SDRAM Data Bus. SDRAM Address Bus. 67, 64, 65, 62, 60, 57, 55, 53, 54, 56, 58, 61 Note: for SDRAM, MA[10:0] are sampled during the ACTIVE command (row address MA[10:0]) and READ/WRITE command (column address MA[7:0], with MA10 defining AUTO PRECHARGE) to select one location out of the 521K available in the respective bank. MA10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (MA10 HIGH). DESCRIPTION
MA[11:0]
O
-7-
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
SDRAM Interface (39 pins), continued
PIN NAME BA1, BA0
PIN NUMBER 66, 68
TYPE O
DESCRIPTION Bank Address: BA defines to which internal bank of SDRAM the ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA is also used to program the 12th and 13th bit of the Mode Register. Chip-0 Select: CS0# enables the command decoder for the external SDRAM BANK-0. CR0007 Bit-7 = "1" => General Purpose I/O [4] CR0007 Bit-7 = "0" => CS1# for the external SDRAM BANK-1 chip select. SDRAM Input/Output Mask. DQM are input mask signals for write accesses and output enable signals for read accesses. SDRAM Clock Enable. CKE activates the SMCLK signal. The SDRAM enters precharge power-down to deactivate the input and output buffers, excluding CKE, for maximum power saving when CKE is LOW coincident with a NOP. SDRAM Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SDRAM Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SDRAM Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SDRAM Clock.
CS0# GPIO4 / CS1#
69
O
95
O
DQM
76
O
CKE
71
O
WE# RAS# CAS# MCLK
73 70 72 75
O O O O
Sensor or Video Interface Interface (16 pins) PIN NAME SPCLK SVID[7:0] SHS SVS SCLK SBPF/ AEC SCK SDA/SDI SDO/SDE PIN NUMBER 118 117 -- 114, 111 -- 108 121 120 123 122 125 126 127 TYPE I I B B O B B B B DESCRIPTION Clock for Sensor or Video Data Input Sensor or Video Data Input. Horizontal Sync Input. Programmable polarity. Vertical Sync Input. Programmable polarity. Clock Output to Sensor Black Pixel Flag / Auto Exposure Control Serial Interface Clock Serial Interface Data Serial Interface Data Output / Serial Data Enable
-8-
W99682BCD
Micro Controller Interface (34 pins) PIN NAME AD[7:0] / P0[7:0] / FD[7:0] A[15:8] / P2[7:0] ALE PSEN# INT1# / P3[3] TXD / P3[1] / WR# RXD / P3[0] / RD# PIN NUMBER 20 -- 13 30 - 27, 24 -- 21 7 8 40 TYPE BU BU DESCRIPTION Multiplexed low-order Address/Data Bus. Port - 0 Flash Memory Data Bus High-order Address Bus. Port - 2 Address Latch Enable. ALE is used to enable the address latch that separates the address from the data on AD bus. Program Strobe Enable. PSEN# forces the external ROM onto AD bus during fetch and MOVC operations. External Interrupt - 1 Port-3 Bit-3 Internal uC Enable (CR0000 Bit-2 = "1") => Serial Transmit Data / Port-3 Bit-1 Internal uC Enable (CR0000 Bit-2 = "0") => Data Write Strobe for access W99682BCD. Internal uC Enable (CR0000 Bit-2 = "1") => Serial Receive Data / Port-3 Bit-0 Internal uC Enable (CR0000 Bit-2 = "0") => Data Read Strobe for access W99682BCD.
BU BU BU
39
BU
38
BU
Display Output (19 pins) PIN NAME CVBS RSET PIN NUMBER 100 103 TYPE A A DESCRIPTION TV Composite-0 Output Full-scale adjust control pin. The full-scale current of DAC is controlled by connecting a resister (RSET) between this pin and VSSA2. The full-scale current IOUT = 10.66 * VREF / RSET (mA). Compensation pin. A 0.1 uF ceramic capacitor with lead length as short as possible must be used to decouple this pin to VDDA1. Voltage reference output. Typical value is 0.9V. A 0.1 F ceramic capacitor with lead length as short as possible must be used to decouple this pin to VSSA2. TV DAC Analog Power Supply for Output. +3.3 V 0.3 V. TV DAC Analog Ground for Output TV DAC Analog Power Supply for Internal. +2.5 V 0.25 V. TV DAC Analog Ground for Internal
COMP
104
A
VREF DACVDDO DACVSSO DACVDDI DACVSSI
105 102 101 106 107
A P G P G
-9-
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
Audio Codec Interface (6 pins) PIN NAME ASCLK / GA0 ABCLK / GA4 ADI / GA5 ADO / GA1 AWS / ASYNC / GA2 ARST# / GA3 35 O 34 O PIN NUMBER 32 37 36 33 TYPE O BR I O DESCRIPTION Audio Interface Enable: Audio System Clock Audio Interface Enable: General Purpose I/O - A[0] Audio Interface Enable: Audio Bit Clock Audio Interface Enable: General Purpose I/O - A[4] Audio Interface Enable: Audio Data Input Audio Interface Enable: General Purpose I/O - A[5] Audio Interface Enable: Audio Data Output Audio Interface Enable: General Purpose I/O - A[1] Audio Interface Enable: I2S => Audio Word Select AC97=> Audio Sample Sync Audio Interface Enable: General Purpose I/O - A[2] Audio Interface Enable: Audio Reset Audio Interface Enable: General Purpose I/O - A[3]
Flash Memory Interface (20 pins) PIN NAME AD[7:0] / P0[7:0] / FD[7:0] FWE# / FIOWR# FRE# / FIORD# FCS0# / FA0 FCS1# / FA1 FALE / FCE1# FCLE / FCE2# FRB# 4 2 1 128 6 5 3 O O O O O O I 20 -- 13 BU PIN NUMBER TYPE Port - 0 Flash Memory Data Bus NAND: Write Enable CompactFlash: I/O Write Strobe NAND: Read Enable CompactFlash: I/O Read Strobe NAND: Chip-0 Enable CompactFlash: Address-0 NAND: Chip-1 Enable CompactFlash: Address-1 NAND: Address Latch Enable CompactFlash: Chip Select Signal - 1 NAND: Command Latch Enable CompactFlash: Chip Select Signal - 2 NAND: Ready/Busy CompactFlash: Ready Signal DESCRIPTION Multiplexed low-order Address/Data Bus.
- 10 -
W99682BCD
Miscellaneous (16pins) PIN NAME RESET XIN XOUT GPIO[6:0] GPIO[4] / CS1# GPIO[3] / INT0# GPIO[2:0] GB0/ PCLKA PIN NUMBER 51 10 11 48, 43, 95, 96, 97 -- 99 95 96 97 -- 99 26 TYPE IS I O BR BR BR BR BR DESCRIPTION Reset In. This pin is active high to reset chip. Reference frequency input from a crystal or a clock source. It should be 48 MHz if PLL is off (PLLSEL = 0) or 12 Mhz if PLL is on (PLLSEL = 1) for full-speed device. Oscillator output to a crystal. This pin is left unconnected if an external clock source is employed. General Purpose I/O [6:0] General Purpose I/O [4] / SDRAM Bank-1 Chip Select General Purpose I/O [3] / Interrupt Output to external C General Purpose I/O [2:0] CR_0000 Bit-6 = "0: General Purpose I/O - B[0] CR_0000 Bit-6 = "0: Programmable Clock Output - A
Power and Ground (38 pins) PIN NAME VDDB VSSB VDDI VSSI AVDD AVSS PIN NUMBER 12, 31, 47, 63, 79, 124 9, 25, 44, 59, 74, 88, 119 50, 113 52, 112 42 41 TYPE P G P G P G DESCRIPTION I/O Pad Buffer Power Supply. Provide isolated power to the I/O buffers for improved noise immunity. +3.3 V 0.3 V. I/O Pad Buffer Ground. Internal Core Logic Power Supply. +2.5 V 0.25 V. Internal Core Logic Ground. PLL Power Supply. . +2.5 V 0.25 V. PLL Ground.
- 11 -
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
5.1 Power-on Reset Initialization
During power-on reset, the states of MD[15:0]] are latched into the W99682BCDs internal configuration registers (CR0000 and CR0001) as device configuration information. Since each pin of MD[15:0] has no internally pulled-up or pulled-down on its I/O buffer. It is required to properly pull-up or pull-down each pin of MD[15:0] bus to config the operation mode of W99682BCD. POWER-on Reset Configuration Definitions
PINS MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Normal Operation Macro Test Mode Enable (Only for Testing) UPLL Disable (Only for Debugging, UPLL Clock from Pin XIN) UPLL Enable VPLL Disable (Only for Debugging, VPLL Clock from Pin GB2) VPLL Enable Normal Operation, Internal Clock is Divided by 2. Fast Cycle, Internal Clock is same as the MC8051 Clock Input. Force D+ Signal to Low Normal Operation USB Self-Powered Device USB Bus-Powered Device USB Low Power Device USB High Power Device Internal RCV comes from SIE (Only for Debugging) Internal RCV comes from USB Transceiver Reserved Normal operation PCLKA Output Function General Purpose I/O B[1] Function Normal operation Reserved Normal operation Reserved Normal operation Reserved Internal uC Disable Internal uC Enable 2 SDRAM Banks 1 SDRAM Bank 4M x 16 SDRAM 1M x 16 SDRAM DEFINITION CONT'L REG CR0001-7 CR0001-6 CR0001-5 CR0001-4 CR0001-3 CR0001-2 CR0001-1 CR0001-0 CR0000_7 CR0000_6 CR0000_5 CR0000_4 CR0000_3 CR0000_2 CR0000_1 CR0000_0
- 12 -
W99682BCD
6. PIN CONFIGURATION
The W99682BCD is packed in a 128 pins LQFP.
9695949392919089888786858483828180797877767574737271706968676665 GP MD MD MD VS MD MD MD MD MD DQ VS CA RA BA BA GP MD MD MD MD MD MD MD VD MD MC W CK CS MA MA IO IO 0 151 142 13SB 124 115 106 9 DB 8 M LKSB S E S 0 0 111 9 3 7 E 3/I4/C NT S1 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 GPIO2 GPIO1 GPIO0 CVBS/B AVSSB AVDDB RSET COMP VREF AVDD AVSS SVID0 SVID1 SVID2 SVID3 VSSI VDDI SVID4 SVID5 SVID6 SVID7 SPCLK VSSB SVS SHS SBPF/AEC SCLK VDDB SCK SDA SDO FA1/FCS1 MA10 VDDB MA8 MA0 MA7 VSSB MA1 MA6 MA2 MA5 MA3 MA4 VSSI RESET VDDI VBUS GPIO6 VDDB DM DP VSSB GPIO5 AVDDP AVSSP INT1 TXD/WR RXD/RD ABCLK/GA4 ADI/GA5 ARST/GA3 AWS/SYN/GA2 FI FI FC GB AS ADO/GA1 FC FAOR O E2/ P0. P0. P0. P0. P0. P0. P0. P0. E1/ P2. P2. P2. P2. 0/P P2. P2. CL 0/F P2. D/ W FC 0/A 2/A 4/A 6/A P2. 2/A FA PS 4/A 6/A VD VD 1/A 3/A 5/A 7/A 1/A 3/A CL 5/A 7/A K/ CS FR LE FR R/ LEAL VS XO D0 D2D3 D5D6 0/A 1011VS 12131415DB KA GA D7 D4 D1 DB EN XI UT SB SB 0 E B FW 89 0 E N E 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
W99682BCD 128 LQFP
123456789
1011121314151617181920212223242526272829303132
Figure 4.1
- 13 -
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER Ambient temperature Storage temperature DC supply voltage (2.5V) DC supply voltage (3.3V) I/O pin voltage with respect to VSS Table 7-1 MIN. 0 -40 0 0 - 0.3 MAX. 70 125 3.5 4.6 5.25 UNIT C C V V V
7.2 DC Characteristics
SYMBOL VDDB PARAMETER Power Supply for I/O Pads Power Supply for DAC Internal Circuit Power Supply for PLL Analog Power Supply for Core Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Pull-up Current Power Down Current Active Current Table 7-2 IOUT = 2 mA IOUT = -2 mA VIN = 0.4V VIN = 2.4V VIN = 0V 2.4 10 -10 -500 TBD TBD CONDITIONS MIN. 3.0 3.0 2.25 2.25 2.25 0 2.0 MAX. 3.6 3.6 2.75 2.75 2.75 0.8 5.25 VSS +0.4 UNIT V V V V V V V V V A A A A mA
DACVDDO Power Supply for DAC Output DACVDDI AVDD VDDI VIL VIH VOL VOH IIL IIH IUP IPD IDD
- 14 -
W99682BCD
7.3 DAC DC Characteristics
PARAMETER TVDAC Resolution Integral Linearity Error Differential Linearity Error Gray Scale Error LSB Size DAC-to-DAC Matching Output Compliance Gray Scale Current Range Output Impedance Output Capacitance (f = 1 MHz; IOUT = 0 mA) Monotonicity Internal VREF Power Supply Reject Ratio (f = 1 KHz) Table 7-3 Note 1. Measured with VREF = 1.235 V, RSET = 386 . RL = 37.5 . 1.230 1.265 1.272 TBD 0 2.0 33.28 2 1.278 34.08 TBD TBD 5 MIN. TYP. 10 0.5 0.5 2 1 TBD MAX. UNIT Bits LSB LSB %Gray A % V mA pF Guarantee d V %
- 15 -
Publication Release Date: December 19, 2003 Revision A1
W99682BCD
8. PACKAGING DIMENSION
128-pins LQFP
HD
D
96
65 64
A A2
A1
97
HE E
128 1
e
b
33
L
L1
32
c
Y
Controlling Dimension : Millimeters
Symbol A A1 A2 b c D E e HD HE L L1 y
0.002
Dimension in inch Min Nom Max
0.063 0.006
Dimension in mm Min Nom Max 1.60
0.05 1.35 0.13 0.10
0.15
1.40 0.16 0.15 1.45 0.23 0.20
0.053 0.055 0.057 0.005 0.006 0.009 0.004 0.006 0.008 0.547 0.551 0.547 0.551 0.016 0.622 0.630
0.556 13.90 14.00 14.10 0.556 13.90 14.00 14.10 0.40 0.638 15.80 16.00 16.20 0.638 15.80 16.00 16.20 0.030 0.45 0.60 0.75 1.00 0.003
0.08
0.622 0.630 0.018 0.024
0.039 0
7
0
7
- 16 -
W99682BCD
9. REVISION HISTORY
VERSION A1 DATE Dec. 19, 2003 PAGE Initial Issue DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 17 -
Publication Release Date: December 19, 2003 Revision A1

▲Up To Search▲

Price & Availability of W99682BCD

	To Download W99682BCD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .