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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. H8/300L Series Programming Manual Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Preface The H8/300L Series of single-chip microcomputers is built around the high-speed H8/300L CPU, with an architecture featuring eight 16-bit (or sixteen 8-bit) general registers and a concise, optimized instruction set. This manual gives detailed descriptions of the H8/300L instructions. The descriptions apply to all chips in the H8/300L Series. Assembly-language programmers should also read the separate H8/300 Series Cross Assembler User's Manual. For hardware details, refer to the hardware manual of the specific chip. Contents Section 1. CPU ................................................................................................................... 1 1.1 Overview ......................................................................................................................... 1 1.1.1 Features ................................................................................................................ 1 1.1.2 Data Structure ...................................................................................................... 2 1.1.3 Address Space...................................................................................................... 4 1.1.4 Register Configuration......................................................................................... 5 1.2 Registers ......................................................................................................................... 6 1.2.1 General Registers ................................................................................................. 6 1.2.2 Control Registers ................................................................................................. 6 1.2.3 Initial Register Values .......................................................................................... 7 1.3 Instructions ...................................................................................................................... 8 1.3.1 Types of Instructions............................................................................................ 8 1.3.2 Instruction Functions ........................................................................................... 9 1.3.3 Basic Instruction Formats .................................................................................... 20 1.3.4 Addressing Modes and Effective Address Calculation........................................ 26 Section 2. Instruction Set ................................................................................................. 31 2.1 Explanation Format ......................................................................................................... 31 2.2 Instructions ...................................................................................................................... 36 2.2.1 (1) ADD (add binary) (byte) ............................................................................... 36 2.2.1 (2) ADD (add binary) (word).............................................................................. 37 2.2.2 ADDS (add with sign extension) .................................................................. 38 2.2.3 ADDX (add with extend carry) ..................................................................... 39 2.2.4 AND (AND logical) ...................................................................................... 40 2.2.5 ANDC (AND control register) ...................................................................... 41 2.2.6 BAND (bit AND) .......................................................................................... 42 2.2.7 Bcc (branch conditionally) ............................................................................ 43 2.2.8 BCLR (bit clear)............................................................................................ 46 2.2.9 BIAND (bit invert AND)............................................................................... 48 2.2.10 BILD (bit invert load).................................................................................... 49 2.2.11 BIOR (bit invert inclusive OR) ..................................................................... 50 2.2.12 BIST (bit invert store) ................................................................................... 51 2.2.13 BIXOR (bit invert exclusive OR) .................................................................. 52 2.2.14 BLD (bit load) ............................................................................................... 53 2.2.15 BNOT (bit NOT) ........................................................................................... 54 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 2.2.21 2.2.22 (1) 2.2.22 (2) 2.2.23 2.2.24 2.2.25 2.2.26 2.2.27 2.2.28 2.2.29 2.2.30 2.2.31 2.2.32 (1) 2.2.32 (2) 2.2.32 (3) 2.2.32 (4) 2.2.32 (5) 2.2.32 (6) 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 2.2.39 2.2.40 2.2.41 2.2.42 2.2.43 2.2.44 2.2.45 2.2.46 BOR (bit inclusive OR)................................................................................. 56 BSET (bit set)................................................................................................ 57 BSR (branch to subroutine)........................................................................... 59 BST (bit store)............................................................................................... 60 BTST (bit test)............................................................................................... 61 BXOR (bit exclusive OR) ............................................................................. 63 CMP (compare) (byte) .................................................................................. 64 CMP (compare) (word) ................................................................................. 65 DAA (decimal adjust add)............................................................................. 66 DAS (decimal adjust subtract) ...................................................................... 68 DEC (decrement)........................................................................................... 70 DIVXU (divide extend as unsigned) ............................................................. 71 EEPMOV (move data to EEPROM) ............................................................. 73 INC (increment) ............................................................................................ 74 JMP (jump).................................................................................................... 75 JSR (jump to subroutine)............................................................................... 76 LDC (load to control register) ....................................................................... 77 MOV (move data) (byte) ............................................................................... 78 MOV (move data) (word).............................................................................. 79 MOV (move data) (byte) ............................................................................... 80 MOV (move data) (word).............................................................................. 81 MOV (move data) (byte) ............................................................................... 82 MOV (move data) (word).............................................................................. 83 MULXU (multiply extend as unsigned)........................................................ 84 NEG (negate)................................................................................................. 85 NOP (no operation) ....................................................................................... 86 NOT (NOT = logical complement) ............................................................... 87 OR (inclusive OR logical)............................................................................. 88 ORC (inclusive OR control register)............................................................. 89 POP (pop data) .............................................................................................. 90 PUSH (push data).......................................................................................... 91 ROTL (rotate left).......................................................................................... 92 ROTR (rotate right) ....................................................................................... 93 ROTXL (rotate with extend carry left).......................................................... 94 ROTXR (rotate with extend carry right) ....................................................... 95 RTE (return from exception) ......................................................................... 96 RTS (return from subroutine)........................................................................ 97 2.2.47 SHAL (shift arithmetic left) .......................................................................... 98 2.2.48 SHAR (shift arithmetic right)........................................................................ 99 2.2.49 SHLL (shift logical left)................................................................................100 2.2.50 SHLR (shift logical right) .............................................................................101 2.2.51 SLEEP (sleep) ...............................................................................................102 2.2.52 STC (store from control register) ..................................................................103 2.2.53 (1) SUB (subtract binary) (byte) .........................................................................104 2.2.53 (2) SUB (subtract binary) (word)........................................................................105 2.2.54 SUBS (subtract with sign extension) ............................................................106 2.2.55 SUBX (subtract with extend carry) ...............................................................107 2.2.56 XOR (exclusive OR logical) .........................................................................108 2.2.57 XORC (exclusive OR control register) .........................................................109 2.3 Operation Code Map .......................................................................................................110 2.4 List of Instructions...........................................................................................................112 2.5 Number of Execution States ............................................................................................119 Section 3. CPU Operation States ...................................................................................127 3.1 Program Execution State .................................................................................................128 3.2 Exception Handling States...............................................................................................128 3.2.1 Types and Priorities of Exception Handling..................................................128 3.2.2 Exception Sources and Vector Table .............................................................129 3.2.3 Outline of Exception Handling Operation ....................................................130 3.3 Reset State .......................................................................................................................131 3.4 Power-Down State ...........................................................................................................131 Section 4. Basic Operation Timing................................................................................133 4.1 On-chip Memory (RAM, ROM)......................................................................................133 4.2 On-chip Peripheral Modules and External Devices.........................................................134 Section 1. CPU 1.1 Overview The H8/300L CPU at the heart of the H8/300L Series features 16 general registers of 8 bits each (or 8 registers of 16-bits each), and a concise, optimized instruction set geared to highspeed operation. 1.1.1 Features The H8/300L CPU has the following features. General register configuration 16 8-bit registers (can be used as 8 16-bit registers) 55 basic instructions * Multiply and divide instructions * Powerful bit manipulation instructions 8 addressing modes * Register direct (Rn) * Register indirect (@Rn) * Register indirect with displacement (@(d:16, Rn)) * Register indirect with post-increment/pre-decrement (@Rn+/@ -Rn) * Absolute address (@aa:8/@aa:16) * Immediate (#xx:8/#xx:16) * Program-counter relative (@(d:8, PC)) * Memory indirect (@@aa:8) 64-kbyte address space 1 High-speed operation * All frequently used instructions are executed in 2 to 4 states * High-speed operating frequency: 5 MHz Add/subtract between 8/16-bit registers: 0.4 s 8 x 8-bit multiply: 2.8 s 16 / 8-bit divide: 2.8 s Low-power operation * Transition to power-down state using SLEEP instruction 1.1.2 Data Structure The H8/300L CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. * All operational instructions except ADDS and SUBS can operate on byte data. * The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. * The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each 4-bit of the byte is treated as a decimal digit. 2 Data Structure in General Registers: Data of all the sizes above can be stored in general registers as shown in figure 1-1. Data type 1-Bit data Register No. RnH Data format 7 0 7 6 5 43 2 1 0 Don't-care 1-Bit data RnL Don't-care 7 0 7 6 54 32 1 0 7 Byte data RnH M S B 0 L S B Don't-care 7 Byte data RnL Don't-care M S B 0 L S B 15 Word data Rn M S B 0 L S B 7 4-Bit BCD data RnH Upper 43 Lower 0 Don't-care 7 4-Bit BCD data RnL Don't-care Upper 43 Lower 0 RnH: RnL: MSB: LSB: Upper 8 bits of General Register Lower 8 bits of General Register Most Significant Bit Least Significant Bit Figure 1-1. Register Data Structure 3 Data Structure in Memory: Figure 1-2 shows the structure of data in memory. The H8/300L CPU is able to access word data in memory (MOV.W instruction), but only if the word data starts from an even-numbered address. If an odd address is designated, no address error occurs, but the access is performed starting from the previous even address, with the least significant bit of the address regarded as 0.* The same applies to instruction codes. * Note that the LSIs in the H8/300L Series also contain on-chip peripheral modules for which access in word size is not possible. Details are given in the applicable hardware manual. Data type Address Data format 1-Bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 0 7 6 5 43 2 1 0 M S B L S B M S B Upper 8 bits Lower 8 bits L S B Word data M S B M S B CCR CCR * L S B L S B Byte data (CCR) on stack M S B Upper 8 bits Lower 8 bits L S B Word data on stack CCR: Condition code register. Note: Word data must begin at an even address. *: Ignored when returned. Figure 1-2. Memory Data Formats The stack is always accessed a word at a time. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are returned, the lower byte is ignored. 1.1.3 Address Space The H8/300L CPU supports a 64-Kbyte address space (program code + data). The memory map differs depending on the particular chip in the H8/300L Series and its operating mode. See the applicable hardware manual for details. 4 1.1.4 Register Configuration Figure 1-3 shows the register configuration of the H8/300L CPU. There are 16 8-bit general registers (R0H, R0L, ..., R7H, R7L), which can also be accessed as eight 16-bit registers (R0 to R7). There are two control registers: the 16-bit program counter (PC) and the 8-bit condition code register (CCR). General Registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H Control Registers (CR) 15 PC CCR 76 54 3 210 IU H U N Z V C 0 Program Counter Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 (SP) SP: Stack Pointer Figure 1-3. CPU Registers 5 1.2 Registers 1.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high (R0H to R7H) and low (R0L to R7L) bytes can be accessed separately as 8-bit registers. The register length is determined by the instruction. R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. In assembly language, the letters SP can be coded as a synonym for R7. As indicated in figure 1-4, R7 (SP) points to the top of the stack. Unused area SP (R7) Stack area Figure 1-4. Stack Pointer 1.2.2 Control Registers The CPU has a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Instructions are fetched by 16-bit (word) access, so the least significant bit of the PC is ignored (always regarded as 0). (2) Condition Code Register (CCR): This 8-bit register indicates the internal status of the CPU with an interrupt mask (I) bit and five flag bits: half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The two unused bits are available to the user. The bit configuration of the condition code register is shown below. 6 Bit Initial value Read/Write * Not fixed 7 I 1 R/W 6 U * R/W 5 H * R/W 4 U * R/W 3 N * R/W 2 Z * R/W 1 V * R/W 0 C * R/W Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked. This bit is set to 1 automatically at the start of interrupt handling. Bits 6 and 4--User Bits (U): These bits can be written and read by software for its own purposes using LDC, STC, ANDC, ORC, and XORC instructions. Bit 5--Half-Carry (H): This bit is used by add, subtract, and compare instructions to indicate a borrow or carry out of bit 3 or bit 11. It is referenced by the decimal adjust instructions. Bit 3--Negative (N): This bit indicates the value of the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero (Z): This bit is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1--Overflow (V): This bit is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry (C): This bit is used by: * Add, subtract, and compare instructions, to indicate a carry or borrow at the most significant bit * Shift and rotate instructions, to store the value shifted out of the most or least significant bit * Bit manipulation instructions, as a bit accumulator Note that some instructions involve no flag changes. The flag operations with each instruction are indicated in the individual instruction descriptions that follow in section 2, Instruction Set. CCR is used by LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by the conditional branch instruction (Bcc). 1.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt mask bit (I) in CCR is set to 1. The other CCR bits and the general registers are not initialized. 7 The initial value of the stack pointer (R7) is not fixed. To prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 1.3 Instructions Features: * The H8/300L CPU has a concise set of 55 instructions. * A general-register architecture is adopted. * All instructions are 2 or 4 bytes long. * Fast multiply/divide instructions and extensive bit manipulation instructions are supported. * Eight addressing modes are supported. 1.3.1 Types of Instructions Table 1-1 classifies the H8/300L instructions by type. Section 2, Instruction Set, gives detailed descriptions. Table 1-1. Instruction Classification Function Instructions Types MOV, POP*, PUSH* Data transfer 1 Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, 14 DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT Logic operations 4 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, 8 Shift ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR Bit manipulation 14 BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc**, JMP, BSR, JSR, RTS Branch 5 RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8 System control Block data transfer EEPMOV 1 Total 55 * POP Rn is equivalent to MOV.W @SP+, Rn. PUSH Rn is equivalent to MOV.W Rn, @-SP. ** Bcc is a conditional branch instruction in which cc represents a condition. 8 1.3.2 Instruction Functions Tables 1-2 to 1-9 give brief descriptions of the instructions in each functional group. The following notation is used. Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) bit of CCR Z Z (zero) bit of CCR V V (overflow) bit of CCR C C (carry) bit of CCR PC Program counter SP Stack pointer (R7) #Imm Immediate data op Operation field disp Displacement + Addition - Subtraction Multiplication x / Division AND logical OR logical Exclusive OR logical Move Not :3, :8, :16 3-bit, 8-bit, or 16-bit length 9 Table 1-2. Data Transfer Instructions Instruction Size* MOV B/W Function (EAs) Rd, POP W Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. PUSH W * Size: Operand size B: Byte W: Word 10 Table 1-3. Arithmetic Instructions Instruction Size* ADD B/W SUB Function Rd Rs Rd, Rd + #Imm Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. Rd Rs C Rd, Rd #Imm C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. Rd 1 Rd Increments or decrements a general register. Rd 1 Rd, Rd 2 Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the condition code register. Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. Rd - Rs, Rd - #Imm Compares data in a general register with data in another general register or with immediate data. Word data can be compared only between two general registers. 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register. * Size: Operand size B: Byte W: Word ADDX SUBX B INC DEC ADDS SUBS DAA DAS MULXU B W B B DIVXU B CMP B/W NEG B 11 Table 1-4. Logic Operation Instructions Instruction Size* AND B Function Rd Rs Rd, Rd #Imm Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #Imm Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #Imm Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. Rd Rd Obtains the one's complement (logical complement) of general register contents. * Size: Operand size B: Byte Table 1-5. Shift Instructions Instruction Size* SHAL B SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR * Size: Operand size B: Byte B B B Function Rd shift Rd Performs an arithmetic shift operation on general register contents. Rd shift Rd Performs a logical shift operation on general register contents. Rd rotate Rd Rotates general register contents. Rd rotate through carry Rd Rotates general register contents through the C (carry) bit. OR B XOR B NOT B 12 Table 1-6. Bit Manipulation Instructions Instruction Size* BSET B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR BIOR B B 13 Table 1-6. Bit Manipulation Instructions (Cont.) Instruction Size* BXOR B Function C ( BIXOR B BLD BILD B B BST BIST B B 14 Table 1-7. Branching Instructions Instruction Size Bcc -- Function Branches if condition cc is true. The branching conditions are as follows. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS -- -- -- -- Description Always (True) Never (False) High Low or Same Carry Clear (High or Same) Carry Set (Low) Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Less or Equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Branches unconditionally to a specified address. Branches to a subroutine at a specified displacement from the current address. Branches to a subroutine at a specified address. Returns from a subroutine. 15 Table 1-8. System Control Instructions Instruction RTE SLEEP LDC Size* -- -- B Function Returns from an exception handling routine. Causes a transition to power-down state. Rs CCR, #Imm CCR Moves immediate data or general register contents to the condition code register. CCR Rd Copies the condition code register to a specified general register. CCR #Imm CCR Logically ANDs the condition code register with immediate data. CCR #Imm CCR Logically ORs the condition code register with immediate data. CCR #Imm CCR Logically exclusive-ORs the condition code register with immediate data. PC + 2 PC Only increments the program counter. * Size: Operand size B: Byte Table 1-9. Block Data Transfer Instruction Instruction Size EEPMOV -- Function if R4L 0 then repeat @R5+ @R6+ R4L - 1 R4L until R4L = 0 else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: size of block (bytes) R5: starting source address R6: starting destination address Execution of the next instruction starts as soon as the block transfer is completed. This instruction is for writing to the large-capacity EEPROM provided on chip with some models in the H8/300L Series. For details see the applicable hardware manual. 16 STC ANDC ORC XORC B B B B NOP -- Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are readmodify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers. Sequence 1 Read 2 Modify 3 Write Operation Read one data byte at the specified address Modify one bit in the data byte Write the modified data byte back to the specified address Example 1: BCLR is executed to clear bit 0 in port control register 4 (PCR4) under the following conditions. Input pin, Low P47: P46: Input pin, High P45 - P40: Output pins, Low The intended purpose of this BCLR instruction is to switch P40 from output to input. Before Execution of BCLR Instruction P47 Input Low 0 1 P46 Input High 0 0 P45 Output Low 1 0 P44 Output Low 1 0 P43 Output Low 1 0 P42 Output Low 1 0 P41 Output Low 1 0 P40 Output Low 1 0 Input/output Pin state PCR4 PDR4 Execution of BCLR Instruction BCLR #0 @PCR4 ;clear bit 0 in PCR4 After Execution of BCLR Instruction P47 P46 P45 Input/output Output Output Output Pin state Low High Low PCR4 1 1 1 PDR4 1 0 0 P44 Output Low 1 0 P43 Output Low 1 0 P42 Output Low 1 0 P41 Output Low 1 0 P40 Input High 0 0 17 Explanation: To execute the BCLR instruction, the CPU begins by reading PCR4. Since PCR4 is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to PCR4 to complete the BCLR instruction. As a result, bit 0 in PCR4 is cleared to 0, making P40 an input pin. In addition, bits 7 and 6 in PCR4 are set to 1, making P47 and P46 output pins. Example 2: BSET is executed to set bit 0 in the port 4 port data register (PDR4) under the following conditions. P47: Input pin, Low P46: Input pin, High P45 - P40: Output pins, Low The intended purpose of this BSET instruction is to switch the output level at P40 from Low to High. Before Execution of BSET Instruction P47 Input Low 0 1 P46 Input High 0 0 P45 Output Low 1 0 P44 Output Low 1 0 P43 Output Low 1 0 P42 Output Low 1 0 P41 Output Low 1 0 P40 Output Low 1 0 Input/output Pin state PCR4 PDR4 Execution of BSET Instruction BSET #0 @PDR4 ;set bit 0 in port 4 port data register 18 After Execution of BSET Instruction P47 Input Low 0 0 P46 Input High 0 1 P45 Output Low 1 0 P44 Output Low 1 0 P43 Output Low 1 0 P42 Output Low 1 0 P41 Output Low 1 0 P40 Output High 1 1 Input/output Pin state PCR4 PDR4 Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P47 and P46 are input pins, the CPU reads the level of these pins directly, not the value in the port data register. It reads P47 as Low (0) and P46 as High (1). Since P45 to P40 are output pins, for these pins the CPU reads the value in PDR4. The CPU therefore reads the value of port 4 as H'40, although the actual value in PDR4 is H'80. Next the CPU sets bit 0 of the read data to 1, changing the value to H'41. Finally, the CPU writes this value (H'41) back to PDR4 to complete the BSET instruction. As a result, bit 0 in PDR4 is set to 0, switching pin P40 to High output. However, bits 7 and 6 in PDR4 change their values. 19 1.3.3 Basic Instruction Formats (1) Format of Data Transfer Instructions Figure 1-5 shows the format used for data transfer instructions. 15 op 15 op 15 op 8 7 rm rn 0 MOV Rm Rn 8 7 rm rn 0 Rn @Rm, or @Rm 0 rm rn @(d:16, Rm) Rn, or Rn @(d:16, Rm) Rn 8 disp. 7 15 op 15 op 15 op rn 8 7 rm rn 0 @Rm+ Rn, or Rn @-Rm 0 abs. @aa:8 Rn, or Rn @aa:8 0 rn @aa:16 Rn, or Rn @aa:16 8 8 abs. 7 7 15 op 15 rn 8 7 IMM 0 #xx:8 Rn 0 rn #xx:16 Rn 8 op IMM 7 15 op Notation op: rm, rn: disp: abs.: IMM: 8 7 rn 0 POP, PUSH Operation field Register field Displacement Absolute address Immediate data Figure 1-5. Instruction Format of Data Transfer Instructions 20 (2) Format of Arithmetic, Logic Operation, and Shift Instructions Figure 1-6 shows the format used for arithmetic, logic operation, and shift instructions. 15 op 15 op 8 7 rn 8 op 7 rm rn 0 MULXU, DIVXU 8 7 rm rn 0 ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 15 0 ADD, SUB, CMP (Rm) ADDX, SUBX (Rm) 15 op 15 op 15 op 15 op rn rn 8 7 IMM 0 ADD, ADDX, SUBX, CMP (#xx:8) 0 rm rn 0 IMM AND, OR, XOR (#xx:8) 0 rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR AND, OR, XOR (Rm) 8 7 8 7 8 7 Notation op: rm, rn: IMM: Operation field Register field Immediate data Figure 1-6. Instruction Format of Arithmetic, Logic, and Shift Instructions 21 (3) Format of Bit Manipulation Instructions Figure 1-7 shows the format used for bit manipulation instructions. 15 op 8 7 IMM rn 0 BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) 15 op 15 op op 15 op op 15 op op 15 op op 8 7 rm rn 0 Operand: register direct (Rn) Bit No.: register direct (Rm) 0 rn IMM 0000 0000 0 0000 0000 0 IMM abs. 0000 0 abs. rm 0000 0 IMM rn 0 rn IMM 0000 0000 0 abs. IMM 0000 Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) 8 7 8 7 rn rm Operand: register indirect (@Rn) Bit No.: register direct (Rm) 8 7 8 7 15 op 8 7 15 op op 15 op op Notation op: rm, rn: abs.: IMM: 8 7 8 7 Operation field Register field Absolute address Immediate data Figure 1-7. Instruction Format of Bit Manipulation Instructions 22 15 op 8 7 IMM rn 0 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) 15 op op 15 op op 8 7 rn IMM 0 0000 0000 0 abs. IMM 0000 Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) 8 7 Notation op: rm, rn: abs.: IMM: Operation field Register field Absolute address Immediate data Figure 1-7. Instruction Format of Bit Manipulation Instructions (Cont.) 23 (4) Format of Branching Instructions Figure 1-8 shows the format used for branching instructions. 15 op 15 op 15 cc 8 7 disp. 0 Bcc 0 rm 0000 0 JMP (@aa:16) JMP (@Rm) 8 7 87 op abs. 8 op 7 abs. 8 op 7 disp. 8 op 7 rm 87 op abs. 8 op 7 abs. 8 7 op 15 0 JMP (@@aa:8) 0 BSR 0 0000 0 JSR (@aa:16) JSR (@Rm) 15 15 15 15 0 JSR (@@aa:8) 0 RTS 15 Notation op: cc: rm: disp.: abs.: Operation field Condition field Register field Displacement Absolute address Figure 1-8. Instruction Format of Branching Instructions 24 (5) Format of System Control Instructions Figure 1-9 shows the format used for system control instructions. 15 8 7 op 0 RTE, SLEEP, NOP 0 rn LDC, STC (Rn) 0 IMM ANDC, ORC, XORC, LDC (#xx:8) 15 op 15 op 8 7 8 7 Notation op: rn: IMM: Operation field Register field Immediate data Figure 1-9. Instruction Format of System Control Instructions (6) Format of Block Data Transfer Instruction Figure 1-10 shows the format used for the block data transfer instruction. 15 8 op op 7 0 EEPMOV Figure 1-10. Instruction Format of Block Data Transfer Instruction 25 1.3.4 Addressing Modes and Effective Address Calculation Table 1-10 lists the eight addressing modes and their assembly-language notation. Each instruction can use a specific subset of these addressing modes. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). The MOV instruction uses all the addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or absolute (5) addressing to identify a byte operand and 3-bit immediate addressing to identify a bit within the byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to identify the bit. Table 1-10. Addressing Modes No. (1) (2) (3) (4) (5) (6) (7) (8) Mode Register direct Register indirect Register indirect with 16-bit displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address (8 or 16 bits) Immediate (3-, 8-, or 16-bit data) PC-relative (8-bit displacement) Memory indirect Notation Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8, @aa:16 #xx:3, #xx:8, #xx:16 @(d:8, PC) @@aa:8 (1) Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. In most cases the general register is accessed as an 8-bit register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. (2) Register indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. 26 (3) Register Indirect with Displacement--@(d:16, Rn): This mode, which is used only in MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. For the MOV.W instruction, the resulting address must be even. (4) Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. The size of the increment is 1 or 2 depending on the size of the operand: 1 for a byte operand; 2 for a word operand. For a word operand, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. The size of the decrement is 1 or 2 depending on the size of the operand: 1 for a byte operand; 2 for a word operand. For a word operand, the original contents of the 16-bit general register must be even. (5) Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The @aa:8 mode uses an 8-bit absolute address of the form H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. (6) Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. 27 (7) PC-Relative--@(d:8, PC): This mode is used to generate branch addresses in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a signextended value to the program counter contents. The result must be an even number. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to 255). Note that the initial part of the area from H'0000 to H'00FF contains the exception vector table. See the applicable hardware manual for details. The word located at this address contains the branch address. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See the memory data structure description in section 1.1.2, Data Structure. Effective Address Calculation Table 1-11 explains how the effective address is calculated in each addressing mode. Table 1-11. Effective Address Calculation (1) Addressing mode, instruction format Register direct Rn Effective address calculation None 3 15 OP 87 43 reg m 0 reg n reg m 0 3 reg n 0 Effective address No. 1 Operands are contained in registers m and n 2 Register indirect @Rn 15 0 16-bit register contents 0 15 OP 76 43 reg 15 0 Operand is at address indicated by register 28 Table 1-11. Effective Address Calculation (2) Addressing mode, instruction format Register indirect with displacement @(d:16, Rn) Effective address calculation Effective address No. 3 15 16-bit register contents 15 OP 76 reg disp 4 Register indirect with pre-decrement @-Rn 43 0 0 15 + 0 16-bit displacement Operand address is sum of register contents and displacement 15 OP 76 reg 43 0 15 0 16-bit register contents 1 or 2* 15 0 Register is decremented before operand access Register indirect with post-increment @Rn+ 15 0 16-bit register contents + 1 or 2* * 1 for a byte operand, 2 for a word operand 5 Absolute address @aa:8 None 15 15 OP Absolute address @aa:16 15 OP abs Any address 0 15 0 87 abs 0 H'FF Operand address is in range from H'FF00 to H'FFFF 87 0 15 0 15 OP 76 reg 43 0 Register is incremented after operand access Register is incremented after operand access 29 Table 1-11. Effective Address Calculation (3) Addressing mode, instruction format Immediate #xx:8. 15 OP 87 IMM 0 Operand is 1-byte immediate data None 0 OP IMM Operand is 2-byte immediate data Effective address calculation None Effective address No. 6 Immediate #xx:16 15 7 PC-relative @(d:8, PC) 15 PC contents + 15 OP 87 disp 0 Sign extension disp Destination address 0 15 0 8 Memory indirect @@aa:8 15 OP 87 abs 15 H'00 15 0 15 Destination address 0 16-bit memory contents 87 0 0 reg, regm, regn: op: disp: abs: IMM: General register Operation field Displacement Absolute address Immediate data 30 Section 2. Instruction Set 2.1 Explanation Format Section 2 gives full descriptions of all the H8/300L Series instructions, presenting them in alphabetic order. Each instruction is explained in a table like the following: ADD (add binary) (byte) Operation Rd + (EAs) Rd Assembly-Language Format ADD.B I: Previous value remains unchanged. H: Set to 1 when there is a carry from bit 3; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a carry from bit 7; otherwise cleared to 0. Description This instruction adds the source operand to the contents of an 8-bit general register and places the result in the general register . Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte ADD.B ADD.B #xx:8, Rd Rs, Rd 8 0 rd 8 2nd byte IMM rs rd 3rd byte 4th byte No. of states 2 2 31 The parts of the table are explained below. Name: The full and mnemonic names of the instruction are given at the top of the page. Operation: The instruction is described in symbolic notation. The following symbols are used. Symbol Rd Rs Rn Inverse logic (logical complement) ()< > Contents of operand effective address * General registers are either 8 bits (R0H/R0L - R7H/R7L) or 16 bits (R0 - R7). Assembly-Language Format: The assembly-language coding of the instruction is given. An example is: ADD. B Mnemonic Size Source Destination 32 The operand size is indicated by the letter B (byte) or W (word). Some instructions have restrictions on the size of operands they handle. The abbreviation EAs or EAd (effective address of source or destination) is used for operands that permit more than one addressing mode. The H8/300L CPU supports the following eight addressing modes. The method of calculating effective addresses is explained in section 1.3.4, Addressing Modes and Effective Address Calculation, above. Notation Rn @Rn @(d:16, Rn) @Rn+/@ -Rn @aa:8/@aa:16 #xx:8/#xx:16 @(d:8, PC) @@aa:8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment/pre-decrement Absolute address Immediate Program-counter relative Memory indirect Operand size: Word or byte. Byte size is indicated for bit-manipulation instructions because these instructions access a full byte in order to read or write one bit. Condition code: The effect of instruction execution on the flag bits in CCR is indicated. The following notation is used: Symbol Meaning The flag is altered according to the result of the instruction. 0 The flag is cleared to "0." -- The flag is not changed. * Not fixed; the flag is left in an unpredictable state. Description: The action of the instruction is described in detail. 33 Instruction Formats: Each possible format of the instruction is shown explicitly, indicating the addressing mode, the object code, and the number of states required for execution when the instruction and its operands are located in on-chip memory. The following symbols are used: Symbol Imm. abs. disp. rs, rd, rn Meaning Immediate data (3, 8, or 16 bits) An absolute address (8 bits or 16 bits) Displacement (8 bits or 16 bits) General register number (3 bits or 4 bits) The s, d, and n correspond to the letters in the operand notation. Register Designation: 16-bit general registers are indicated by a 3-bit rs, rd, or rn value. 8-bit registers are indicated by a 4-bit rs, rd, or rn value. Address registers used in the @Rn, @(disp:16, Rn), @Rn+, and @-Rn addressing modes are always 16-bit registers. Data registers are 8-bit or 16-bit registers depending on the size of the operand. For 8-bit registers, the lower three bits of rs, rd, or rn give the register number. The most significant bit is 1 if the lower byte of the register is used, or 0 if the upper byte is used. Registers are thus indicated as follows: 16-Bit register rs, rd, or rn Register 000 R0 001 R1 : : 111 R7 8-Bit registers rs, rd, or rn Register 0000 R0H 0001 R1H : : 0111 R7H 1000 R0L 1001 R1L : : 1111 R7L Bit Data Access: Bit data are accessed as the n-th bit of a byte operand in a general register or memory. The bit number is given by 3bit immediate data, or by a value in a general register. When a bit number is specified in a general register, only the lower three bits of the register are significant. Two examples are shown below. 34 BSET R1L, R2H R1L don't care 011 Bit number = 3 R2H 01100101 Bit 3 is set to 1 BLD #5, @H'FF02:8 Bit No. 5 10100110 C H'FF02 Loaded to C (carry) flag in CCR The addressing mode and operand size apply to the register or memory byte containing the bit. Number of States Required for Execution: The number of states indicated is the number required when the instruction and any memory operands are located in on-chip ROM or RAM. If the instruction or an operand is located in external memory or the on-chip register field, additional states are required for each access. See section 2.5, Number of Execution States. 35 2.2 Instructions 2.2.1 (1) ADD (add binary) (byte) Operation Rd + (EAs) Rd Assembly-Language Format ADD.B I: Previous value remains unchanged. H: Set to 1 when there is a carry from bit 3; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a carry from bit 7; otherwise cleared to 0. Description This instruction adds the source operand to the contents of an 8-bit general register and places the result in the general register . Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte ADD.B ADD.B #xx:8, Rd Rs, Rd 8 0 rd 8 2nd byte IMM rs rd 3rd byte 4th byte No. of states 2 2 36 2.2.1 (2) ADD (add binary) (word) Operation Rd + Rs Rd Assembly-Language Format ADD.W Rs, Rd Operand Size Word Condition Code I ---- H N -- Z V ADD C I: Previous value remains unchanged. H: Set to 1 when there is a carry from bit 11; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a carry from bit 15; otherwise cleared to 0. Description This instruction adds word data in two general registers and places the result in the second general register. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte ADD.W Rs, Rd 0 9 2nd byte 0 rs 0 rd 3rd byte 4th byte No. of states 2 37 2.2.2 ADDS (add with sign extension) Operation Rd + 1 Rd Rd + 2 Rd Assembly-Language Format ADDS #1, Rd ADDS #2, Rd Operand Size Word Condition Code I H N Z ADDS V C ------ I: H: N: Z: V: C: ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction adds the immediate value 1 or 2 to word data in a general register. Unlike the ADD instruction, it does not affect the condition code flags. Instruction Formats and Number of Execution States Addressing mode Register direct Register direct Instruction code Mnem. Operands 1st byte ADDS ADDS #1, Rd #2, Rd 0 0 B B 2nd byte 0 8 0 rd 0 rd 3rd byte 4th byte No. of states 2 2 Note: This instruction cannot access byte-size data. 38 2.2.3 ADDX (add with extend carry) Operation Rd + (EAs) + C Rd Assembly-Language Format ADDX ADDX V C I: Previous value remains unchanged. H: Set to 1 if there is a carry from bit 3; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a carry from bit 7; otherwise cleared to 0. Description This instruction adds the source operand and carry flag to the contents of an 8-bit general register and places the result in the general register. Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte ADDX ADDX #xx:8, Rd Rs, Rd 9 0 rd E 2nd byte IMM rs rd 3rd byte 4th byte No. of states 2 2 39 2.2.4 AND (AND logical) Operation Rd (EAs) Rd Assembly-Language Format AND AND V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction ANDs the source operand with the contents of an 8-bit general register and places the result in the general register. Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte AND AND #xx:8, Rd Rs, Rd E 1 rd 6 2nd byte IMM rs rd 3rd byte 4th byte No. of states 2 2 40 2.2.5 ANDC (AND control register) Operation CCR #IMM CCR Assembly-Language Format ANDC #xx:8, CCR Operand Size Byte I: H: N: Z: V: C: Condition Code I H N Z ANDC V C ANDed with bit 7 of the immediate data. ANDed with bit 5 of the immediate data. ANDed with bit 3 of the immediate data. ANDed with bit 2 of the immediate data. ANDed with bit 1 of the immediate data. ANDed with bit 0 of the immediate data. Description This instruction ANDs the condition code register (CCR) with immediate data and places the result in the condition code register. Bits 6 and 4 are ANDed as well as the flag bits. No interrupt requests are accepted immediately after this instruction. All interrupts, including the nonmaskable interrupt (NMI), are deferred until after the next instruction. Instruction Formats and Number of Execution States Addressing mode Immediate Instruction code Mnem. Operands 1st byte ANDC #xx:8, CCR 0 6 2nd byte IMM 3rd byte 4th byte No. of states 2 41 2.2.6 BAND (bit AND) Operation C ( BAND V C ------ -------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. ANDed with the specified bit. Description This instruction ANDs a specified bit with the carry flag and places the result in the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 C C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BAND BAND BAND #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 7 7 7 6 C E 2nd byte 0 IMM 0 rd rd 0 abs 7 7 6 6 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 * Register direct, register indirect, or absolute addressing. 42 2.2.7 Bcc (branch conditionally) Operation If cc then PC + d:8 PC else next; Assembly-Language Format Bcc d:8 Condition code field (For mnemonics, see the table on the next page.) Operand Size -- I: H: N: Z: V: C: Condition Code I H N Z V Bcc C ------ ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. 43 Bcc (branch conditionally) Bcc Description If the specified condition is false, this instruction does nothing; the next instruction is executed. If the specified condition is true, a signed displacement is added to the address of the next instruction and execution branches to the resulting address. The displacement is a signed 8-bit value which must be even. The branch destination address can be located in the range -126 to +128 bytes from the address of the Bcc instruction. The applicable conditions and their mnemonics are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE cc Field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (True) Never (False) High Low or Same Carry Clear (High or Same) Carry Set (Low) Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Less or Equal Condition Always true Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 X Y (Signed) X < Y (Signed) X > Y (Signed) X Y (Signed) X > Y (Unsigned) X Y (Unsigned) X Y (Unsigned) X < Y (Unsigned) X Y (Signed or unsigned) X = Y (Signed or unsigned) Meaning BT, BF, BHS, and BLO are synonyms for BRA, BRN, BCC, and BCS, respectively. 44 Bcc (branch conditionally) Instruction Formats and Number of Execution States Instruction code Mnem. BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Operands d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 1st byte 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 1 2 3 4 5 6 7 8 9 A B C D E F 2nd byte disp. disp. disp. disp. disp. disp. disp. disp. disp. disp. disp. disp. disp. disp. disp. disp. 3rd byte 4th byte Bcc Adressing mode PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative PC relative No . of states 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 * The branch address must be even. 45 2.2.8 BCLR (bit clear) Operation 0 ( BCLR Condition Code I H N Z V C ------ ---------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction clears a specified bit in the destination operand to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit general register. The destination operand can be located in a general register or memory. The specified bit is not tested before being cleared. The condition code flags are not altered. #xx:3 or Rn 7 0 Bit No. 0 * Register direct, register indirect, or absolute addressing. 46 BCLR (bit clear) Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BCLR BCLR BCLR BCLR BCLR BCLR #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 Rn, Rd Rn, @Rd Rn, @aa:8 7 7 7 6 7 7 2 D F 2 D F rn 0 rd abs 2nd byte 0 IMM 0 rd abs rd 0 6 6 2 2 rn rn rd 0 7 7 2 2 0 IMM 0 IMM 3rd byte BCLR 4th byte No. of states 2 0 0 8 8 2 0 0 8 8 47 2.2.9 BIAND (bit invert AND) Operation C [ ( BIAND II HH N N Z ZV VC C ---------------- ---------- -- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. ANDed with the inverse of the specified bit. Description This instruction ANDs the inverse of a specified bit with the carry flag and places the result in the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 Invert C C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BIAND #xx:3, Rd BIAND #xx:3,@Rd BIAND #xx:3,@aa:8 7 7 7 6 C E 2nd byte 1 IMM 0 rd abs rd 0 7 7 6 6 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 * Register direct, register indirect, or absolute addressing. 48 2.2.10 BILD (bit invert load) Operation ( BILD Condition Code I H N Z V C ------ -------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded with the inverse of the specified bit. Description This instruction loads the inverse of a specified bit into the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 Invert C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BILD BILD BILD #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 7 7 7 7 C E 2nd byte 1 IMM 0 rd abs rd 0 7 7 7 7 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 * Register direct, register indirect, or absolute addressing. 49 2.2.11 BIOR (bit invert inclusive OR) Operation C [ ( BIOR V C ------ -------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. ORed with the inverse of the specified bit. Description This instruction ORs the inverse of a specified bit with the carry flag and places the result in the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 Invert C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BIOR BIOR BIOR #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 7 7 7 4 C E 2nd byte 1 IMM 0 rd abs rd 0 7 7 4 4 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 * Register direct, register indirect, or absolute addressing. 50 C 2.2.12 BIST (bit invert store) Operation C ( BIST V C ------ ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction stores the inverse of the carry flag to a specified bit location in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 C Invert The values of the unspecified bits are not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BIST BIST BIST #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 6 7 7 7 D F 2nd byte 1 IMM 0 rd abs rd 0 6 6 7 7 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of states 2 8 8 * Register direct, register indirect, or absolute addressing. 51 2.2.13 BIXOR (bit invert exclusive OR) Operation C [ ( BIXOR Condition Code I H N Z V C ------ I: H: N: Z: V: C: -------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Exclusive-ORed with the inverse of the specified bit. Description This instruction exclusive-ORs the inverse of a specified bit with the carry flag and places the result in the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 Invert C C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BIXOR #xx:3, Rd BIXOR #xx:3,@Rd BIXOR #xx:3,@aa:8 7 7 7 5 C E 2nd byte 1 IMM 0 rd abs rd 0 7 7 5 5 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 * Register direct, register indirect, or absolute addressing. 52 2.2.14 BLD (bit load) Operation ( BLD Condition Code I H N Z V C ------ I: H: N: Z: V: C: -------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded with the specified bit. Description This instruction loads a specified bit into the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BLD BLD BLD #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 7 7 7 7 C E 2nd byte 0 IMM 0 rd abs rd 0 7 7 7 7 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 * Register direct, register indirect, or absolute addressing. 53 2.2.15 BNOT (bit NOT) Operation ( BNOT V C ------ I: H: N: Z: V: C: ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction inverts a specified bit in a general register or memory location. The bit number is specified by 3-bit immediate data, or by the lower three-bits of a general register. The operation is shown schematically below. #xx:3 or Rn 7 Bit No. 0 Invert The bit is not tested before being inverted. The condition code flags are not altered. * Register direct, register indirect, or absolute addressing. 54 BNOT (bit NOT) Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BNOT BNOT BNOT BNOT BNOT BNOT #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 Rn, Rd Rn, @Rd Rn, @aa:8 7 7 7 6 7 7 1 D F 1 D F rn 0 rd abs 2nd byte 0 IMM 0 rd abs rd 0 6 6 1 1 rn rn 0 0 rd 0 7 7 1 1 0 IMM 0 IMM 0 0 3rd byte BNOT 4th byte No. of states 2 8 8 2 8 8 55 2.2.16 BOR (bit inclusive OR) Operation C ( BOR C ------ -------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. ORed with the specified bit. Description This instruction ORs a specified bit with the carry flag and places the result in the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 C C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BOR BOR BOR #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 7 7 7 4 C E 2nd byte 0 IMM 0 rd abs rd 0 7 7 4 4 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 * Register direct, register indirect, or absolute addressing. 56 2.2.17 BSET (bit set) Operation 1 ( BSET V C ------ I: H: N: Z: V: C: ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction sets a specified bit in the destination operand to 1. The bit number can be specified by 3-bit immediate data, or by the lower three-bits of an 8-bit general register. The destination operand can be located in a general register or memory. The specified bit is not tested before being cleared. The condition code flags are not altered. #xx:3 or Rn 7 Bit No. 0 1 * Register direct, register indirect, or absolute addressing. 57 BSET (bit set) Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BSET BSET BSET BSET BSET BSET #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 Rn, Rd Rn, @Rd Rn, @aa:8 7 7 7 6 7 7 0 D F 0 D F rn 0 rd abs 2nd byte 0 IMM 0 rd abs rd 0 6 6 0 0 rn rn 0 0 rd 0 7 7 0 0 0 IMM 0 IMM 0 0 3rd byte 4th byte BSET No. of states 2 8 8 2 8 8 58 2.2.18 BSR (branch to subroutine) Operation PC @-SP PC + d:8 PC Assembly-Language Format BSR d:8 Operand Size -- Condition Code I H N Z V BSR C ------ ---------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction pushes the program counter (PC) value onto the stack, then adds a specified displacement to the program counter value and branches to the resulting address. The program counter value used is the address of the instruction following the BSR instruction. The displacement is a signed 8-bit value which must be even. The possible branching range is -126 to +128 bytes from the address of the BSR instruction. Instruction Formats and Number of Execution States Addressing mode PC-relative Instruction code Mnem. Operands 1st byte BSR d:8 5 5 2nd byte disp 3rd byte 4th byte No. of states 6 59 2.2.19 BST (bit store) Operation C ( BST C ------ ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction stores the carry flag to a specified flag location in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 C Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BST BST BST #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 6 7 7 7 D F 2nd byte 0 IMM 0 rd abs rd 0 6 6 7 7 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of states 2 8 8 * Register direct, register indirect, or absolute addressing. 60 2.2.20 BTST (bit test) Operation ( BTST V C ------ ---- I: H: N: Z: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the specified bit is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction tests a specified bit in a general register or memory location and sets or clears the Zero flag accordingly. The bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit general register. The operation is shown schematically below. #xx:3 or Rn 7 Bit No. 0 Test The value of the specified bit is not altered. * Register direct, register indirect, or absolute addressing. 61 BTST (bit test) Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Absolute address Register direct Register indirect Absolute address Instruction code Mnem. Operands 1st byte BTST BTST BTST BTST BTST BTST #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 Rn, Rd Rn, @Rd Rn, @aa:8 7 7 7 6 7 7 3 C E 3 C E rn 0 rd abs 2nd byte 0 IMM 0 rd abs rd 0 6 6 3 3 rn rn rd 0 7 7 3 3 0 IMM 0 IMM 3rd byte BTST 4th byte No. of states 2 0 0 6 6 2 0 0 6 6 62 2.2.21 BXOR (bit exclusive OR) Operation C ( BXOR V C ------ -------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Exclusive-ORed with the specified bit. Description This instruction exclusive-ORs a specified bit with the carry flag and places the result in the carry flag. The specified bit can be located in a general register or memory. The bit number is specified by 3-bit immediate data. The operation is shown schematically below. Bit No. 7 #xx:3 0 C C The value of the specified bit is not changed. Instruction Formats and Number of Execution States Addressing mode Register direct Register indirect Instruction code Mnem. Operands 1st byte BXOR BXOR #xx:3, Rd #xx:3,@Rd #xx:3,@aa:8 7 7 7 5 C E 2nd byte 0 IMM 0 rd abs rd 0 7 7 5 5 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of states 2 6 6 Absolute address BXOR * Register direct, register indirect, or absolute addressing. 63 2.2.22 (1) CMP (compare) (byte) Operation Rd - (EAs); set condition code Assembly-Language Format CMP.B CMP V C I: Previous value remains unchanged. H: Set to 1 when there is a borrow from bit 3; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a borrow from bit 7; otherwise cleared to 0. Description This instruction subtracts an 8-bit source register or immediate data from an 8-bit destination register and sets the condition code flags according to the result. The destination register is not altered. Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte CMP.B CMP.B #xx:8,Rd Rs, Rd A 1 rd C 2nd byte IMM rs rd 3rd byte 4th byte No. of states 2 2 64 2.2.22 (2) CMP (compare) (word) Operation Rd - Rs; set condition code Assembly-Language Format CMP.W Rs, Rd Operand Size Word Condition Code I ---- H N -- Z CMP V C I: Previous value remains unchanged. H: Set to 1 when there is a borrow from bit 11; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a borrow from bit 15; otherwise cleared to 0. Description This instruction subtracts a source register from a destination register and sets the condition code flags according to the result. The destination register is not altered. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte CMP.W Rs, Rd 1 D 2nd byte 0 rs 0 rd 3rd byte 4th byte No. of states 2 65 2.2.23 DAA (decimal adjust add) Operation Rd (decimal adjust) Rd Assembly-Language Format DAA Rd Operand Size Byte Condition Code I ---- H * N -- Z V * DAA C I: Previous value remains unchanged. H: Unpredictable. N: Set to 1 when the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 when the adjusted result is zero; otherwise cleared to 0. V: Unpredictable. C: Set to 1 when there is a carry from bit 7; otherwise left unchanged. Description When the result of an addition operation performed by the ADD.B or ADDX instruction on 4bit BCD data is contained in an 8-bit general register and the carry and half-carry flags, the DAA instruction adjusts the result by adding H'00, H'06, H'60, or H'66 to the general register according to the table below. Valid results are not assured if this instruction is executed under conditions other than those stated above. Status before adjustment C flag 0 0 0 0 0 0 1 1 1 Upper nibble 0 -9 0 -8 0 -9 A-F 9 -F A-F 0 -2 0 -2 0 -3 H flag 0 0 1 0 0 1 0 0 1 Lower nibble 0 -9 A-F 0 -3 0 -9 A-F 0 -3 0 -9 A-F 0 -3 Value added H'00 H'06 H'06 H'60 H'66 H'66 H'60 H'66 H'66 Resulting C flag 0 0 0 1 1 1 1 1 1 66 DAA (decimal adjust add) Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte DAA Rd 0 F 2nd byte 0 rd 3rd byte 4th byte DAA No. of states 2 67 2.2.24 DAS (decimal adjust subtract) Operation Rd (decimal adjust) Rd Assembly-Language Format DAS Rd Operand Size Byte Condition Code I ---- H * N -- Z DAS V * C -- I: Previous value remains unchanged. H: Unpredictable. N: Set to 1 when the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 when the adjusted result is zero; otherwise cleared to 0. V: Unpredictable. C: Previous value remains unchanged. Description When the result of a subtraction operation performed by the SUB.B, SUBX, or NEG instruction on 4-bit BCD data is contained in an 8-bit general register and the carry and halfcarry flags, the DAA instruction adjusts the result by adding H'00, H'FA, H'A0, or H'9A to the general register according to the table below. Valid results are not assured if this instruction is executed under conditions other than those stated above. Status before adjustment C flag 0 0 1 1 Upper nibble 0-9 0-8 7-F 6-F H flag 0 1 0 1 Lower nibble 0-9 6-F 0-9 6-F Value added H'00 H'FA H'A0 H'9A Resulting C flag 0 0 1 1 68 DAS (decimal adjust subtract) Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte DAS Rd 1 F 2nd byte 0 rd 3rd byte 4th byte DAS No. of states 2 69 2.2.25 DEC (decrement) Operation Rd - 1 Rd Assembly-Language Format DEC Rd Operand Size Byte Condition Code I H N -- Z DEC V C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs (the previous value in Rd was H'80); otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction decrements an 8-bit general register and places the result in the general register. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte DEC Rd 1 A 2nd byte 0 rd 3rd byte 4th byte No. of states 2 70 2.2.26 DIVXU (divide extend as unsigned) Operation Rd / Rs Rd Assembly-Language Format DIVXU Rs, Rd Operand Size Byte Condition Code I H N -- Z DIVXU V C ------ ---- I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the divisor is negative; otherwise cleared to 0. Z: Cleared to 0 when divisor 0; otherwise not guaranteed. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction divides a 16-bit general register by an 8-bit general register and places the result in the 16-bit general register. The quotient is placed in the lower byte. The remainder is placed in the upper byte. The operation is shown schematically below. Rd Rd Dividend 16 bits / Rs Divisor 8 bits (RdH) (RdL) Remainder Quotient 8 bits 8 bits Valid results (Rd, N, Z) are not assured if division by zero is attempted or an overflow occurs. Division by zero is indicated in the Zero flag. Overflow can be avoided by the coding shown on the next page. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte DIVXU Rs, Rd 5 1 2nd byte rs 0 rd 3rd byte 4th byte No. of states 14 71 DIVXU (divide extend as unsigned) DIVXU Note: DIVXU Overflow Since the DIVXU instruction performs 16-bit / 8-bit 8-bit division, an overflow will occur if the divisor byte is equal to or less than the upper byte of the dividend. For example, H'FFFF / H'01 H'FFFF causes an overflow. (The quotient has more than 8 bits.) Overflows can be avoided by using a subprogram like the following. A work register is required. To perform DIVXU R0L, R1: MOV.B #H'00, R2H CMP.B R0L, R1H BCC L1 DIVXU R0L, R1 MOV.B R1L, R2L BRA L2 L1 MOV.B R1H, R2L DIVXU R0L, R2 MOV.B R2H, R1H DIVXU R0L, R1 MOV.B R2L, R2H MOV.B R1L, R2L L2 RTS (*4) R1 R2 Remainder Quotient (Low) (*4) (*3) R2 Partial remainder Quotient (High) (*3) (*2) R1 Partial remainder Dividend (Low) (*1) R1 R2 H'00 Dividend Dividend (High) (*2) R1 Remainder Quotient (*1) R1 R0L Divisor Dividend Quotient 72 2.2.27 EEPMOV (move data to EEPROM) Operation if R4L 0 then repeat @R5+ @R6+ R4L - 1 R4L until R4L = 0 else next; Assembly-Language Format EEPMOV Operand Size -- EEPMOV Condition Code I H N Z V C ------ ---------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction moves a block of data from the memory location specified in general register R5 to the memory location specified in general register R6. General register R4L gives the byte length of the block. Data are transferred a byte at a time. After each byte transfer, R5 and R6 are incremented and R4L is decremented. When R4L reaches 0, the transfer ends and the next instruction is executed. No interrupt requests are accepted during the data transfer. At the end of this instruction, R4L contains H'00. R5 and R6 contain the last transfer address +1. The memory locations specified by general registers R5 and R6 are read before the block transfer is performed. Instruction Formats and Number of Execution States Addressing mode Instruction code Mnem. Operands 1st byte EEPMOV 7 B 2nd byte 5 C 3rd byte 5 9 4th byte 8 F No. of states 9+4n* * n is the initial value in R4L (0 n 255). Although n bytes of data are transferred, memory is accessed 2(n+1) times, requiring 4(n+1) states. 73 2.2.28 INC (increment) Operation Rd + 1 Rd Assembly-Language Format INC Rd Operand Size Byte Condition Code I H N -- Z V INC C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs (the previous value in Rd was H'7F); otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction increments an 8-bit general register and places the result in the general register. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte INC Rd 0 A 2nd byte 0 rd 3rd byte 4th byte No. of states 2 74 2.2.29 JMP (jump) Operation (EAd) PC Assembly-Language Format JMP JMP C ------ ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction branches unconditionally to a specified destination address. The destination address must be even. Instruction Formats and Number of Execution States Addressing mode Register indirect Instruction code Mnem. Operands 1st byte JMP @Rn @aa:16 @@aa:8 5 5 5 9 A B 2nd byte 0 rn 0 abs. 0 0 abs. 3rd byte 4th byte No. of states 4 6 8 Absolute address JMP Memory indirect JMP 75 2.2.30 JSR (Jump to subroutine) Operation PC @-SP (EAd) PC Assembly-Language Format JSR JSR C ------ ---------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction pushes the program counter onto the stack, then branches to a specified destination address. The program counter value pushed on the stack is the address of the instruction following the JSR instruction. The destination address must be even. Instruction Formats and Number of Execution States Addressing mode Register indirect Instruction code Mnem. Operands 1st byte JSR @Rn @aa:16 @@aa:8 5 5 5 2nd byte 0 0 abs. abs. 3rd byte 4th byte No. of states 6 8 8 D 0 rn E F 0 Absolute address JSR Memory indirect JSR 76 2.2.31 LDC (load to control register) Operation (EAs) CCR Assembly-Language Format LDC LDC C Loaded from the source operand. Loaded from the source operand. Loaded from the source operand. Loaded from the source operand. Loaded from the source operand. Loaded from the source operand. Description This instruction loads the source operand contents into the condition code register (CCR). Bits 4 and 6 are loaded as well as the flag bits. No interrupt requests are accepted immediately after this instruction. All interrupts are deferred until after the next instruction. Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte LDC LDC #xx:8, CCR Rs, CCR 0 0 7 3 0 2nd byte IMM rs 3rd byte 4th byte No. of states 2 2 77 2.2.32 (1) MOV (move data) (byte) Operation Rs Rd Assembly-Language Format MOV.B Rs, Rd Operand Size Byte Condition Code I H N -- Z MOV V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction moves one byte of data from a source register to a destination register and sets condition code flags according to the data value. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte MOV.B Rs, Rd 0 C 2nd byte rs rd 3rd byte 4th byte No. of states 2 78 2.2.32 (2) MOV (move data) (word) Operation Rs Rd Assembly-Language Format MOV.W Rs, Rd Operand Size Word Condition Code I H N -- Z MOV V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction moves one word of data from a source register to a destination register and sets condition code flags according to the data value. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte MOV.W Rs, Rd 0 D 2nd byte 0 rs 0 rd 3rd byte 4th byte No. of states 2 79 2.2.32 (3) MOV (move data) (byte) Operation (EAs) Rd Assembly-Language Format MOV.B MOV V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction moves one byte of data from a source operand to a destination register and sets condition code flags according to the data value. The MOV.B @R7+, Rd instruction should never be used, because it leaves an odd value in the stack pointer. See section 3.2.3 for details. Instruction Formats and Number of Execution States Addressing mode Immediate Register indirect Register indirect with displacement Instruction code Mnem. Operands 1st byte MOV.B #xx:8, Rd MOV.B @RS, Rd MOV.B @(d:16,Rs),Rd F 6 6 6 2 6 rd 8 E C rd A 0 2nd byte IMM 0 rs 0 rs 0 rs abs rd abs. rd rd rd disp. 3rd byte 4th byte No. of states 2 4 6 6 4 6 Register indirect with post-increment MOV.B @Rs+, Rd Absolute address Absolute address MOV.B @aa:8, Rd MOV.B @aa:16, Rd 80 2.2.32 (4) MOV (move data) (word) Operation (EAs) Rd Assembly-Language Format MOV.W MOV Condition Code I H N -- Z V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction moves one word of data from a source operand to a destination register and sets condition code flags according to the data value. If the source operand is in memory, it must be located at an even address. MOV.W @R7+, Rd is identical in machine language to POP.W Rd. Note that the LSIs in the H8/300L Series contain on-chip peripheral modules for which access in word size is not possible. Details are given in the applicable hardware manual. Instruction Formats and Number of Execution States Addressing mode Immediate Register indirect Register indirect with displacement Instruction code Mnem. Operands 1st byte MOV.W #xx:16, Rd MOV.W @RS, Rd MOV.W @(d:16,Rs),Rd 7 6 6 6 6 9 9 2nd byte 0 0 rd 3rd byte 4th byte IMM No. of states 4 4 disp. 6 6 abs. 6 0 rs 0 rd F 0 rs 0 rd D 0 rs 0 rd B 0 0 rd Register indirect with post-increment MOV.W @Rs+, Rd Absolute address MOV.W @aa:16, Rd 81 2.2.32 (5) MOV (move data) (byte) Operation Rs (EAd) Assembly-Language Format MOV.B Rs, MOV V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction moves one byte of data from a source register to memory and sets condition code flags according to the data value. The MOV.B Rs, @-R7 instruction should never be used, because it leaves an odd value in the stack pointer. See section 3.2.3 for details. The instruction MOV.B RnH, @-Rn or MOV.B RnL, @-Rn decrements register Rn, then moves the upper or lower byte of the decremented result to memory. Instruction Formats and Number of Execution States Addressing mode Register indirect Register indirect with displacement Instruction code Mnem. Operands 1st byte MOV.B Rs, @Rd Rs, MOV.B @(d:16,Rd) 6 6 6 3 6 8 E C rs A 8 2nd byte 1 rd 1 rd 1 rd abs rs abs. rs rs rs disp. 3rd byte 4th byte No. of states 4 6 6 4 6 Register indirect with pre-decrement MOV.B Rs, @-Rd Absolute address Absolute address MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 82 2.2.32 (6) MOV (move data) (word) Operation Rs (EAd) Assembly-Language Format MOV.W Rs, MOV V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction moves one word of data from a general register to memory and sets condition code flags according to the data value. The destination address in memory must be even. MOV.W Rs, @-R7 is identical in machine language to PUSH.W Rs. The instruction MOV.W Rn, @-Rn decrements register Rn by 2, then moves the decremented result to memory. Note that the LSIs in the H8/300L Series contain on-chip peripheral modules for which access in word size is not possible. Details are given in the applicable hardware manual. Instruction Formats and Number of Execution States Addressing mode Register indirect Register indirect with displacement Instruction code Mnem. Operands 1st byte MOV.W MOV.W Rs, @Rd Rs, @(d:16, Rd) Rs, @-Rd Rs, @aa:16 6 6 6 6 9 2nd byte 1 rd 0 rs disp. 3rd byte 4th byte No. of states 4 6 6 abs. 6 F 1 rd 0 rs D 1 rd 0 rs B 8 0 rs Register indirect with pre-decrement MOV.W Absolute address MOV.W 83 2.2.33 MULXU (multiply extend as unsigned) Operation Rd x Rs Rd Assembly-Language Format MULXU Rs, Rd Condition Code I H N Z MULXU V C ------ I: H: N: Z: V: C: ---------- Operand Size Byte Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction performs 8-bit x 8-bit 16-bit multiplication. It multiplies a destination register by a source register and places the result in the destination register. The source register is an 8-bit register. The destination register is a 16-bit register containing the data to be multiplied in the lower byte. (The upper byte is ignored). The result is placed in both bytes of the destination register. The operation is shown schematically below. Rd Don't-care Multiplicand 8 bits x Rs Multiplier 8 bits Rd Product 16 bits The multiplier can occupy either the upper or lower byte of the source register. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte MULXU Rs, Rd 5 0 2nd byte rs 0 rd 3rd byte 4th byte No. of states 14 84 2.2.34 NEG (negate) Operation 0 - Rd Rd Assembly-Language Format NEG Rd Operand Size Byte Condition Code I ---- H N -- Z NEG V C I: Previous value remains unchanged. H: Set to 1 when there is a borrow from bit 3; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs (the previous contents of the destination register was H'80); otherwise cleared to 0. C: Set to 1 when there is a borrow from bit 7 (the previous contents of the destination register was not H'00); otherwise cleared to 0. Description This instruction replaces the contents of an 8-bit general register with its two's complement (subtracts the register contents from H'00). If the original contents of the destination register was H'80, the register value remains H'80 and the overflow flag is set. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte NEG Rd 1 7 2nd byte 8 rd 3rd byte 4th byte No. of states 2 85 2.2.35 NOP (no operation) Operation PC + 2 PC Assembly-Language Format NOP Operand Size -- I: H: N: Z: V: C: Condition Code I H N Z V NOP C ------ ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction only increments the program counter, causing the next instruction to be executed. The internal state of the CPU does not change. Instruction Formats and Number of Execution States Addressing mode Instruction code Mnem. Operands 1st byte NOP 0 0 2nd byte 0 0 3rd byte 4th byte No. of states 2 86 2.2.36 NOT (NOT = logical complement) Operation Rd Rd Assembly-Language Format NOT Rd Operand Size Byte Condition Code I H N -- Z NOT V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction replaces the contents of an 8-bit general register with its one's complement (subtracts the register contents from H'FF). Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte NOT Rd 1 7 2nd byte 0 rd 3rd byte 4th byte No. of states 2 87 2.2.37 OR (inclusive OR logical) Operation Rd (EAs) Rd Assembly-Language Format OR OR C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction ORs the source operand with the contents of an 8-bit general register and places the result in the general register. Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte OR OR #xx:8, Rd Rs, Rd C 1 rd 4 rs 2nd byte IMM rd 3rd byte 4th byte No. of states 2 2 88 2.2.38 ORC (inclusive OR control register) Operation CCR #IMM CCR Assembly-Language Format ORC #xx:8, CCR Operand Size Byte ORC Condition Code I I: H: N: Z: V: C: H N Z V C ORed with bit 7 of the immediate data. ORed with bit 5 of the immediate data. ORed with bit 3 of the immediate data. ORed with bit 2 of the immediate data. ORed with bit 1 of the immediate data. ORed with bit 0 of the immediate data. Description This instruction ORs the condition code register (CCR) with immediate data and places the result in the condition code register. Bits 6 and 4 are ORed as well as the flag bits. No interrupt requests are accepted immediately after this instruction. All interrupts are deferred until after the next instruction. Instruction Formats and Number of Execution States Addressing mode Immediate Instruction code Mnem. Operands 1st byte ORC #xx:8, CCR 0 4 2nd byte IMM 3rd byte 4th byte No. of states 2 89 2.2.39 POP (pop data) Operation @SP+ Rn Assembly-Language Format POP Rn Operand Size Word Condition Code I H N -- Z V 0 POP C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction pops data from the stack to a 16-bit general register and sets condition code flags according to the data value. POP.W Rn is identical in machine language to MOV.W @SP+, Rn. Instruction Formats and Number of Execution States Addressing mode Instruction code Mnem. Operands 1st byte POP Rd 6 D 2nd byte 7 0 rn 3rd byte 4th byte No. of states 6 90 2.2.40 PUSH (push data) Operation Rn @-SP Assembly-Language Format PUSH Rn Operand Size Word PUSH Condition Code I H N -- Z V 0 C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the data value is negative; otherwise cleared to 0. Z: Set to 1 when the data value is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction pushes data from a 16-bit general register onto the stack and sets condition code flags according to the data value. PUSH.W Rn is identical in machine language to MOV.W Rn, @-SP. Instruction Formats and Number of Execution States Addressing mode Instruction code Mnem. Operands 1st byte PUSH Rs 6 D 2nd byte F 0 rn 3rd byte 4th byte No. of states 6 91 2.2.41 ROTL (rotate left) Operation Rd (rotated left) Rd Assembly-Language Format ROTL Rd Operand Size Byte ROTL Condition Code I H N -- Z V 0 C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Receives the previous value in bit 7. Description This instruction rotates an 8-bit general register one bit to the left. The most significant bit is rotated to the least significant bit, and also copied to the carry flag. The operation is shown schematically below. MSB LSB C Bit 7 Bit 0 Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte ROTL Rd 1 2 2nd byte 8 rd 3rd byte 4th byte No. of states 2 92 2.2.42 ROTR (rotate right) Operation Rd (rotated right) Rd Assembly-Language Format ROTR Rd Operand Size Byte Condition Code I H N -- Z ROTR V 0 C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates an 8-bit general register one bit to the right. The least significant bit is rotated to the most significant bit, and also copied to the carry flag. The operation is shown schematically below. MSB LSB Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte ROTR Rd 1 3 2nd byte 8 rd 3rd byte 4th byte No. of states 2 Bit 7 Bit 0 C 93 2.2.43 ROTXL (rotate with extend carry left) Operation Rd (rotated with carry left) Rd Assembly-Language Format ROTXL Rd Operand Size Byte Condition Code I H N -- Z ROTXL V 0 C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Receives the previous value in bit 7. Description This instruction rotates an 8-bit general register one bit to the left through the carry flag. The carry flag is rotated into the least significant bit of the register. The most significant bit rotates into the carry flag. The operation is shown schematically below. MSB LSB C Bit 7 Bit 0 Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte ROTXL Rd 1 2 2nd byte 0 rd 3rd byte 4th byte No. of states 2 94 2.2.44 ROTXR (rotate with extend carry right) Operation Rd (rotated with carry right) Rd Assembly-Language Format ROTXR Rd Operand Size Byte Condition Code I H N -- Z ROTXR V 0 C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates an 8-bit general register one bit to the right through the carry flag. The least significant bit is rotated into the carry flag. The carry flag rotates into the most significant bit. The operation is shown schematically below. MSB LSB Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte ROTXR Rd 1 3 2nd byte 0 rd 3rd byte 4th byte No. of states 2 Bit 7 Bit 0 C 95 2.2.45 RTE (return from exception) Operation @SP+ CCR @SP+ PC Assembly-Language Format RTE Operand Size -- I: H: N: Z: V: C: Restored from stack. Restored from stack. Restored from stack. Restored from stack. Restored from stack. Restored from stack. Condition Code I H N Z V RTE C Description This instruction returns from an exception-handling routine. It pops the condition code register (CCR) and program counter (PC) from the stack. Program execution continues from the address restored to the program counter. The CCR and PC contents at the time of execution of this instruction are lost. The CCR is one byte in size, but it is popped from the stack as a word (in which the lower 8 bits are ignored). This instruction therefore adds 4 to the value of the stack pointer (R7). Instruction Formats and Number of Execution States Addressing mode Instruction code Mnem. Operands 1st byte RTE 5 6 2nd byte 7 0 3rd byte 4th byte No. of states 10 96 2.2.46 RTS (return from subroutine) Operation @SP+ PC Assembly-Language Format RTS Operand Size -- I: H: N: Z: V: C: Condition Code I H N Z V RTS C ------ ---------- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction returns from a subroutine. It pops the program counter (PC) from the stack. Program execution continues from the address restored to the program counter. The PC contents at the time of execution of this instruction are lost. Instruction Formats and Number of Execution States Addressing mode Instruction code Mnem. Operands 1st byte RTS 5 4 2nd byte 7 0 3rd byte 4th byte No. of states 8 97 2.2.47 SHAL (shift arithmetic left) Operation Rd (shifted arithmetic left ) Rd Assembly-Language Format SHAL Rd Operand Size Byte Condition Code I H N -- Z SHAL V C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 7. Description This instruction shifts an 8-bit general register one bit to the left. The most significant bit shifts into the carry flag, and the least significant bit is cleared to 0. The operation is shown schematically below. MSB LSB 0 C Bit 7 Bit 0 The SHAL instruction is identical to the SHLL instruction except for its effect on the overflow (V) flag. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte SHAL Rd 1 0 2nd byte 8 rd 3rd byte 4th byte No. of states 2 98 2.2.48 SHAR (shift arithmetic right) Operation Rd (shifted arithmetic right ) Rd Assembly-Language Format SHAR Rd Operand Size Byte Condition Code I H N -- Z SHAR V 0 C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts an 8-bit general register one bit to the right. The most significant bit remains unchanged. The sign of the result does not change. The least significant bit shifts into the carry flag. The operation is shown schematically below. MSB LSB Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte SHAR Rd 1 1 2nd byte 8 rd 3rd byte 4th byte No. of states 2 Bit 7 Bit 0 C 99 2.2.49 SHLL (shift logical left) Operation Rd (shifted logical left ) Rd Assembly-Language Format SHLL Rd Operand Size Byte SHLL Condition Code I H N -- Z V 0 C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts an 8-bit general register one bit to the left. The least significant bit is cleared to 0. The most significant bit shifts into the carry flag. The operation is shown schematically below. MSB LSB 0 C Bit 7 Bit 0 The SHLL instruction is identical to the SHAL instruction except for its effect on the overflow (V) flag. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte SHLL Rd 1 0 2nd byte 0 rd 3rd byte 4th byte No. of states 2 100 2.2.50 SHLR (shift logical right) Operation Rd (shifted logical right ) Rd Assembly-Language Format SHLR Rd Operand Size Byte SHLR Condition Code I H N -- Z V 0 C ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts an 8-bit general register one bit to the right. The most significant bit is cleared to 0. The least significant bit shifts into the carry flag. The operation is shown schematically below. MSB LSB Bit 7 Bit 0 Mnem. Operands SHLR Rd 0 C Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code 1st byte 1 1 2nd byte 0 rd 3rd byte 4th byte No. of states 2 101 2.2.51 SLEEP (sleep) Operation Program execution state powerdown mode Assembly-Language Format SLEEP Operand Size -- SLEEP Condition Code I H N Z V C ------ ---------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description When the SLEEP instruction is executed, the CPU enters a power-down mode. Its internal state remains unchanged, but the CPU stops executing instructions and waits for an exceptionhandling request (interrupt or reset). When it receives an exception-handling request, the CPU exits the power-down mode and begins the exception-handling sequence. If the interrupt mask (I) bit is set to 1, the power-down mode can be released only by a nonmaskable interrupt (NMI) or reset. For information about the power-down modes, see the applicable hardware manual. Instruction Formats and Number of Execution States Addressing mode Instruction code Mnem. Operands 1st byte SLEEP 0 1 2nd byte 8 0 3rd byte 4th byte No. of states 2 102 2.2.52 STC (store from control register) Operation CCR Rd Assembly-Language Format STC CCR, Rd Operand Size Byte STC Condition Code I H N Z V C ------ ---------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction copies the condition code register (CCR) to a specified general register. Bits 6 and 4 are copied as well as the flag bits. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte STC CCR, Rd 0 2 2nd byte 0 rd 3rd byte 4th byte No. of states 2 103 2.2.53 (1) SUB (subtract binary) (byte) Operation Rd - Rs Rd Assembly-Language Format SUB.B Rs, Rd Operand Size Byte Condition Code I ---- H N -- Z V SUB C I: Previous value remains unchanged. H: Set to 1 when there is a borrow from bit 3; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a borrow from bit 7; otherwise cleared to 0. Description This instruction subtracts an 8-bit source register from an 8-bit destination register and places the result in the destination register. Only register direct addressing is supported. To subtract immediate data it is necessary to use the SUBX.B instruction, first setting the zero flag to 1 and clearing the carry flag to 0. The following codings can also be used to subtract nonzero immediate data. (1) ORC #H'05, CCR SUBX #(Imm - 1), Rd (2) ADD #(0 - Imm), Rd XORC #H'01, CCR Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte SUB.B Rs, Rd 1 8 2nd byte rs rd 3rd byte 4th byte No. of states 2 104 2.2.53 (2) SUB (subtract binary) (word) Operation Rd - Rs Rd Assembly-Language Format SUB.W Rs, Rd Operand Size Word SUB Condition Code I ---- H N -- Z V C I: Previous value remains unchanged. H: Set to 1 when there is a borrow from bit 11; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. C: Set to 1 when there is a borrow from bit 15; otherwise cleared to 0. Description This instruction subtracts a 16-bit source register from a 16-bit destination register and places the result in the destination register. Instruction Formats and Number of Execution States Addressing mode Register direct Instruction code Mnem. Operands 1st byte SUB.W Rs, Rd 1 9 2nd byte 0 rs 0 rd 3rd byte 4th byte No. of states 2 105 2.2.54 SUBS (subtract with sign extension) Operation Rd - 1 Rd Rd - 2 Rd Assembly-Language Format SUBS #1, Rd SUBS #2, Rd Operand Size Word SUBS Condition Code I H N Z V C ------ ---------- I: H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction subtracts the immediate value 1 or 2 from word data in a general register. Unlike the SUB instruction, it does not affect the condition code flags. The SUBS instruction does not permit byte operands. Instruction Formats and Number of Execution States Addressing mode Register direct Register direct Instruction code Mnem. Operands 1st byte SUBS SUBS #1, Rd #2, Rd 1 1 B B 2nd byte 0 8 0 rd 0 rd 3rd byte 4th byte No. of states 2 2 106 2.2.55 SUBX (subtract with extend carry) Operation Rd - (EAs) - C Rd Assembly-Language Format SUBX SUBX V C I: Previous value remains unchanged. H: Set to 1 if there is a borrow from bit 3; otherwise cleared to 0. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Previous value remains unchanged when the result is zero; otherwise cleared to 0. V: Set to 1 when an overflow occurs; otherwise cleared to 0. Description This instruction subtracts the source operand and carry flag from the contents of an 8-bit general register and places the result in the general register. Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte SUBX SUBX #xx:8, Rd Rs, Rd B 1 rd E rs 2nd byte IMM rd 3rd byte 4th byte No. of states 2 2 107 2.2.56 XOR (exclusive OR logical) Operation Rd (EAs) Rd Assembly-Language Format XOR XOR C -- ------ I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 when the result is negative; otherwise cleared to 0. Z: Set to 1 when the result is zero; otherwise cleared to 0. V: Cleared to 0. C: Previous value remains unchanged. Description This instruction exclusive-ORs the source operand with the contents of an 8-bit general register and places the result in the general register. Instruction Formats and Number of Execution States Addressing mode Immediate Register direct Instruction code Mnem. Operands 1st byte XOR XOR #xx:8, Rd Rs, Rd D 1 rd 5 rs 2nd byte IMM rd 3rd byte 4th byte No. of states 2 2 108 2.2.57 XORC (exclusive OR control register) Operation CCR #IMM CCR Assembly-Language Format XORC #xx:8, CCR Operand Size Byte Condition Code I H N Z XORC V C I: Exclusive-ORed with bit 7 of the immediate data. H: Exclusive-ORed with bit 5 of the immediate data. N: Exclusive-ORed with bit 3 of the immediate data. Z: Exclusive-ORed with bit 2 of the immediate data. V: Exclusive-ORed with bit 1 of the immediate data. C: Exclusive-ORed with bit 0 of the immediate data. Description This instruction exclusive-ORs the condition code register (CCR) with immediate data and places the result in the condition code register. Bits 6 and 4 are exclusive-ORed as well as the flag bits. No interrupt requests are accepted immediately after this instruction. All interrupts, including the nonmaskable interrupt (NMI), are deferred until after the next instruction. Instruction Formats and Number of Execution States Addressing mode Immediate Instruction code Mnem. Operands 1st byte XORC #xx:8, CCR 0 5 2nd byte IMM 3rd byte 4th byte No. of states 2 109 2.3 Operation Code Map Table 2-1 shows the operation code map for instructions of the H8/300L CPU. Only the first byte (bits 15 to 8 of the first word) of the instruction code is indicated here. Indicates that the most significant bit of the 2nd byte (bit 7 of 1st word of instruction code) is 0. Indicates that the most significant bit of the 2nd byte (bit 7 of 1st word of instruction code) is 1. 110 Table 2-1. Operation Code Map LO 4 5 6 7 8 9 A B C D E F HI ORC XORC ANDC LDC ADD INC ADDS MOV ADDX DAA 0 1 2 3 0 NOT OR XOR AND SUB DEC SUBS CMP SUBX DAS NOP SLEEP STC LDC SHLL NEG SHLR ROTXL ROTXR 1 SHAL SHAR ROTL ROTR 2 MOV 3 BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT 4 RTS BSR RTE JMP BRA BRN BHI BLS BGT BLE 5 BST MOV * MULXU DIVXU JSR 6 BOR BXOR BAND BIST BLD MOV EEPMOV BSET BIOR BIXOR BIAND BILD BNOT BCLR BTST : 2 1 3 * ! " Bit manipulation instructions ADD ADDX CMP SUBX OR XOR AND MOV 111 7 8 9 A B C D E F Note: The PUSH and POP instructions are equivalent in machine language to the MOV instruction. See the descriptions of individual instructions in section 2.2, Instructions, for details. 2.4 List of Instructions Table 2-2. List of Instructions (1) Addressing Mode and Instruction Length (Bytes) No. of States * @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa:8/16 #xx:8/16 @@aa mplied Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd MOV.W @(d:16, Rs), Rd MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd PUSH Rs Operation @Rn Size Condition Code I HNZVC ---- B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @(d:16, Rs16) Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rs16 @(d:16, Rd16) W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP W SP-2 SP Rs16 @SP 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2 Rn 0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 0--6 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 112 Table 2-2. List of Instructions (2) Addressing Mode and Instruction Length (Bytes) No. of States * 2 2 2 2 2 2 2 2 2 2 2 2 2 @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa:8/16 #xx:8/16 @@aa mplied Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd MULXU.B Rs, Rd DIVXU.B Rs, Rd Operation @Rn Size Condition Code I HNZVC -- B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8+C Rd8 B Rd8+Rs8+C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal-adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8-C Rd8 B Rd8-Rs8-C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal-adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 B Rd8xRs8 Rd16 B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rn -- -- -- -- ------------ 2 ------------ 2 ---- --* -- -- -- --2 *2 -- ------------ 2 ------------ 2 ---- --* -- -- -- --2 *--2 -- -- -- -- -- -- -- 14 -- -- -- -- 14 AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd 2 2 2 2 2 2 2 ---- ---- ---- ---- ---- ---- ---- 0--2 0--2 0--2 0--2 0--2 0--2 0--2 113 Table 2-2. List of Instructions (3) Addressing Mode and Instruction Length (Bytes) No. of States * 2 2 2 2 2 2 2 2 @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa:8/16 #xx:8/16 @@aa mplied Mnemonic SHAL.B Rd Operation C b7 b0 0 @Rn Size Condition Code I HNZVC ---- B Rn 2 SHAR.B Rd B C b7 b0 2 ---- 0 SHLL.B Rd B C b7 b0 0 2 ---- 0 SHLR.B Rd B 0 b7 b0 C 2 ---- 0 0 ROTXL.B Rd B C b7 b0 2 ---- 0 ROTXR.B Rd B C b7 b0 2 ---- 0 ROTL.B Rd B C b7 b0 2 ---- 0 ROTR.B Rd B C b7 b0 2 ---- 0 BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 2 4 4 2 4 4 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 114 Table 2-2. List of Instructions (4) Addressing Mode and Instruction Length (Bytes) No. of States * 2 6 6 2 6 6 @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa:8/16 #xx:8/16 @@aa mplied Mnemonic BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 Operation @Rn Size Condition Code I HNZVC B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) Rn 2 ------------ 2 4 4 ------------ 8 ------------ 8 ------------ 2 4 4 ------------ 8 ------------ 8 ------------ 2 4 4 ------------ 8 ------------ 8 ------------ 2 4 4 ------------ 8 ------------ 8 ------ ---- 2 4 4 ------ ---- 6 ------ ---- 6 ------ ---- 2 4 4 ------ ---- 6 ------ ---- 6 ---------- 4 4 ---------- ---------- ---------- 4 4 ---------- ---------- 2 2 2 2 2 2 2 2 4 4 ------------ 2 ------------ 8 ------------ 8 115 Table 2-2. List of Instructions (5) Addressing Mode and Instruction Length (Bytes) No. of States * 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa:8/16 #xx:8/16 @@aa mplied Mnemonic BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 Operation @Rn Size Rn Branching Condition Condition Code I HNZVC B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- if condition is true then -- PC -- PC+d:8 else next; -- -- -- -- -- CZ = 0 CZ = 1 C=0 C=1 Z=0 Z=1 V=0 V=1 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 2 2 2 2 2 2 2 2 2 ------------ 2 ------------ 8 ------------ 8 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 116 Table 2-2. List of Instructions (6) Addressing Mode and Instruction Length (Bytes) No. of States * 2 2 2 2 @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa:8/16 #xx:8/16 @@aa mplied Mnemonic BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8 Operation @Rn Size Rn Branching Condition N=0 N=1 NV = 0 NV = 1 Z(NV) = 0 Z(NV) = 1 Condition Code I HNZVC -- if condition is true then -- PC -- PC+d:8 else next; -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 2 2 2 2 2 2 2 4 2 2 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 6 ------------ 8 ------------ 6 -- SP-2 SP PC @SP PC PC+d:8 -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR 2 2 2 2 2 2 JSR @Rn ------------ 6 JSR @aa:16 4 ------------ 8 JSR @@aa:8 2 ------------ 8 RTS RTE 2 ------------ 8 2 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR 2 ------------ 2 ------------ 2 117 Table 2-2. List of Instructions (7) Addressing Mode and Instruction Length (Bytes) No. of States * 2 @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa:8/16 #xx:8/16 @@aa mplied Mnemonic XORC #xx:8, CCR NOP EEPMOV Operation @Rn Size Condition Code I HNZVC B CCR#xx:8 CCR -- PC PC+2 -- if R4L 0 Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L = 0 else next; 2 Rn 2 ------------ 2 4 ------------ Notes: * The number of execution states indicated here assumes that the operation code and operand data are in on-chip memory. For other cases, refer to section 2.5, Number of Execution States. Set to 1 when there is a carry or borrow at bit 11; otherwise cleared to 0. When the result is 0, the previous value remains unchanged; otherwise cleared to 0. Set to 1 when there is a carry in the adjusted result; otherwise the previous value remains unchanged. The number of execution states is 4n + 9, with n being the value set in R4L. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is 0; otherwise cleared to 0. 118 2.5 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table 2-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table 2-4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. 1. BSET #0, @FF00 From table 2-4: I = L = 2, J = K = M = N= 0 From table 2-3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. 2. JSR @@ 30 From table 2-4: I = 2, J = K = 1, L = M = N = 0 From table 2-3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 119 Table 2-3. Number of States Taken by Each Cycle in Instruction Execution Execution Status (instruction cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation SI SJ SK SL SM SN 1 2 2 or 3* Access Location On-Chip Peripheral Module On-Chip Memory * Depends on which on-chip module is accessed. See the applicable hardware manual for details. 120 Table 2-4. Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDX ADDS.W #1/2, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI BLS d:8 d:8 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 1 J K L M N Instruction Mnemonic BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE BCLR d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 d:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd 121 Instruction Mnemonic Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L 2 2 M N BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 1 1 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 1 1 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 1 1 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 2 2 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 1 1 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 1 1 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 2 2 2 2 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 1 1 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd 2 2 2 122 Instruction Mnemonic Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L 2 1 M N BSET BSR BST BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 1 1 1 1 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 1 1 CMP CMP. B #xx:8, Rd CMP. B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 12 2n+2* 1 2 2 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 2 LDC LDC #xx:8, CCR LDC Rs, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd 1 123 Instruction Mnemonic Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L 1 1 1 1 1 1 1 1 1 2 2 M N MOV MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd MOV.W @(d:16, Rs), Rd MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 2 1 1 2 1 2 1 1 2 2 1 1 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 12 2 2 MULXU NEG NOP NOT OR MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC POP PUSH ROTL ROTR ROTXL ROTXR RTE RTS ORC #xx:8, CCR POP Rd PUSH Rs ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd RTE RTS 2 2 2 2 124 Instruction Mnemonic Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N SHLL SHAL SHAR SHLR SLEEP STC SUB SHLL.B Rd SHAL.B Rd SHAR.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SUBS SUBX SUBS.W #1/2, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each. 125 Section 3. CPU Operation States There are three CPU operation states, namely, program execution state, power-down state, and exception-handling state. In power-down state there are sleep mode, standby mode, and watch mode. These operation states are shown in figure 3-1. Figure 3-2 shows the state transitions. For further details please refer to the applicable hardware manual. State Program execution state Active mode The CPU executes successive program instructions, synchronized by the system clock. Subactive mode The CPU executes successive program instructions in lowspeed operations, synchronized by the subclock. Low-power modes Power-down state A state in which some or all of the chip functions are stopped to conserve power. Sleep mode Standby mode Watch mode Exception-handling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt. Figure 3-1. CPU Operation States 127 Reset cleared Reset state Reset occurs Reset occurs Interrupt raised Exceptionhandling state Interrupt raised Interrupt handling complete Power-down state SLEEP instruction executed Program execution state Note: On the transitions between modes, see the applicable hardware manual. Figure 3-2. State Transitions 3.1 Program Execution State In program execution state the CPU executes program instructions in sequence. 3.2 Exception Handling States Exception-handling states are transient states occurring when exception handling is raised by a reset or interrupt, and the CPU changes its normal processing flow, branching to a start address acquired from a vector table. In exception handling caused by an interrupt, PC and CCR values are saved to the stack, with reference made to a stack pointer (R7). 3.2.1 Types and Priorities of Exception Handling Exception handling includes processing of reset exceptions and of interrupts. Table 3-1 summarizes the factors causing each kind of exception, and their priorities. Reset exception handling has the highest priority. 128 Table 3-1. Types of Exception Handling and Priorities Timing for start of exception handling Reset exception handling starts as soon as RES pin changes from low to high. When an interrupt request is made, interrupt exception handling starts after execution of the present instruction is completed. Priority High Exception source Reset Detection timing Clock-synchronous Interrupt End of instruction execution* Low * Interrupt detection is not made upon completion of ANDC, ORC, XORC, and LDC instruction execution, nor upon completion of reset exception handling. 3.2.2 Exception Sources and Vector Table The factors causing exception handling can be classified as in figure 3-3. For details of exception handling, the vector numbers of each source, and the vector addresses, see the applicable hardware manual. Reset Exception source Interrupt Internal interrupt (interrupt raised by on-chip peripheral module) External interrupt Figure 3-3. Classification of Exception Sources 129 3.2.3 Outline of Exception Handling Operation A reset has the highest priority of all exception handling. After the RES pin goes to low level putting the CPU in reset state, the RES pin is then put at high level, and reset exception handling is started at the point when the reset conditions are met. For details on reset conditions refer to the applicable hardware manual. When reset exception handling is started, the CPU gets a start address from the exception handling vector table, and starts executing the exception handling routine from that address. During execution of this routine and immediately after, all interrupts including NMI are masked. When interrupt exception handling is started, the CPU refers to the stack pointer (R7) and pushes the PC and CCR contents to the stack. The CCR I bit is then set to 1, a start address is acquired from the exception handling vector table, and the interrupt exception handling routine is executed from this address. The stack state in this case is as shown in figure 3-4. SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack SP (R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PCH PCL Even-numbered address Prior to start of interrupt exception handling Notation PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Contents saved to stack After completion of interrupt exception handling Notes: * Ignored on return from interrupt. 1. PC shows the address of the first instruction to be executed upon return from the interrupt. 2. Saving and restoring of register contents must always be done in word size, and must start from an even-numbered address. Figure 3-4. Stack State after Completion of Interrupt Exception Handling 130 3.3 Reset State When the RES pin goes to low level, all processing stops and the system goes to reset state. The I bit of the condition code register (CCR) is set, masking all interrupts. After the RES pin is changed externally from low to high level, reset exception handling starts at the point when the reset conditions are met. For details on reset conditions refer to the applicable hardware manual. 3.4 Power-Down State In power-down state the CPU operation is stopped, reducing power consumption. For details see the applicable hardware manual. 131 Section 4. Basic Operation Timing CPU operation is synchronized by a clock (). The period from the rising edge of to the next rising edge is called one state. A memory cycle or bus cycle consists of two or three states. For details on access to on-chip memory and to on-chip peripheral modules see the applicable hardware manual. 4.1 On-chip Memory (RAM, ROM) Two-state access is employed for high-speed access to on-chip memory. The data bus width is 16 bits, allowing access in byte or word size. Figure 4-1 shows the on-chip memory access cycle. Bus cycle T1 state T2 state Internal address bus Address Internal read signal Internal data bus* (read access) Read data Internal write signal Internal data bus* (write access) Write data Note: A 16-bit data bus is used making possible access to word-size data in 2 states. Figure 4-1. On-Chip Memory Access Cycle 133 4.2 On-chip Peripheral Modules and External Devices On-chip peripheral modules are accessed in two or three states. The data bus width is 8 bits, so access is made in byte size only. Access to word data or instruction codes is not possible. Figure 4-2 shows the on-chip peripheral module access cycle. Bus cycle T1 state T2 state Internal address bus Address Internal read signal Internal data bus* (read access) Read data Internal write signal Internal data bus* (write access) Write data (a) Two-state access Bus cycle T1 state T2 state T3 state Internal address bus Address Internal read signal Internal data bus* (read access) Read data Internal write signal Internal data bus* (write access) Write data (b) Three-state access Note: An 8-bit data bus is used. Figure 4-2. On-Chip Peripheral Module Access Cycle 134 H8/300L Series Programming Manual Publication Date: 1st Edition, December 1991 Published by: Business Planning Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 1991. All rights reserved. Printed in Japan. |
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