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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. 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SH Graphics/Speech Processing Demonstration System NAV-DS4 Application Note ADE-502-058 Rev. 1.0 Preliminary 3/5/03 Hitachi, Ltd. Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Preface This Application Note covers the hardware and software of the NAV-DS4 navigation SH graphics/speech processing demonstration system developed by Hitachi, Ltd. It includes a number of practical examples intended for use as reference material when designing a navigation system using an SH3 microcomputer and Q2 graphics renderer (however, note that NAV-DS4 does not support GPS (Global Positioning System)). The NAV-DS4 uses a variety of Hitachi semiconductor devices, including an SH3 (SH7708) 32bit RISC processor, Q2 (HD64411) 2-dimensional (2D) graphics renderer, 16M DRAM (HM51W18165), and 8M flash memory (HN29WT800). Demonstration application software provided with the NAV-DS4 comprises map drawing and display, YUV natural image display, ADPCM speech output. All of this software runs on an HISH77 real-time operating system conforming to the ITRON standard. Operation, performance, and standards as a product are not guaranteed for the NAV-DS4. The operation of the electronic circuits and software included in this Application Note must be evaluated and confirmed by the user before use in an actual application system. Contents Section 1 1.1 1.2 1.3 1.4 1.5 1.6 Overview............................................................................................................ 1 System Specifications ........................................................................................................ 1 System Configuration ........................................................................................................ 3 Drawing and Display Processing Procedure...................................................................... 4 External Appearance of NAV-DS4.................................................................................... 6 Operating Procedures ......................................................................................................... 7 Usage Notes ....................................................................................................................... 13 NAV-DS4 Software ....................................................................................... Overview of Demonstration System.................................................................................. Overall Software Configuration......................................................................................... Task Configuration ............................................................................................................ Task Functions ................................................................................................................... Hardware Configuration .................................................................................................... Operation of Mother Board and Daughter Board .............................................................. SH7708 Operating Conditions ........................................................................................... Q2 Operating Conditions ................................................................................................... Interfaces between SH7708 and Peripherals...................................................................... SH7708 and Peripheral Timing Charts .............................................................................. 15 15 18 19 20 Section 2 2.1 2.2 2.3 2.4 Section 3 3.1 3.2 3.3 3.4 3.5 3.6 NAV-DS4 Hardware...................................................................................... 21 21 23 23 35 48 63 i Section 1 Overview 1.1 System Specifications Table 1.1 summarizes the specifications of the navigation graphics demonstration system covered in this Application Note. Table 1.1 Item Product code Product name Mother board CPU RAM ROM Daughter board Graphics renderer UGM CD-ROM drive Embedded OS Navigation Graphics Demonstration System Specifications Specifications NAV-DS4 Navigation graphics demonstration system SH-3 (SH7708) EDO-DRAM (4 Mbyte) * 1 SRAM (256 kbyte) * 2 Flash memory (8 Mbyte) Q2 * 3 EDO-DRAM (4 Mbyte) Max. 10X (SCSI) * 4 HI-SH77 Data transfer speed: 1.5 Mbytes/sec Real-time multitasking OS conforming to ITRON specifications Ver. 2.02 Operating frequency: 30 MHz Internal operating frequency: 60 MHz Notes Graphics processing Map data Conforms to Navigation System Researcher's Association unified standard 16 bits/pixel: 60,000 colors Display colors 8 bits/pixel: 256 of 260,000 colors Display size Functions 320 x 240 5-level reduction/enlargement 4-directional smooth scrolling 360-degree rotation Dot units (up/down/left/right) Degree units (left rotation/ right rotation) Restoration and playback of YUV- Q2 hardware compressed natural images 1 Table 1.1 Item Speech processing Notes: 1. 2. 3. 4. 5. Navigation Graphics Demonstration System Specifications (cont) Specifications Functions Restoration and playback of ADPCM-compressed speech * 6 Notes SH3 software EDO: Extended Data Out--Dynamic Random Access Memory SRAM: Static Random Access Memory Q2: Quick 2D Graphics Renderer SCSI: Small Computer System Interface TRON: The Real Time Operating System Nucleus ITRON: Micro Industrial TRON 6. ADPCM: Adaptive Delta Pulse Code Modulation 2 1.2 System Configuration Figure 1.1 shows the system configuration. PC SCI I/F SH-3 (HD6417708) Key input block Q2 (HD64411) EDODRAM (16 Mbit x 2) Video output block TV screen DAC Display monitor Data bus Address bus CD-ROM drive with built-in speaker ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, SCI I/F FLASH (8 Mbit x 8) EDODRAM (16 Mbit x 2) Speech I/F DAC Line input Figure 1.1 System Configuration This demonstration system consists of a mother board holding a 32-bit RISC processor (SH7708: 60 MHz operation), a daughter board holding a graphics renderer (Q2: 30 MHz operation), and a CD-ROM drive that reads map data from a CD-ROM. In graphics processing, the SH7708 handles geometrical operations while the Q2 is responsible for rendering (drawing) operations. This reduces the processing load on the SH processor and improves system bus utilization. In speech processing, real-time regeneration of ADPCM speech data is possible by means of highspeed processing using the SH7708, enabling the number of dedicated devices used, and system cost, to be reduced. A real-time multitasking OS (operating system) conforming the ITRON specifications is incorporated, enabling both independent and parallel processing, and increasing the real-time capabilities of the system. 3 1.3 Drawing and Display Processing Procedure Figure 1.2 shows the map drawing flow in the NAV-DS4. The procedure is outlined below. 1. Management information, text, and map data are read from CD-ROM and stored in DRAM. 2. The SH7708 performs coordinate conversion on the map data and transfers the converted data to DRAM. 3. The SH7708 regenerates the display list (list of Q2 drawing commands) from the coordinate map data in DRAM, and transfers this to the Q2's UGM. 4. The SH7708 enables drawing execution by the Q2. The Q2. performs drawing in accordance with the display list. The SH7708 can execute other tasks while the Q2 is drawing. 5. The Q2 uses a double-buffering system with a drawing plane and a display plane , so that the display plane can be displayed during drawing. Display control is performed by the Q2 itself, without involving the SH7708. 6. When drawing ends, the drawing plane and display plane are switched. Screen switching control by the Q2 or the SH7708 can be selected. 7. In 8-bit/pixel mode, dot-unit data is converted to any of 256 colors from among 260,000 colors with the color palette (CPLT: ColPalet). In 16-bit/pixel mode, 60,000 colors can be displayed. 4 CD-ROM Map data, text, management information Monitor Flash memory DRAM OS (HI-SH77) Application Drawing library Coordinateconverted map data Map data (vector data format) Text data management information RGB 1 Map data, text, management information data transfer DRAM Map data, text, management information 2 Map data transfer SH microcomputer Coordinate conversion processing 3 Transfer of data after 7 1 D/A Q2 I/F Data bus CPLT Display unit DRAM Coordinate-converted map data before drawing CPU coordinate conversion 4 Transfer of data 2 Cache BSC SH microcomputer Display list (example) POLYGON4C . . LINE . . 3 before drawing SH microcomputer Display list regeneration processing 5 Display list transfer 4 5 Rendering unit Q2 Drawing processing 6 CD-ROM Display frame UGM (DRAM) Drawing frame Figure 1.2 Drawing and Display Processing Flow 6 Drawing in UGM UGM (DRAM) Data after drawing processing Q2 Display processing Display list 7 RGB signal output Display 5 1.4 External Appearance of NAV-DS4 Figure 1.3 shows an external view of the NAV-DS4. The NAV-DS4 consists of a mother board, a daughter board, a CD-ROM drive, and a monitor. The system is operated by means of operating key switches on the mother board. The operating keys are shown in figure 1.4. ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, CD-ROM drive with built-in speaker SCSI cable Q2 Mother board Daughter board Monitor Operating key switches SH7708 Figure 1.3 External View of NAV-DS4 SW0 SW1 Menu SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 Enter SW10 SW11 Wide area SW12 SW13 SW14 SW15 Detail Figure 1.4 NAV-DS4 Operating Key Panel Layout 6 1.5 Operating Procedures NAV-DS4 operating procedures are described here. Be sure to read the Usage Notes in the following section before operating the NAV-DS4. (1) Demonstration System Setup Procedure (See Figure 1.5) 1. Place the mother board, CD-ROM drive, and monitor on a table, desk, or similar flat surface as shown in the figure below. 2. Connect the daughter board to the mother board connector as shown in the figure. 3. Connect the SCSI cable and monitor cable. 4. Connect the power cords to the CD-ROM drive and monitor, plug them into a 100 VAC power outlet, and turn on the power. 5. Insert a Navigation System Research Association format CD-ROM in the prescribed position in the CD-ROM drive, and turn on the CD-ROM drive power. 6. Check steps 2 to 5 again, then plug the power cord connected to the mother board into a 100 VAC power outlet, and turn on the power. CD-ROM CD-ROM drive ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, Graphics processing unit power cable SCSI cable Power switch Power cord Monitor cable Daughter board Monitor Reset switch Q2 Mother board SH7708 Figure 1.5 NAV-DS4 Setup Procedure Diagram 7 (2) Operations after Setup (Examples) Display Screen SW Board Operations Initial screen on powering on No operation necessary Menu Description Initial screen When power is turned on, the initial screen is displayed. (Automatic) SuperH RISC engine Enter Map screen display No operation necessary Menu Map screen is displayed Enter After the initial screen is displayed, map data is read from the CD-ROM, drawing is performed, and the result is displayed on the screen. (Automatic) Map screen scrolling Up Menu Right Left Enter Scrolling (in any of 4 directions) continues while the up, down, left, or right key is pressed on the SW board, and stops when the key is released. Down 8 Display Screen SW Board Operations Map screen enlargement/reduction Description Menu Enter Wide area Detail Pressing the Detail key in the SW board displays a Reduce map enlarged by one level; pressing the Wide Area key displays a map reduced by one level. (5 enlargement/reduction levels available) Enlarge Map screen rotation Right rotation Left rotation Menu Enter Wide area Detail The map is rotated (in degree units) about the center of the screen while a rotation key on the SW board is pressed. Rotation stops when the key is released. Setting after rotation Menu Menu screen North-up display setting YUV MENU ADPCM Enter Wide area Detail Up Menu Enter After a map rotation demonstration, press the Menu key on the SW board, select "North-up display setting," and press the Enter key. The display will return to its state prior to the rotation. Down 9 (3) YUV Demonstration Operations Display Screen SW Board Operations Starting YUV demonstration Menu Up Fixed-north YUV MENU ADPCM Enter Wide area Detail Menu Description Enter Press the menu key to display the menu screen, and move the cursor to "YUV" with the up/down keys. The YUV demonstration is started by pressing the Enter key. Down YUV demonstration Menu Enter Wide area Detail The YUV natural image display demonstration is an automatic demonstration (no key input required). End of YUV demonstration Menu Enter Wide area Detail The automatic demonstration ends after approximately one minute, and the map screen is displayed again. 10 (4) ADPCM Demonstration Operations Display Screen SW Board Operations Starting ADPCM demonstration Menu Up Fixed-north YUV MENU ADPCM Enter Wide area Detail Menu Description Enter Down Press the menu key to display the menu screen, and move the cursor to "ADPCM" with the up/down keys. The ADPCM demonstration is started by pressing the Enter key. Phrase playback : Phrase playback keys 0 Fixed-north YUV MENU ADPCM 8 12 4 1 Menu 2 6 3 7 Wide area 5 Enter 9 13 10 14 11 Detail 15 Keys and corresponding phrases Key No. 2 4 5 6 8 10 12 13 14 Phrase Pin-pon O-yo-so Ko-no-sa-ki Ryou-ki-n-jo-no-sa-ki Meaning Chimes Approximately Ahead Beyond the tollbooth Pressing a phrase playback key plays the phrase assigned to that key. The phrase playback keys arranged so that a sentence can be constructed from four phrases (including chimes) by selecting a phrase from each row in turn, starting at the top row and moving downward. (The phrase arrangement is shown on the left.) Ichi-ki-ro-mei-to-ru-de 1 km Ni-ki-ro-mei-to-ru-de Ji-ta-ku-de-su 2 km Your home Mo-ku-te-ki-chi-de-su Your destination De-gu-chi-de-su The exit 11 Display Screen SW Board Operations Phrase recording/deletion Description Fixed-north YUV MENU ADPCM Menu Enter Wide area Detail Deletion Sentence playback Phrase recording Pressing the record key (Detail) will record the phrase played immediately before. The maximum number of recordings is set at 5. Pressing the delete key (Wide Area) will delete the phrase recorded immediately before. This is used to delete a phrase recorded by mistake. Fixed-north YUV MENU ADPCM Menu Pressing the sentence playback key (Enter) will play the recorded phrases as a sentence. Wide area Detail Enter Sentence playback Ending ADPCM demonstration Menu End Enter Wide area Detail Pressing the end key (menu) will end the ADPCM demonstration and display the map screen again. 12 1.6 Usage Notes 1. The power supply must be 100 VAC. The NAV-DS4 can be used in both 50 Hz and 60 Hz regions. 2. Always grip the plug when connecting or removing a power cord. 3. System damage, fire, or electric shock may result if a power cord, power cable, or flat cable is stretched, bent, extended, touched with wet hands, or inserted the wrong way round. 3. This system is a navigation demonstration unit, and is not covered by the same after-sales service warranty as other Hitachi products. 5. This system has been developed for use under normal environmental conditions (normal temperature and humidity). Special consideration has not been given to variations in environmental conditions or secular change. 6. If a demonstration does not operate normally (fails to work when power is turned on) or halts, press the Reset button. If this does not restore normal operation, disconnect and the reconnect the mother board power supply. If repeated use of these methods fails to restore normal operation, consult the manufacturer. 7. If the CD-ROM drive races out of control, turn of the power immediately. 8. Remove any dust from CD-ROM disks before use, as this may prevent data from being read. 13 Section 2 NAV-DS4 Software 2.1 Overview of Demonstration System The NAV-DS4 can execute the following four kinds of demonstration. 1. Map drawing and display demonstration (scrolling, zooming, rotation) Map data is read from a Navigation System Researcher's Association format CD-ROM and drawing and display are performed. The drawn map can be scrolled up, down, left, or right in dot units, enlarged or reduced in 5 stages, and rotated through 360 degrees. 2. Natural image (YUV image) display demonstration Natural image data that has undergone YUV compression is read from a Navigation System Researcher's Association format CD-ROM, high-speed conversion from YUV data to RGB data is performed using the Q2, and the result is displayed. During display, the converted data is enlarged/reduced, transformed, rotated, etc., using the high-speed drawing functions of the Q2. 3. ADPCM speech playback demonstration Speech data that has undergone ADPCM compression is read from a Navigation System Researcher's Association format CD-ROM, restored using ADPCM restoration middleware, and played via the speaker. Operations for these demonstrations are carried out by means of the key switches on the board. Table 2.1 lists the key functions, and figure 2.1 shows the overall NAV-DS4 demonstration software configuration. 15 Table 2.1 Key Functions Key Functions In Map Drawing To look above display map screen To look below display map screen To look to left of display map screen To look to right of display map screen Left (anticlockwise) rotation Right (clockwise) rotation Reduces display map Enlarges display map -- Displays menu screen -- -- -- -- -- -- In Menu Selection Selects item above Selects item below -- -- -- -- -- In ADPCM Demonstration Reads ADPCM speech data Reads ADPCM speech data Reads ADPCM speech data Reads ADPCM speech data -- -- Deletes data recorded immediately before Records selected data Outputs recorded data as sentence Ends ADPCM demonstration Reads ADPCM speech data Reads ADPCM speech data Reads ADPCM speech data Reads ADPCM speech data Reads ADPCM speech data -- Function Scrolling Mark Assigned No. 5 d 8 a Rotation 7 3 Enlargement/ reduction Wide area b Detail f 9 1 2 4 6 c e 0 -- Starts selected application -- -- -- -- -- -- -- Menu selection Enter MENU Other --: Invalid (pressing this key has no effect). 16 Start of demonstration Initialization NAV-DS4 demonstration CPU register settings Q2 register settings Set map display coordinate initial values Set mode decision variable to map mode Scroll keys Read CD-ROM Unit data Scroll processing Zoom keys Enlargement/ reduction processing Rotate keys Rotation processing Initial screen display Map drawing and display Key input Read CD-ROM Disk label Drawing parameters Unit management information Until Menu key input Until demonstration selection input Menu display Until reset or power-off Fixed-north display YUV demonstration Demonstration selection input YUV automatic demonstration ADPCM demonstration Until key input Menu display End of demonstration Until Menu key input Phrase output Phrase recording Key input Recorded phrase deletion Continuous playback of recorded phrases Figure 2.1 Overall NAV-DS4 Demonstration Software Configuration 17 2.2 Overall Software Configuration The NAV-DS4 incorporates an HI-SH77 real-time multitasking operating system conforming to the ITRON standard. Application programs are divided into processing units which are recorded in the kernel as "tasks." A maximum of 1023 tasks can be recorded. The kernel identifies and manages each task by means of a number from 1 to 1023 called the task ID. Tasks are activated via the kernel by means of asynchronously generated events such as key input operations. Interrupt handlers are also created to handle processing by interrupts. When an interrupt occurs, control is passed to an interrupt handler via an exception service routine in the kernel. The NAVDS4 uses a variety of interrupts, including key input, SCSI protocol control, and CD-ROM drive data reads. Having the operating system manage and control program flow in this way enables efficient, realtime demonstration operations to be implemented. The relationship between tasks and the kernel in the NAV-DS4 is illustrated in figure 2.2. For detailed specifications of the HI-SH77 operating system, refer to the HI-SH77 User's Manual and Construction Manual. Events Execution Kernel Interrupt handler Key input SCSI control System calls Execution Task 1 Application Execution System calls Task 2 Application Figure 2.2 Relationship Between Tasks and Kernel 18 2.3 Task Configuration Figure 2.3 shows the configuration of the tasks and interrupt handlers recorded in the kernel by the NAV-DS4. Kernel Key input control tasks Menu control task Scroll control task Rotation control task Enlargement/ reduction control task ADPCM control task Activation Menu control task Activation Scroll control task Activation Rotation control task Activation Enlargement/ reduction control task Activation ADPCM control task SCSI control block CD-ROM data read Interrupt handlers Mode control block Drawing/ display control block Drawing/ display control block ADPCM control block Drawing/ display control block CD-ROM control block Drawing/ display control block CD-ROM control block CD-ROM control block Activation Key input control task Speech output control Key no. Read YUV control block Activation : Indicates that the task is activated by issuance of a processing request (system call) to the kernel. Figure 2.3 Task and Interrupt Handler Configuration 19 2.4 Task Functions Table 2.2 summarizes the functions of the tasks and interrupt handlers recorded in the kernel by the NAV-DS4. Table 2.2 Task Name Key input control Summary of Functions (1/3) Function Issues a processing request (system call) to the kernel according to the key input, activating a task. The meaning of the keys depends on the key input mode. 1. In map mode (normal mode) Performs scroll control task activation by means of the up/down/left/right arrow keys, rotation control task activation by means of the rotate keys, enlargement/reduction control task activation by means of the Wide Area and Detail keys, and menu control task activation by means of the Menu key. 2. In menu operation mode Selects a menu display item by means of the up/down arrow keys, and activated the task corresponding to the item. 3. In ADPCM mode Performs activation of ADPCM control tasks corresponding to the up/down/left/right arrow keys, rotate keys, Wide Area and Detail keys, and Enter and Menu keys. Menu selection control Scroll control Draws the menu screen, and sets the menu operation mode, ADPCM demonstration mode, or speech synthesis demonstration mode from map mode according to the menu display items Reads map data from the CD-ROM, creates a display list, and draws a map in the Q2's multi-valued source area. In scroll movement processing, drawing is performed while updating coordinate locations from the multi-valued source area to the display area at each Q2 vertical sync signal. Performs coordinate conversion of map data by means of affine transformation processing, creates a display list, and draws in the display area with the Q2. Reads wide-area or detailed map data from the CD-ROM, creates a display list, and draws in the display area with the Q2. Reads ADPCM data from the CD-ROM, and performs data expansion processing. Rotation control Enlargement/ reduction control ADPCM control 20 Section 3 NAV-DS4 Hardware 3.1 Hardware Configuration The NAV-DS4 mother board consists of an SH7708 32-bit RISC microcomputer, various kinds of memory (an HM51W18165AJ-6 2-Mbyte DRAM, HN29WB800T-8 8-Mbyte flash memory, and HN67W1664-JP-12 256-kbyte static RAM), an HD151015 level shifter, Hitachi HD74LVC Series CMOS logic semiconductor devices, an RS-232C control IC, SCSI control IC, D/A converter, and three FPGAs (field programmable gate arrays) for key input control, SCSI control, and speech control. The daughter board comprises an HD64411F (Q2), HM5118165ATT-7 2-Mbyte DRAM, and HD153510 F50 (DAC) Hitachi semiconductor devices, and an RGB encoder. Tables 3.1 and 3.2 list the functions of the LSIs mounted on the NAV-DS4's mother board and daughter board, and figure 3.1 shows the hardware configuration. Table 3.1 Mounted LSI HD6417708F60A (SH7708) HM51W18165AJ-6 HM67W1664-JP-12 HN29WB800T-8 HD151015 HD74LVC244A HD74LVC245A HD74LVC08 HD74LVC00 HD74LVC32 HD74LVC04 HD74LVC14 EPF8282ATC100-3 EPF8452ATC100-3 EPM7032LC44-6 SYM53CF96-2 PD6376GS MAX233ACWP LTI086CT-3.3 LTI086CT-5 Functions of LSIs Mounted on Mother Board Device Function 32-bit RISC microcomputer 16Mbit-EDO-DRAM 1Mbit-SRAM 8Mbit-FLASH MEMORY Level shifter Unidirectional level shifter Bidirectional level shifter AND gate NAND gate OR gate Inverter (NOT) Schmitt trigger inverter Key input control (FPGA) Speech output (FPGA) SCSI control (FPGA) SCSI controller DAC RS-232C controller DD conversion LSI DD conversion LSI 21 Table 3.2 Mounted LSI Functions of LSIs Mounted on Daughter Board Device Function Quick 2D Graphics Renderer 16Mbit-EDO-DRAM 8bit-3chDAC Inverter (NOT) RGB encoder HD64411F (Q2) HM5118165ATT-7 HD153510F50 HD74LS04FP CXA1645 Mother board Daughter board 4 Mbytes UGM: DRAM (EDO mode) Image output block Personal computer RS-232C interface SCI 16 Mbits RGB encoder 16 Mbits TV monitor CD-ROM drive SCSI controller SCSI control FPGA CPU SH7708 Q2 DAC RGB monitor Address bus Data bus (32-bit) 8 Mbytes Flash memory 8 Mbits Expansion connector 16 Mbits 8 Mbits 8 Mbits 16 Mbits 8 Mbits 8 Mbits Key input FPGA 8 Mbits 8 Mbits 8 Mbits Expansion unit 4 Mbytes DRAM (EDO mode) 256 kbytes SRAM 1 Mbit 1 Mbit Speech output FPGA DAC Speech output block Speaker Key input block Note: The mother and daughter boards are connected by a board-to-board connector. Figure 3.1 Hardware Configuration 22 3.2 Operation of Mother Board and Daughter Board Mother board operations are as follows: 1. 2. 3. 4. 5. 6. The mother board is controlled by the SH7708. Controls the Q2 on the daughter board. Controls the external CD-ROM drive connected via a SCSI interface. Controls the 16 keys. Outputs 16-bit stereo speech data. When a PC is connected to the SCI connector, performs serial data communication with the PC. Daughter board operations are as follows: 1. Controls drawing processing and display processing by the Q2. 2. Outputs images to the TV monitor and RGB monitor. 3.3 SH7708 Operating Conditions (1) Operating Clock: In the NAV-DS4, a 30 MHz crystal oscillator is used for the SH7708's external input clock. The clock operating mode is set to mode 0 by external switching of the mode pins (MD0, MD1, and MD2). The frequency multiplication ratio of the SH7708's on-chip PLL circuit is set to x2, and the internal clock and peripheral clock division ratios are set to x1 and x1/2, respectively, in the frequency control register (FRQCR), so that the SH7708's internal clock (Io) is 60 MHz and its peripheral clock (Po) is 30 MHz. The SH7708 clock operating mode pin settings and corresponding operations used in the NAV-DS4 are shown in table 3.3, and the frequency control register (FRQCR) settings and corresponding operations in figure 3.2. Table 3.3 Clock Operating Mode Pin Settings and Operations Clock Input/ Output Supply Source/ Output EXTAL/ CKIO PLL Circuit 1 Divider 1 CKI0 On/Off Input Frequency Internal Clock ON PLL circuit 1 output EXTAL Frequency resulting from applying PLL circuit 1 frequency multiplication ratio and divider 1 division ratio to CKI0 Pin Names Clock Operating Mode MD2 MD1 MD0 Mode 0 0 0 0 23 Bit: 15 -- 14 -- 0 0 13 -- 0 0 12 -- 0 0 11 -- 0 0 10 -- 0 0 9 -- 0 0 8 7 6 5 4 3 IFC 1 0 0 2 IFC 0 0 0 1 0 CKO PLL P STC STC EN EN STBY 1 0 0 1 0 0 0 0 0 0 0 1 PFC PFC 1 0 0 0 0 1 Initial value Set value 0 0 : Clock is output from CKI0 pin. : PLL circuit 1 is not used. (As clock operating mode 0 is used, this bit is invalid.) : PLL standby is not performed. (As clock operating mode 0 is used, this bit is invalid.) * STC1, 0 = 01 : PLL circuit 1 frequency multiplication ratio is x2. * IFC1, 0 = 00 : Internal clock frequency division ratio is x1. * PFC1, 0 = 01 : Peripheral clock frequency division ratio is x1/2. * CKOEN = 1 * PLLEN = 0 * PSTBY = 0 Figure 3.2 Frequency Control Register (FRQCR) Settings and Operations (2) Pin Functions: The SH7708 has a number of multiplex pins. The multiplex pins and pin functions used by the NAV-DS4 are listed in table 3.4. 24 Table 3.4 Multiplex Pins and Pin Functions Function Pin No. Pin Name On Reset (in ) On Recovery after Reset (in ) (After elapse of 50 [ns]) Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus 5 8 9 10 11 12 13 14 84 85 86 103 104 108 109 117 118 119 120 123 124 126 129 130 D23 D22 D21 D20 D19 D18 D17 D16 MD2 MD1 MD0 MD4 MD3 _CS6 _CS5 _WE3 _WE2 PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 RXD TXD SCK _CE2B _CE2A _CE1B _CE1A DQMUU _ICIOWR DQMUL _ICIORD Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Operating mode (clock operating Serial data reception and break mode setting) state detection Operating mode (clock operating Serial data transmission and mode setting) break state sending Operating mode (clock operating Serial clock input/output and mode setting) I/O port Operating mode (area 0 bus width setting) Operating mode (area 0 bus width setting) Chip select 6 Chip select 5 Write strobe signal for D31-D24 Write strobe signal for D23-D16 CAS signal for D31-D24 CAS signal for D23-D16 Write strobe signal for D15-D8 Write strobe signal for D7-D0 _OE CAS signal for D7-D0 RAS signal Operating mode (entire-space endian setting) Operating mode (area 0 bus width setting) Operating mode (area 0 bus width setting) Chip select 6 Chip select 5 Write strobe signal for D31-D24 Write strobe signal for D23-D16 CAS signal for D31-D24 CAS signal for D23-D16 Write strobe signal for D15-D8 Write strobe signal for D7-D0 CAS signal for D7-D0 RAS signal Operating mode (entire-space endian setting) _CASHH _CAS2H _CASHL _CAS2L _WE1 _WE0 _CASLL _RAS MD5 DQMLU DQMLL _CAS _CE _RAS2 25 (3) Interrupt Handling: The NAV-DS4 uses IRL interrupts. The key input FPGA has an interrupt priority encoder function, and inputs levels to pins _IRL3-_IRL0 according to the _INRQ15-_INRQ0 pin priority levels shown in table 3.5. Figure 3.3 shows the interrupt priority encoder peripheral block diagram. Table 3.5 Pin _INRQ15 _INRQ14 _INRQ13 _INRQ12 _INRQ11 _INRQ10 _INRQ9 _INRQ8 _INRQ7 _INRQ6 _INRQ5 _INRQ4 _INRQ3 _INRQ2 _INRQ1 _INRQ15-_INRQ0 Pins and Interrupt Priority Order Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 _IRL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 _IRL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 _IRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 _IRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Low Interrupt Priority Order High 26 _INRQ15 Interrupt requests Expansion connector Q2 (daughter board) Speech output FPGA SCSI Key input FPGA _INRQ14 _INRQ13 _INRQ12 _INRQ11 _INRQ10 _INRQ9 _INRQ8 _INRQ7 _INRQ6 _INRQ5 SCSI control FPGA _INRQ4 _INRQ3 _INRQ2 _INRQ1 Interrupt priority encoder _IRL2 _IRL1 _IRL0 Figure 3.3 Interrupt Priority Encoder Peripheral Block Diagram CPU: SH7708 27 _IRL3 (4) Address Map: In the SH7708, the physical address space can be managed as seven separate areas, numbered 0 to 6, each of up to 64 Mbytes in size. The address map of the NAV-DS4 is shown in figure 3.4. The function and bus cycle state of each area are set with the bus control register (BCR1). Bus control register (BCR1) settings and corresponding operations are shown in figure 3.5. Data bus width set value [bits] H'00000000 Area 0 H'007FFFFF H'03FFFFFF H'04000000 H'04000041 Area 1 H'07FFFFFF H'08000000 H'0803FFFF Area 2 SCSI 16 Flash memory 8 Mbytes 32 Use * Programs * Character fonts * Monitor program * CD-ROM data reading SRAM 256 kbytes 32 * Monitor program work area H'0BFFFFFF H'0C000000 Area 3 H'0C3FFFFF H'0FFFFFFF H'10000000 H'103FFFFF Area 4 H'11000000 H'110005FF H'13FFFFFF H'14000000 H'14000007 H'14000013 H'14000023 H'17FFFFFF H'18000000 Area 6 Terminal address depends on what is connected. DRAM 4 Mbytes 32 * Program work area * Map data UGM (DRAM) 4 Mbytes Q2 1536 bytes 16 * Display list * Source/work area * Frame buffers * Q2 on-chip registers Speech output FPGA Key input FPGA 32 * Speech data output * Key input control * Interrupt priority encoder Area 5 Expansion connector 32 * Expansion ROM connection * Speech recognition unit connection H'1BFFFFFF Figure 3.4 NAV-DS4 Address Map 28 Bit: 15 -- 14 -- 0 0 13 -- 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 DRAM DRAM DRAM A5 A6 HIZ ENDI A0 A0 A5 A5 A6 A6 CNT AN BST1 BST0 BST1 BST0 BST1 BST0 TP2 TP1 TP0 PCM PCM 0 0 0/1 -- 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Initial value Set value 0 0 * HIZCNT = 0 * * * * * * : _RAS and _CAS signals become high-impedance in standby mode and when bus is released. A0BST1, 0 = 00 : Area 0 is accessed as ordinary memory. A5BST1, 0 = 00 : Area 5 is accessed as ordinary memory. A6BST1, 0 = 00 : Area 6 is accessed as ordinary memory. DRAMTP2, 1, 0 = 100 : Area 2 is accessed as ordinary memory, and area 3 as DRAM. A5PCM = 0 : Area 5 is accessed as ordinary memory. A6PCM = 0 : Area 6 is accessed as ordinary memory. Figure 3.5 Bus Control Register (BCR1) Settings and Operations (5) Memory Bus Width and Data Format: The SH7708's memory bus width is set for each space. Flash memory is connected to area 0, and mode pins MD3 and MD4 are set by an external switch to give a 32-bit bus width. The MD5 mode pin is set by an external switch to designate a big-endian data format. Mode pin settings and the corresponding operations are shown in table 3.6. The bus width of areas 1 to 6 is set in bus control register 2 (BCR2). Bus control register 2 (BCR2) settings and the corresponding operations are shown in table 3.6. However, the DRAM interface bus width is set in the individual memory control register (MCR). See (7) below for details of this register. Table 3.6 Mode Pin Settings and States Pin Name MD5 0 MD4 1 MD3 1 Endian Big Description Area 0 Bus Width 32 bits 29 Bit: 15 -- 14 -- 0 0 13 A6 SZ1 1 1 12 A6 SZ0 1 1 11 A5 SZ1 1 1 10 A5 SZ0 1 1 9 A4 SZ1 1 1 8 A4 SZ0 1 0 7 A3 SZ1 1 1 6 A3 SZ0 1 1 5 A2 SZ1 1 1 4 A2 SZ0 1 1 3 A1 SZ1 1 1 2 A1 SZ0 1 0 1 -- 0 0 0 PORT EN 0 0 Initial value Set value 0 0 * * * * * * * A6SZ1, 0 = 11 A5SZ1, 0 = 11 A4SZ1, 0 = 10 A3SZ1, 0 = 11 A2SZ1, 0 = 11 A1SZ1, 0 = 10 PORTEN = 0 : : : : : : : Area 6 bus width is set to 32 bits. Area 5 bus width is set to 32 bits. Area 4 bus width is set to 16 bits. Area 3 bus width is set to 32 bits. Area 2 bus width is set to 32 bits. Area 1 bus width is set to 16 bits. D23-D16 are not used as port pins. Figure 3.6 Bus Control Register 2 (BCR2) Settings and Operations (6) Wait Control: With some peripheral devices, data bus drive is not immediately switched off when the read signal from the SH7708 is switched off. Therefore, when consecutive accesses that span a number of areas are performed, or when a switch is made to write access immediately after read access, for example, there is a possibility of a data collision on the data bus. For this reason, wait control register 1 (WCR1) is set to provide automatic idle cycle insertion. Wait control register 1 (WCR1) settings and the corresponding operations are shown in figure 3.7. Wait state insertion cycle specifications for each area are made in wait control register 2 (WCR2). The data access pitch specification for burst access is also made in this register. The flash memory (HN29WB800T-8) connected to area 0, can be accessed in four cycles with two wait states inserted. Wait control register 2 (WCR2) settings and the corresponding operations are shown in figure 3.8. 30 Bit: 15 -- 14 -- 0 0 13 A6 IW1 1 0 12 A6 IW0 1 1 11 A5 IW1 1 0 10 A5 IW0 1 1 9 A4 IW1 1 0 8 A4 IW0 1 1 7 A3 IW1 1 0 6 A3 IW0 1 1 5 A2 IW1 1 0 4 A2 IW0 1 1 3 A1 IW1 1 0 2 A1 IW0 1 1 1 A0 IW1 1 0 0 A0 IW0 1 1 Initial value Set value 0 0 When switching from one area to another, or when switching from read access to write access in the same area * * * * * * * A6IW1, 0 = 01 A5IW1, 0 = 01 A4IW1, 0 = 01 A3IW1, 0 = 01 A2IW1, 0 = 01 A1IW1, 0 = 01 A0IW1, 0 = 01 : : : : : : : For area 6, one idle cycle is inserted. For area 5, one idle cycle is inserted. For area 4, one idle cycle is inserted. For area 3, one idle cycle is inserted. For area 2, one idle cycle is inserted. For area 1, one idle cycle is inserted. For area 0, one idle cycle is inserted. Figure 3.7 Wait Control Register 1 (WCR1) Settings and Operations Bit: 15 A6 W2 Initial value Set value 1 1 14 A6 W1 1 1 13 A6 W0 1 1 12 A5 W2 1 0 11 A5 W1 1 0 10 A5 W0 1 1 9 A4 W2 1 1 8 A4 W1 1 0 7 A4 W0 1 0 6 A3 W1 1 0 5 A3 W0 1 0 4 3 2 1 A0 W1 1 1 0 A0 W0 1 0 A1-2 A1-2 A0 W1 W0 W2 1 0 1 1 1 0 * * * * * * A6W2, 1, 0 = 111 A5W2, 1, 0 = 001 A4W2, 1, 0 = 100 A3W1, 0 = 00 A1-2W1, 0 = 01 A0W2, 1, 0 = 010 : : : : : : Number of wait states inserted for area 6 = 10 Number of wait states inserted for area 5 = 1 Number of wait states inserted for area 4 = 4 DRAM _CAS assertion width = 1 state Number of wait states inserted for areas 1 and 2 = 1 Number of wait states inserted for area 0 = 2 Figure 3.8 Wait Control Register 2 (WCR2) Settings and Operations 31 (7) Memory Control: In the NAV-DS4, EDO mode 16-Mbit DRAM (HM51W18165AJ-6) is connected to area 3. DRAM access in EDO mode requires a maximum of six cycles, with Tr and Trw cycles inserted, and a minimum of two cycles when consecutive addresses are accessed (using burst access). CAS-before-RAS refreshing is used. The _RAS and _CAS timing, burst control, address multiplex specifications, and refresh control specifications are made in the individual memory control register (MCR). Individual memory control register (MCR) settings and the corresponding operations are shown in table 3.9. The refresh period, presence or absence of interrupt generation, and the interrupt generation period, are specified in the refresh timer control/status register (RTCSR). The upper limit of the refresh timer counter (RTCNT) is set in the refresh timer constant register (RCTOR). Refresh timer control/status register (RTCSR) settings and the corresponding operations are shown in figure 3.10, and refresh timer constant register (RCTOR) settings and operations in figure 3.11. Bit: 15 14 13 12 11 10 9 8 7 -- 0 0 6 BE 0 1 5 4 3 2 1 0 TCP1 TCP0 RCD1 RCD0 TRWL TRWL TRAS TRAS 1 0 1 0 Initial value Set value 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 SZ AMX1 AMX0 RFSH RMO EDO DE MODE 0 1 0 1 0 0 0 1 0 0 0 1 Settings when DRAM is connected to area 3 * * * * * * * * * * TPC1, 0 = 01 RCD1, 0 = 01 TRWL1, 0 = 00 TRAS1, 0 = 01 BE =1 SZ = 1 AMX1, 0 = 10 RFSH = 1 RMODE = 0 EDOMODE = 1 : : : : : : : : : : Minimum number of cycles until _RAS is next asserted after being negated = 2 _RAS-_CAS assertion delay time = 2 cycles Not set _RAS assertion period in _CAS-before-_RAS refreshing = 3 cycles Burst access is performed Bus size is 32 bits. Address multiplex setting = 10-bit column address product used Refresh control specification = refresh performed _CAS-before-_RAS refreshing is performed. Set to EDO mode. (Data sampling timing for read cycle is CKI0 rise. _RAS signal negation timing is 1/2 machine cycle after CKI0.) Figure 3.9 Individual Memory Control Register (MCR) Settings and Operations 32 Bit: 15 -- 14 -- 0 0 13 -- 0 0 12 -- 0 0 11 -- 0 0 10 -- 0 0 9 -- 0 0 8 -- 0 0 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Initial value Set value 0 0 * CMF = 0 * * * * * : Status flag indicating that the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values match. CMIE = 0 : Interrupt requests by CMF are disabled. CKS2, 1, 0 = 001 : Selects refresh timer counter (RTCNT) input clock. (CKI0/4) OVF = 0 : Status flag indicating that the number of refresh requests indicated in the refresh count register (RFCR) has exceeded the number indicated by LMTS. OVIE = 0 : Interrupt requests by OVF are disabled. LMTS = 0 : Count limit value compared with the number of refresh requests indicated in the refresh count register (RFCR) (the count limit value is set to 1024). Figure 3.10 Refresh Timer Control/Status Register (RTCSR) Settings and Operations Bit: 15 -- Initial value Set value 0 0 14 -- 0 0 13 -- 0 0 12 -- 0 0 11 -- 0 0 10 -- 0 0 9 -- 0 0 8 -- 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 7 6 5 4 3 2 1 0 * Sets the upper limit of the RTCNT counter. (Lower 8 bits) * Calculation formula: RTCNT value = DRAM refresh period [s] refresh timer counter (RTCNT) period [s] 16 x 10-3 [s] 1024 [cycles] 1 (CKI0/4) [cycles] = = 30 x 106 16 x 10-3 x = 117.1875 H'75 1024 4 Figure 3.11 Refresh Time Constant Register (RTCOR) Setting and Calculation Formula 33 (8) Cache Memory: The SH7708 has on-chip cache memory. Use of 8-kbyte cache (normal mode) or 4-kbyte cache and 4-kbyte RAM (RAM mode) can be selected. A mixed instructions/data type 4-way set-associative configuration (normal mode) or 2-way set-associative configuration (RAM mode) can be selected. With the NAV-DS4, normal mode, using 8-kbyte cache memory, is set. The operating mode is set in the cache control register (CCR). Cache control register (CCR) settings and the corresponding operations are shown in table 3.12. Bit: 31 -- -- 0 0 5 RA 0 0 4 0 0 0 3 CF 0 1 2 -- 0 0 1 WT 0 0 0 CE 0 1 Initial value Set value 0 0 * * * * RA = 0 CF = 1 WT = 0 CE = 1 : : : : Normal mode (8-kbyte cache) V, U, and LRU bits of all cache entries are cleared to 0. Write-back mode Cache is used. Figure 3.12 Cache Control Register (CCR) Settings and Operations 34 3.4 Q2 Operating Conditions (1) Operating Clocks: There are two Q2 clocks, the drawing clock (CLK0) and the display clock (CLK1). The SH7708's CKI0 (30 MHz) output is input via a level shifter as the drawing clock (CLK0). For the clock operating mode, the mode pins (Mode0, Mode1, are Mode2) are set to mode 3 by means of an external switch. The Q2 clock operating mode pin settings used by the NAV-DS4, and the corresponding operations, are shown in table 3.3. The Q2 display clock (CLK1) is provided by a 14.318 MHz crystal oscillator. A display dot clock of 7.15 MHz (1/2 the CLK1 clock frequency) provided by the Q2's on-chip frequency divider is set by means of the Q2's display mode register (DSMR). See (2) below for details of this register. Table 3.3 Clock Operating Mode Pin Settings and States Pin Names MD2 0 MD1 1 MD0 1 Operation Multiplication On/Off Clock Operating Mode Mode 3 Internal Clock Same as external input clock Normal Off operating state (2) Interface Control: Overall Q2 control is performed by settings in a group of registers called the interface control registers (FRQCR). These registers are as follows: * * * * * * * * System control register (SYSR): Sets Q2 system operation. Status register (SR): Reads the Q2's internal status externally (read-only). Status register clear register (SRCR): Clears the corresponding status register contents. Interrupt enable register (IER): Sets the conditions for interrupt generation from the Q2 to the CPU. Memory mode register (MEMR): Sets the size and number of UGM memories. Display mode register (DSMR): Settings related to Q2 display operations. Rendering mode register (REMR): Settings related to Q2 drawing operations. Input data conversion mode register (IEMR): Settings related to format conversion of input data from the CPU. Interface control register (FRQCR) settings used by the NAV-DS4, and the corresponding operations, are shown in figures 3.13 to 3.18. 35 Bit: 15 14 13 12 -- 0 11 -- 0 10 -- 0 9 DC 8 RS 7 DBM 6 5 DMA 0 4 3 2 1 CCM 0 SRES DRES DEN Set value 0 0 1 0 or 1 0 or 1 0 or 1 1 or 0 0 0 0 0 0 * SRES = 0 * DRES = 0 DEN = 1 * DC = 0 =1 * RS = 0 =1 * DBM = 01 = 10 * DMA = 00 * CCM = 0000 : Command execution is enabled. : Display synchronization operation is started. The values stored in the UGM are output from the DD pin as display data. : Display frame buffer switching is not performed in manual display change mode. : Display frame buffer switching is performed in manual display change mode. : Rendering is not started. : Rendering is started. : Auto rendering mode is set. : Manual display change mode is set. : Normal mode is set. : Normal mode is set. Note: The values of DC, RS, and DBM are changed according to the processing executed. Figure 3.13 System Control Register (SYSR) Settings and Operations Bit: 15 14 13 12 11 10 9 8 -- 0 7 -- 0 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0 TVE FRE DME CEE VBE TRE CSE Set value 0 0 0 0 0 or 1 0 0 TVE = 0 FRE = 0 DME = 0 CEE = 0 VBE = 0 =1 * TRE = 0 * CSE = 0 * * * * * : : : : : : : : TV synchronization error flag interrupt is not enabled. Frame flag interrupt is not enabled. DMA flag interrupt is not enabled. Command error flag interrupt is not enabled. Vertical blanking flag interrupt is not enabled. Vertical blanking flag interrupt is enabled. Trap flag interrupt is not enabled. Command suspend flag interrupt is not enabled. Note: The value of VBE is changed according to the processing executed. Figure 3.14 Interrupt Enable Register (IER) Settings and Operations 36 Bit: 15 -- 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 -- 0 8 -- 0 7 -- 0 6 5 MES 4 3 MEA 2 1 -- 0 -- 0 Set value 0 0 1 1 0 1 0 * MES = 010 * MEA = 01 : Two 16-Mbit DRAMs are used for the UGM. : Number of row address bits = 10 Figure 3.15 Memory Mode Register (MEMR) Settings and Operations Bit: 15 -- Set value 0 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 8 7 TVM 0 0 6 5 SCM 0 or 1 0 0 1 4 3 2 REF 0 1 1 0 YCM DOT 0 1 : RGB/YCrCb conversion is not performed. : 1/2 the frequency of the clock input from the CLK1 pin is used as the display dot clock. * TVM = 0 : Sets master mode in which HSYNC, VSYNC, and ODDF are output. * SCM = 00 : Display output is set to non-interlace. = 10 : Interlace sync set for video monitor output. * REF = 0101 : Refresh timing set to 5 cycles. Note: The value of SCM is changed according to the processing executed. * YCM = 0 * DOT = 1 Figure 3.16 Display Mode Register (DSMR) Settings and Operations Bit: 15 -- Set value 0 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 -- 0 8 -- 0 7 -- 0 6 MWX 1 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 GBM 0 or 1 * MWX = 1 * GBM = 0 =1 : The UGM X-direction logical coordinate space is set to 1024 pixels. : Rendering data bit configuration is set to 8 bits/pixel (in map data processing). : Rendering data bit configuration is set to 16 bits/pixel (in natural image data processing). Note: The value of GBM is changed according to the processing executed. Figure 3.17 Rendering Mode Register (REMR) Settings and Operations 37 Bit: 15 -- 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 -- 0 8 -- 0 7 -- 0 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 YUV 0 or 1 0 Set value 0 0 * YUV = 00 = 10 : Sets normal mode in which data conversion is not performed. : Sets mode in which YUV-RGB data conversion is performed. (In YUV data processing) Note: The value of YUV is changed according to the processing executed. Figure 3.18 Input Data Conversion Mode Register (IEMR) Settings and Operations (3) Memory Control: The Q2 uses a UGM (unified graphics memory) architecture, in which data of different formats (such as frame buffer area data and font pattern area data) is stored and managed in the same memory. The configuration of the UGM connected to the Q2 is determined by settings in a group of registers called the memory control registers (MECR). These registers are as follows: * * * * * * Display size register (DSR): Sets the display screen size. Display start address register (DSAR): Sets the frame buffer area. Display list start address register (DLSAR): Sets the display list area. Multi-valued source area start address register (SSAR): Sets the multi-valued source area. Work area start address register (WSAR): Sets the work area. DMA transfer start address register (DMASR): Sets the transfer destination UGM address in DMA transfer. * DMA transfer word count register (DMAWR): Sets the number of words to be transferred in DMA transfer. Since DMA transfer is not used by the NAV-DS4, no DMA transfer start address register (DMASR) or DMA transfer word count register (DMAWR) settings are made. Memory control register (MECR) settings, and the corresponding operations, are shown in figures 3.19 to 3.23. UGM memory maps are shown in figure 3.24, and 3.25. 38 Bit: 15 -- 14 -- 0 14 -- 0 13 -- 0 13 -- 0 12 -- 0 12 -- 0 11 -- 0 11 -- 0 10 -- 0 10 -- 0 9 8 7 6 5 DSX 4 3 2 1 0 Set value Bit: 0 15 -- 0 9 -- 0 1 8 0 7 0 6 1 5 1 4 DSY 1 3 1 2 1 1 1 0 Set value 0 0 1 1 1 0 1 1 1 1 * DSX = 0100111111 : The number of display screen dots in the horizontal direction (X direction) is set to 320. * DSY = 011101111 : The number of display screen dots in the vertical direction (Y direction) is set to 240. Figure 3.19 Display Size Register (DSR) Settings and Operations Bit: 15 -- Set value Bit: 0 15 -- Set value 0 14 -- 0 14 -- 0 13 -- 0 13 -- 0 12 -- 0 12 -- 0 11 -- 0 11 -- 0 10 -- 0 10 -- 0 9 -- 0 9 -- 0 8 -- 0 8 -- 0 7 -- 0 7 -- 0 0 0 0 0 6 0 5 0 4 6 5 4 3 DSA0 0 3 DSA1 0 1 0 0 0 2 0 1 0 0 2 1 0 * DSA0 = 0000000 * DSA1 = 0000100 : The frame buffer 0 start address is set to UGM address 0h. : The frame buffer 1 start address is set to UGM address 40000h (in 8-bit/pixel mode). Note: The values of the frame buffer 0 and 1 start addresses are changed according to the processing executed. Figure 3.20 Display Start Address Register (DSAR) Settings and Operations 39 Bit: 15 -- 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 -- 0 8 -- 0 7 -- 0 6 5 4 3 DLSAH 2 1 0 Set value Bit: 0 0 0 0 1 0 0 1 15 14 13 12 11 10 DLSAL 9 8 7 6 5 4 -- 3 -- 0 2 -- 0 1 -- 0 0 -- 0 Set value 0 0 0 0 0 0 0 0 0 0 0 0 * DLSAH = 0001001 : Bits A22 to A16 of the display list start address. * DLSAL = 00000000000 : Bits A15 to A5 of the display list start address. The display list start address is set to UGM address 90000h (in initialization). Note: The value of the display list start address is changed according to the processing executed. Figure 3.21 Display List Start Address Register (DLSAR) Settings and Operations Bit: 15 -- Set value 0 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 -- 0 8 -- 0 7 -- 0 0 0 6 5 4 3 2 1 0 -- 0 0 0 SSAH 1 0 * SSAH = 001000 : The multi-valued source area start address is set to UGM address 100000h (in 8-bit/pixel data processing). = 000000 : The multi-valued source area start address is set to UGM address 0h (in natural image data processing). Note: The value of SSAH is changed according to the processing executed. Figure 3.22 Multi-Valued Source Area Start Address Register (SSAR) Settings and Operations Bit: 15 -- Set value 0 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 -- 0 8 -- 0 7 -- 0 0 0 0 6 5 4 3 WSAH 1 0 0 0 2 1 0 * WSAH = 0001000 : The work area start address is set to UGM address 80000h (in 8-bit/pixel data processing). = 0011000 : The work area start address is set to UGM address 180000h (in natural image data processing). Note: The value of WSAH is changed according to the processing executed. Figure 3.23 Work Area Start Address Register (WSAR) Settings and Operations 40 8 bits/pixel, screen size = 320 x 240, 16-Mbit memory x 1 319 H'00000 F0 240 256 F1 496 512,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 576,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Work ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1023 H'40000 Binary source H'80000 H'90000 H'100000 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Display list ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1024,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 0 319 639 959 1 1264 239 2 Buffer area 4 1504 479 5 6 Multi-valued source 7 1744 719 8 9 3 2047 Figure 3.24 UGM Memory Map (8-Bit/Pixel Mode) 41 16 bits/pixel, screen size = 320 x 240, 16-Mbit memory x 1 319 H'00000 F0 240 256 F1 496 512 YUV data expansion area 2 Multi-valued source YUV data expansion area 1 679 1023 H'80000 752 768,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Work ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 784,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Display list ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Binary source H'1FFFFE 1023,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, H'180000 H'188000 Figure 3.25 UGM Memory Map (16-Bit/Pixel Mode) (4) Display Control: The Q2 performs double-buffering control that switches alternately between the display area and drawing area located in the UGM, making it possible to alternate between high-speed drawing processing and display processing. Q2-controlled display timing settings are made in a group of registers called the display control registers (DSCR). These registers are as follows: * Display window register (DSWR): Sets display screen horizontal and vertical output timing. * Horizontal synchronization pulse width register (HSWR): Sets the low-level pulse width of the horizontal sync signal. * Horizontal scan cycle register (HCR): Sets the horizontal scan cycle. * Vertical synchronization position register (VSPR): Sets the start position of the vertical sync signal. * Vertical scan cycle register (VCR): Sets the vertical scan cycle. * Display off output register (DOOR): Sets the display data to be output when the display is off. * Color detection register (CDER): Detects display color data. Display control register (DSCR) settings used by the NAV-DS4, and the corresponding operations, are shown in figures 3.26 to 3.31. 42 Bit: 15 -- 14 -- 0 14 -- 0 14 -- 0 14 -- 0 13 -- 0 13 -- 0 13 -- 0 13 -- 0 12 -- 0 12 -- 0 12 -- 0 12 -- 0 11 -- 0 11 -- 0 11 -- 0 11 -- 0 10 -- 0 10 -- 0 10 -- 0 10 -- 0 9 8 7 6 5 HDS 4 3 2 1 0 Set value Bit: 0 15 -- 0 9 0 8 0 7 1 6 0 5 HDE 1 4 1 3 1 2 1 1 0 0 Set value Bit: 0 15 -- 0 9 1 8 1 7 0 6 0 5 VDS 1 4 1 3 1 2 1 1 0 0 Set value Bit: 0 15 -- 0 9 0 8 0 7 0 6 0 5 VDE 1 4 0 3 0 2 0 1 0 0 Set value 0 0 1 0 0 0 0 0 0 0 0 * * * * HDS = 0001011110 HDE = 0110011110 VDS = 0000010000 VDE = 0100000000 : : : : The horizontal display start position is set to 5eh. The horizontal display end position is set to 19eh. The vertical display start position is set to 10h. The vertical display end position is set to 100h. Note: HDS and HDE are set in dot clock units, and VDS and VDE in raster line units. Figure 3.26 Display Window Register (DSWR) Settings and Operations Bit: 15 -- Set value 0 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 9 -- 0 8 -- 0 7 -- 0 0 0 1 6 5 4 3 HSW 1 1 1 1 2 1 0 * HSW = 0011111 : The low-level pulse width of the horizontal sync signal is set to 1fh. Note: HSW is set in dot clock units. Figure 3.27 Horizontal Synchronization Pulse Width Register (HSWR) Settings and Operations 43 Bit: 15 -- 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 9 8 7 6 5 HC 4 3 2 1 0 Set value 0 0 0 1 1 1 0 0 0 1 1 0 * HC = 111000110 : One horizontal scan cycle, including the horizontal retrace line interval, is set to 1c6h. Note: HC is set in dot clock units. Figure 3.28 Horizontal Scan Cycle Register (HCR) Settings and Operations Bit: 15 -- Set value 0 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 0 1 0 0 0 9 8 7 6 5 VSP 0 0 0 1 1 4 3 2 1 0 * VSP = 0100000011: The start position of the vertical sync signal is set to 103h. Note: VSP is set in dot clock units. Figure 3.29 Vertical Synchronization Position Register (VSPR) Settings and Operations Bit: 15 -- Set value 0 14 -- 0 13 -- 0 12 -- 0 11 -- 0 10 -- 0 0 1 0 0 0 9 8 7 6 5 VC 0 0 1 1 0 4 3 2 1 0 * VC = 100000110 : One vertical scan cycle, including the vertical retrace line interval, is set to 106h. Note: VC is set in raster line units. Figure 3.30 Vertical Scan Cycle Register (VCR) Settings and Operations 44 Bit: 15 -- 14 -- 0 14 13 -- 0 13 12 -- 0 12 11 -- 0 11 10 -- 0 10 9 -- 0 9 -- 8 -- 0 8 -- 0 7 6 5 4 DOR 3 2 1 -- 0 -- 0 0 -- 0 Set value Bit: 0 15 0 7 0 6 0 5 0 4 DOB 0 3 0 2 0 1 -- DOG Set value 0 0 0 0 0 0 0 0 1 1 1 1 1 0 * DOR = 000000 * DOG = 000000 * DOB = 011111 : The R component of the data output in the display-off state is set to 0h. : The G component of the data output in the display-off state is set to 0h. : The B component of the data output in the display-off state is set to 1fh. Figure 3.31 Display Off Output Register (DOOR) Settings and Operations (5) Input Data Control: The NAV-DS4 uses the YUV-RGB data conversion function of the Q2 to implement high-speed natural image drawing. To control YUV data conversion by the Q2, settings are made in a group of registers called the input data control registers (IDCR). These registers are as follows: * Image data transfer start address register (ISAR): Sets the transfer destination address for image data transfer. * Image data size register (IDSR): Sets the image data size. * Image data entry register (HCR): Used to input the image data to be converted, Input data control register (IDCR) settings used by the NAV-DS4, and the corresponding operations, are shown in figures 3.32 to 3.34. 45 Bit: 15 -- 14 -- 0 14 13 -- 0 13 12 -- 0 12 11 -- 0 11 10 -- 0 10 9 -- 0 9 8 -- 0 8 ISAL 7 -- 0 7 6 5 4 3 ISAH 2 1 0 Set value Bit: 0 15 0 6 0 5 0 4 0 3 0 2 0 1 0 0 -- Set value 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 : Image data transfer destination physical address bits A22 to A16 are set to 0h. * ISAL = 001010000000000 : Image data transfer destination physical address bits A15 to A0 are set to 2800h. Note: The values of ISAH and ISAL are changed according to the processing executed. * ISAH = 0000000 Figure 3.32 Image Data Transfer Start Address Register (ISAR) Settings and Operations Bit: 15 -- Set value Bit: 0 15 -- Set value 0 14 -- 0 14 -- 0 13 -- 0 13 -- 0 12 -- 0 12 -- 0 11 -- 0 11 -- 0 0 10 -- 0 1 0 0 1 0 9 1 8 0 7 1 6 10 9 8 7 6 5 IDSX 1 5 IDSY 0 0 0 0 0 0 0 4 1 3 0 2 0 1 0 0 4 3 2 1 0 * IDSX = 00101101000 : The image data X-direction size is set to 360 dots. * IDSY = 1001000000 : The image data Y-direction size is set to 240 dots. Note: IDSX and IDSY are set in pixel units. Figure 3.33 Image Data Size Register (IDSR) Settings and Operations Bit: 15 14 13 12 11 10 9 8 IDE Set value 7 6 5 4 3 2 1 0 * IDE : Used to input image data. Figure 3.34 Image Data Entry Register (IDER) Setting and Operation 46 (6) Color Palette: The NAV-DS4 uses the Q2's on-chip color palette for map drawing in 8bit/pixel mode, enabling simultaneous display of 256 colors out of a total of 260,000. Color palette settings are made using a group of 256 registers called color palette registers (CP000-CP255). Colors are set using 6 bits for each of R, G, and B. Color palette register values are cleared when drawing is performed after changing from 8-bit/pixel mode to 16-bit/pixel mode, so the settings must be made again when returning to 8-bit/pixel mode. Color palette register (CP000-CP255) settings used by the NAV-DS4 are shown in figure 3.35. Bit: 15 -- Set value Bit: 0 15 14 -- 0 14 13 -- 0 13 12 -- 0 12 11 -- 0 11 10 -- 0 10 9 -- 0 9 -- 0 0 0 8 -- 0 8 -- 0 0 0 0 7 0 6 7 6 5 4 3 2 1 -- 0 3 0 2 0 1 -- 0 0 0 0 -- 0 0 -- 0 R000 0 5 0 4 B000 0 0 G000 Set value 0 0 0 0 Bit: 15 -- 14 -- 0 14 13 -- 0 13 12 -- 0 12 11 -- 0 11 10 -- 0 10 9 -- 0 9 -- 8 -- 0 8 -- 0 7 6 5 4 3 2 1 -- 0 -- 0 0 -- 0 R255 0 7 0 6 0 5 0 4 B255 0 0 0 0 0 0 0 3 0 2 Set value Bit: 0 15 0 1 -- 0 G255 Set value 0 0 0 0 0 0 0 Note: Due to space limitations, it is not possible to show all the color palette set values. Figure 3.35 Color Palette Register (CP000-CP255) Settings 47 3.5 Interfaces between SH7708 and Peripherals (1) Interface to 5 V Operation Units: The NAV-DS4 includes both 5 V and 3.3 V operation units. As the SH7708 operates at 3.3 V, it is connected directly to the 3.3 V operation units, but is connected to the 5 V operation units via a level shifter. A decoder using TLL circuitry is provided to prevent signal contact between the 3.3 V and 5 V operation units (bidirectional bus only). Figure 3.36 shows a block diagram of the interface between the SH7708 and the 5 V operation units. 3.3 V VccA DiR VccB _G 5V CKIO A0 Level shifter: HD151015 Unidirectional level shifter: HD74LVC244A B0 Output bus A Y Y A 3.3 V Vcc CPU: SH7708 Input bus _1G and _2G are fixed at GND so that the 5 V units can be accessed at all times (access is always enabled). _1G _2G Bidirectional bus RD/_WR _CS6 _CS5 _CS1 B T/_R Bidirectional level shifter: HD74LVC245A A 3.3 V Vcc _OE Decoder Figure 3.36 Block Diagram of Interface to 5 V Operation Units 48 5 V units (2) Flash Memory Interface: The NAV-DS4 is equipped with 8 Mbytes of flash memory (HN29WB800T-8), used in byte mode, to hold programs and character fonts. Figure 3.37 shows a block diagram of the interface between the SH7708 and the flash memory. A TTL decoder is provided to allow separate access to the upper 4 Mbytes and lower 4 Mbytes of the 8-Mbyte memory. Figure 3.38 shows a logic diagram of the flash memory decoder, and table 3.8 gives the corresponding truth table. Data bus D0:31 Address bus A2:21 (A2:21) (D24:31) (A2:21) Flash memory: HN29WB800T-8 A-1:18 _CE _OE A-1:18 _CE _OE I/O 0:7 Flash memory: HN29WB800T-8 I/O 0:7 (HH-0) (A2:21) (HH-1) (D16:23) (A2:21) (D16:23) I/O 0:7 I/O 0:7 I/O 0:7 (D0:7) (D8:15) CPU: SH7708 Flash memory: HN29WB800T-8 A-1:18 _CE _OE CSO (A2:21) A-1:18 _CE _OE I/O 0:7 (HL-0) (A2:21) (HL-1) (D8:15) Flash memory: HN29WB800T-8 A-1:18 _CE _OE A-1:18 _CE _OE I/O 0:7 (LH-0) (A2:21) (A2:21) (LH-1) (D0:7) Flash memory: HN29WB800T-8 Address bus A22, A23 _RD A-1:18 _CE A-1:18 _CE _OE I/O 0:7 _FLAOE0 _FLAOE1 Decoder _OE (LL-0) (LL-1) Figure 3.37 Block Diagram of Flash Memory Interface 49 Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 (D24:31) _RD A23 _FLAOE0 Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 H'00000000 to H'003FFFFF Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 Flash memory: HN29WB800T-8 _FLAOE0 CPU: SH7708 _FLAOE0 _FLAOE0 Addresses _FLAOE1 A22 Decoder _FLAOE1 _FLAOE1 _FLAOE1 Addresses H'00400000 to H'007FFFFF Figure 3.38 Flash Memory Decoder Logic Diagram Table 3.8 Flash Memory Decoder Truth Table Input _RD L L L L H H H H A23 L L H H L L H H A22 L H L H L H L H Output _FLAOE0 _FLOE1 L H H H H H H H H L H H H H H H Address H'00000000-H'003FFFFF selection Address H'00400000-H'007FFFFF selection 50 (3) DRAM Interface: The NAV-DS4 is equipped with two EDO mode 16-Mbit DRAMs (HM51W18165AJ-6), giving a total of 4 Mbytes, for use as working memory, used with a 32-bit bus width. CAS-before-RAS mode is used for refreshing. Figure 3.39 shows a block diagram of the interface between the SH7708 and the DRAMs. Data bus D0:31 Address bus A2:11 (A2:11) A0:9 _RAS RD/_WR _CASHH _CASHL CPU: SH7708 _RAS _WE DRAM: HM51W18165AJ-6 I/O 0:15 _UCAS _LCAS _OE (A2:11) DRAM: HM51W18165AJ-6 A0:9 _RAS _WE _CASLH _CASLL I/O 0:15 _UCAS _LCAS _OE Figure 3.39 Block Diagram of EDO-DRAM Interface (D16: 15) 51 (D16: 31) (4) SRAM Interface: The NAV-DS4 is equipped with two 1-Mbit SRAMs (HM67W1664JP-12), giving a total of 256 kbytes, for use as working memory, used with a 32-bit bus width. Figure 3.40 shows a block diagram of the interface between the SH7708 and the SRAMs. Data bus D0:31 Address bus A2:17 (A2:17) (D24:31) I/O 9:16 (D16:23) I/O 1:8 I/O 9:16 (D0:7) I/O 1:8 (D8:15) A0:15 _CS2 _RD RD/_WR _CS _OE _WE _UB _LB _WE3 CPU: SH7708 _WE2 (A2:17) A0:15 _CS _OE _WE _UB _LB _WE1 _WE0 Note: The area inside the dotted line is TTL circuitry. Figure 3.40 Block Diagram of SRAM Interface 52 SRAM: HM67W1664JP-12 SRAM: HM67W1664JP-12 (5) Q2-UGM Interface: The NAV-DS4 has a Q2 (HD64411F) and two EDO mode 16-Mbit DRAMs (HM5118165ATT-7) (4 Mbytes), used as the UGM, mounted on its daughter board. A 30 MHz clock is supplied from the SH7708 on the mother board as the drawing clock (CLK0). Accesses from the SH7708 to the Q2 are of two kinds: UGM accesses and accesses to the Q2's on-chip registers. The decoder for access selection consists of TTL circuitry. Figure 3.41 shows a logic diagram of the UGM/Q2 on-chip register selection decoder, and table 3.9 gives the corresponding truth table. As UGM access is performed by CPU transfer, and does not use the DMA controller, the Q2's _DACK pin is fixed high and the _DREQ pin is left open. Figure 3.42 shows a block diagram of the Q2 peripheral interface. _CS4 A24 CPU: SH7708 _CS0 Q2: HD64411F _CS1 Decoder Figure 3.41 UGM/Q2 On-Chip Register Selection Decoder Logic Diagram Table 3.9 Input _CS4 L L H H A24 L H L H UGM/Q2 On-Chip Register Selection Decoder Truth Table Output _CS0 L H H H _CS1 H L H H UGM selection Q2 on-chip register selection 53 A1:22 D0:15 _CS4 A24 _RD _WE0 _WE1 3.3 V Open Decoder *1 A1:22 D0:15 _CS0 _CS1 DISP CDE ODDF _HSYNC/_EXHSYNC _VSYNC/_EXVSYNC _RD _CSYNC _WE0 DD0:17 _WE1 FCLK DCLK _DACK _DREQ _WAIT *2 MA0:11 MD0:15 Display unit _WAIT CPU: SH7708 5V Pull-up resistor 10 k H H L Open CKIO MODE0 MODE1 MODE2 TEST _MWE _WE _UCAS _LCAS _OE _MUCAS _MLCAS _MOE DRAM: HM5118165ATT-7 DRAM: HM5118165ATT-7 A0:9, NC6:7 Q2: HD64411F D0:15 Level 30 MHz CLK0 shifter Crystal oscillator 14.31818 MHz _MRAS0 _RAS CLK1 470 pF CAP0 A0:9, NC6:7 _IRL0 _IRL1 _IRL2 _IRL3 _RESET Interrupt priority encoder _IRL _WE _UCAS _RESET 3.3 V CPUVcc 5V _LCAS _OE D0:15 RESET switch Vcc PLLVcc CPUGND GND PLLGND _MRAS1 _RAS UGM Notes: 1. UGM/Q2 on-chip register selection decoder 2. Wait signal from expansion connector Figure 3.42 Block Diagram of Q2 Peripheral Interface 54 (6) Q2-display Unit Interface: An 8-bit 3-channel DAC (HD153510F50) and an RGB/video encoder (CXA1645) are mounted on the daughter board, and connected to the Q2, as the display unit. The display unit generates analog RGB signals and NTSC video signals from the 18-bit output from Q2 pins DD0 to DD17. Control of the resolution, the horizontal and vertical sync signals, etc., is performed by the Q2. A 14.318 MHz signal is supplied from the crystal oscillator on the daughter board as the display clock (CLK1). Figure 3.42 shows a block diagram of the display unit. RGB output _HSYNC/_EXHSYNC _VSYNC/_EXVSYNC C1; 0.1 F A Vcc R_IN G_IN B_IN RGB encoder: CXA1645M GND R_OUT G_OUT B_OUT CV_OUT Video output YTRAP C2; 33 pF TV monitor Q2: HD64411F _CSYNC SYNC_IN FCLK SC_IN DD0:17 DA2:7 DB2:7 DC2:7 8-bit DAC: FHD153510F50 IOA IOB IOC DISP CLK1 DCLK _BLANK DOTCK Crystal oscillator 14.31818 MHz * Connect C1 (0.1 F) and C2 (33 PF) between AVcc and GND and to the YTRAP pin. If C1 and C2 are not provided, color drift may occur in NTSC display images. * With NTSC video output, set bit 5 = 1 and bit 4 = 0 (interlace sync mode) as the scan mode (SCM) setting in the Q2 display mode register (DSMR). Figure 3.43 Q2 Display Unit Block Diagram 55 (7) Speech Output: Using the FPGA, the NAV-DS4's speech output unit converts 32-bit stereo speech data (16 bits each for left and right channels) transferred from the SH7708 into serial speech data, which it outputs via a DAC. The devices used are a PD6376GS (manufactured by NEC) for the DAC and an EPF8452ATC100-3 for the FPGA. Figure 3.44 shows the speech output unit peripheral block diagram, and figure 3.45 shows an internal block diagram of the speech output FPGA. The main components of the FPGA are a clock generator, an interrupt controller, and a parallel-toserial converter. The clock generator generates clocks LRCK (selected by the status register) and CLK (7.5 MHz) for output to the DAC, using CLK_SH (30 MHz). The interrupt controller issues interrupt requests to the SH7708 in synchronization with LRCK. Each time an interrupt is generated, the SH7708 transfers parallel data to the 32-bit buffer in the FPGA. The transferred data is converted to serial data by the parallel-to-serial converter in synchronization with CLK. Then data synthesis is performed, and serial speech data is output to the DAC. Figure 3.46 and 3.47 show the functions of the speech output FPGA registers. Figure 3.48 shows the speech output unit timing chart. Board side Off-board Digital circuitry 5V Analog circuitry 5V A.Vdd A0:7 D0:31 A0, A2:7 D0:31 _CS5 _RD _WR 30 MHz CLK_SH CPU: SH7708 _CS5 _RD _WE0 CKIO _IRL0 _IRL1 _IRL2 _IRL3 Speech output FPGA: EPF8452ATC100-3 D.Vdd LRCK LRCK CLK CLK Interrupt _INRQ11 _IRL priority encoder _RESET SI SI D.GND _RESET RESET switch Figure 3.44 Speech Output Unit Peripheral Block Diagram 56 DAC: PD6376GS A.GND Speaker Interrupt request signal _INRQ11 Interrupt controller Serial data left/right identification signal 44.1/22.025 11.025/8.0 kHz LRCK 7.5 MHz CLK Serial data read clock Clock generator Upper 16-bit parallel-to-serial converter D0:31 Speech data / FPGA internal register read/ write data 32-bit buffer Data synthesis Lower 16-bit parallel-to-serial converter SI Serial speech data Figure 3.45 Speech Output FPGA Internal Block Diagram D29 . . . D2 ... ... Bit Bit name Initial value D31 DR31 0 D30 DR30 0 D1 DR1 0 D0 DR0 0 The receive register is used to input speech data. It is a write-only register, and _IRL is cleared after data is written. Figure 3.46 Receive Register Function 57 Bit Bit name Initial value D31 . . . D4 Not used 0 D3 11E 0 D2 22E 0 D1 44E 0 D0 DAE 0 The status register is used for LRCK signal selection (see table below). DAE is used as ADPCM_SW. 11E 22E 44E DAE Set value 0 0 1 -- -- 0 0 0 1 -- 0 0 0 0 1 0 1 1 1 1 Function LRCK signal is not output. (ADPCM_SW: Off) LRCK signal is output at 8 [kHz]. LRCK signal is output at 11.025 [kHz]. LRCK signal is output at 22.05 [kHz]. LRCK signal is output at 44.1 [kHz]. Figure 3.47 Status Register Settings and Functions 30.0 MHz CLK_SH APSD_SW 44.1 kHz, 22,05 kHz, 11,05 kHz, or 8.0 kHz LRCK _IRL Transmit data = 16 bits CLK 7.5 MHz Transmit data = 16 bits SI D31 D16 D15 D0 D31 ADPCM_SW is generated by setting the DAE flag in the status register. LRCK, CLK, and _IRL are generated using CLK_SH. Figure 3.48 Speech Output Unit Timing Chart 58 (8) SCSI Interface: The NAV-DS4 reads map data from a an external CD-ROM drive containing a navigation CD-ROM, and performs drawing and display based on this data. A SCSI interface is used for the external CD-ROM drive, and CPU transfer is used for data transfer. An SYM53CF962 (manufactured by Symbiosis Logic) is used for the SCSI controller, and an EPM7032LC44-6 (manufactured by Altera) is mounted as the control FPGA. Since the SCSI interface uses littleendian mode, the upper and lower bytes of the device are reversed for connection to the SH7708. Figure 3.49 shows the SCSI controller peripheral block diagram. A half-pitch 50-pin connector (female, shielded) is mounted, and single-end connection is used. CPU data D0:15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Off-board Board side SCSI data DB0:15 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8 0 15 14 13 12 11 10 9 PAD0:7 DB0:7 D0:7 D0:7 Upper and lower data bytes reversed D8:15 A1:4 Data bus D0:15 DB8:15 SCSI connector: NHS050-032-BS2 A0:3 CD-ROM drive Address bus A0:25 SCSI: SYM53CF96-2 _WR A0, A2:7 _CS _DBWR _DACK DREQ _CS DWE _DACK DREQ A0,A2:7 _CS1 _RD _WE0 _WE1 _INRQ4 Interrupt priority encoder _INRQ10 INT _CS1 _RD _WE0 _WE1 5V Pull-up resistor 10 k SCSI control FPGA: EPM7032LC44-6 Mode0 Mode1 Set to mode 3 DIP switch _INT _IRL0 _IRL1 _IRL2 _IRL3 CLK RESET 30 MHz CKIO _RESET RESET switch Figure 3.49 SCSI Controller Peripheral Block Diagram 59 CPU: SH7708 _RD (9) Key Input Interface: The NAV-DS4 is equipped with 16 switches mounted on the mother board, with an EPF8282ATC100-3 (manufactured by Altera) used as the control FPGA. Momentary switching is used, in which the on-state is maintained while the switch is pressed. The FPGA has an interrupt priority encoder function. Figure 3.50 shows the key input FPGA peripheral block diagram. 5V Pull-up resistors 10 k x 16 Switch layout on board 0 4 8 12 1 5 9 13 2 6 10 14 3 7 11 15 SW0:15 SW0 ... SW15 AD0:5 D0:7 Address bus A0:5 Data bus D0:7 _RD _CS5 5V Key input FPGA: EPF8282ATC100-3 Pull-up resistors 10 k x 8 RD CS5 DSW0:7 5V Pull-up resistors 10 k x 15 ... Interrupt priority encoder Interrupt requests _INRQ1 . . . . _INRQ15 _IRL3 _IRL2 _IRL1 _IRL0 Figure 3.50 Key Input FPGA Peripheral Block Diagram 60 CPU: SH7708 DIP switch ... (10) Serial Communication Interface (SCI): The NAV-DS4 can perform serial data exchange with a PC using the SH7708's on-chip SCI. An MAX233ACWP (manufactured by Maxim) is used as the RS-232C driver. An RS-232C standard D-sub 9-pin (male) connector is used. A DIP switch allows switching between cross and straight connection. Figure 3.51 shows the SCI peripheral block diagram. Off-board (female) Board (male) side SCI connector (RS-232C): 17AE-23090A-9750 (male) T1OUT DCD RxD TxD DTR GND DSR RTS CTS RI 10 F + - Cross/ straight switching 5V DIP switch T2OUT T1IN MD1/TXD Personal computer SCI interface RS-232C driver: MAX233 ACWP R1IN R2IN Vcc C2+ C2+ C2- C2- GND GND T2IN R1OUT R2OUT C1+ C1- V- V- V+ MD2/RXD SCI Figure 3.51 SCI Peripheral Block Diagram CPU: SH7708 61 (11) Expansion Connectors: The NAV-DS4 is equipped with board-to-board expansion connectors that provide for functional expansion by means of hardware. The expansion connectors are intended for connection to 5 V systems, and a level shifter is used between the connected system and the SH7708. Two HIF7C-80PA-1.27DSAL connectors (80-pin plug type, manufactured by Hirose) are used, and HIF7C-80DA-1.27DSAL units are required on the receptacle side. Figure 3.52 shows the expansion connector peripheral block diagram. Board (plug) side Off-board (receptacle) Address bus A0:25 _IRQOUT CKIO _BS RD/_WR _RD _CS0 _CS1 _CS2 _CS5 _CS6 _WE3 _WE2 _CASHH _CASHL _WE1 _WE0 _CASLH _CASLL _RAS CKE _RESET Address bus A0:25 _IRQOUT CKIO _BS RD/_WR _RD _CS0 _CS1 _CS2 _CS5 _CS6 _WE3 _WE2 _CASHH _CASHL _WE1 _WE0 _CASLH _CASLL _RAS CKE _RESET CPU: SH7708 5V RESET switch Data bus D0:31 _IOIS16 _WAIT Data bus D0:31 _IOIS16 _WAIT Wait signal from Q2 _IRL0 _IRL1 _IRL2 _IRL3 Interrupt priority encoder 5V _INRQ2 _INRQ7 _INRQ13 Figure 3.52 Expansion Connector Peripheral Block Diagram 62 Expansion connector B: HIF7C-80PA-1.27DSAL Expansion connector A: HIF7C-80PA-1.27DSAL 3.6 SH7708 and Peripheral Timing Charts (1) SH7708 Flash Memory Read Timing T1 33.3ns CKIO tAD 15ns A25:0 tCSD1 14ns _CS0 tRSD 14ns _RD tRDS1 12ns (a) Time until CPU data read setup D31:0 104.55 ns tACC 80ns(max) tCE 80ns(max) _CE tOE 40ns(max) _OE (_FLAOE) Decode circuit delay: 12 ns I/O (b) Time until flash memory outputs data 95 [ns] (worst case) Flash memory Tw1 33.3ns Tw2 33.3ns T2 33.3ns tRDH1 0ns CPU (c) CPU data hold time tRDH1 0ns (d) Flash memory data hold time tOH 0ns 63 In case of 2-wait/4-cycle access to SH7708 flash memory: 1) Data setup time: (a) Time until CPU data read setup T1 + Tw1 + Tw2 + (T2/2) - tRDS1 = 33.3 + 33.3 + 33.3 + (33.3/2) - 12 = 104.55 [ns] (b) Time until flash memory outputs data Viewed from address: t AD + tACC = 15 + 80 = 95 [ns] Worst case Viewed from _CE: tCSD1 + tCE = 14 + 80 = 94 [ns] Viewed from _OE: (T1/2) + tRSD + decode circuit delay + t OE = (33.3/2) + 14 + 12 + 40 = 82.65 [ns] Thus, (b) < (a), and the CPU setup time is satisfied. 2) Data hold time: (c) CPU data hold time tRDH1 = 0 [ns] (d) Flash memory data hold time tOH = 0 [ns] Thus, (d) (c), and the CPU data hold time is satisfied. From 1) and 2), 2-wait/4-cycle access is possible. 64 (2) SH7708 SRAM Read Timing T1 33.3ns CKIO tAD 15ns A25:0 tCSD1 14ns _CS2 tRDH1 0ns Tw 33.3ns T2 33.3ns RD/_WR tRSD 14ns _RD tRDS1 12ns D31:0 (a) Time until CPU data read setup 71.25ns tOE 6ns (max) tAA 12ns (max) tACS 12ns (max) tLB, tUB 6ns(max) _LB, _UB TTL circuit delayviewed from _RD: 6 ns (b) Time until SRAM outputs data 42.65 [ns] (worst case) tOH 3ns (d) SRAM data hold time tRDH1 0ns I/O SRAM CPU tRWD 14ns (c) CPU data hold time 65 In case of 1-wait/3-cycle read access to SRAM: 1) Data setup time: (a) Time until CPU data read setup T1 + Tw + (T2/2) - tRDS1 = 33.3 + 33.3 + (33.3/2) - 12 = 71.25 [ns] (b) Time until SRAM outputs data Viewed from address: t AD + tAA = 15 + 12 = 27 [ns] Viewed from _CS2: tCSD1 + tACS = 14 + 12 = 26 [ns] Viewed from _RD: (T1/2) + t RSD + tOE = (33.3/2) + 14 + 6 = 36.65 [ns] Viewed from _LB, _UB: (T1/2) + tRSD + TTL circuit delay + t LB , tUB = (33.3/2) + 14 + 6 + 6 = 42.65 [ns] Worst case Thus, (b) < (a), and the CPU setup time is satisfied. 2) Data hold time: (c) CPU data hold time tRDH1 = 0 [ns] (d) SRAM data hold time (viewed from address) tOH = 3 [ns] Thus, (d) (c), and the CPU data hold time is satisfied. From 1) and 2), 1-wait/3-cycle read access is possible. 66 (3) SH7708 SRAM Write Timing T1 33.3ns CKIO tAD 15ns A25:0 tCSD1 14ns _CS2 tRWD 14ns RD/_WR tWED 14ns _WEn (a) Time until CPU data write setup D31:0 tWDD1 17ns (c) CPU data hold time tWDH3 0ns Tw 33.3ns T2 33.3ns TTL circuit delay viewed from _WEn: 6 ns tLBW,tUBW(min) 9ns Delay: 6 ns _LB, _UB tDW 6ns (b) Time until SRAM inputs data 39.65 [ns] (worst case) tOH 3ns (d) SRAM data hold time I/O SRAM CPU 67 In case of 1-wait/3-cycle write access to SRAM: 1) Data setup time: (a) Time until CPU data write setup tWDD1 = 17 [ns] (b) Time until SRAM inputs data Viewed from _LB, _UB: (T1/2) + tWED + TTL circuit delay + t LBW, tUBW - tDW = (33.3/2) + 14 + 6 + 9 - 6 = 39.65 [ns] Worst case Thus, (b) > (a), and the CPU setup time is satisfied. 2) Data hold time: (c) CPU data hold time (viewed from _WEn) tWDH1 = 0 [ns] (d) SRAM data hold time tDH = 0 [ns] Thus, (d) (c), and the CPU data hold time is satisfied. From 1) and 2), 1-wait/3-cycle write access is possible. 68 (4) SH7708 DRAM Normal Access Read Timing (EDO Mode) _CAS Read data assert cycle latch cycle Tc1 Tc2 33.3ns 33.3ns _RAS precharge interval (Tpc) (Tpc) 33.3ns 33.3ns _RAS assert cycle Tr Trw 33.3ns 33.3ns CKIO tAD 15ns tAD 15ns Row address tAD 15ns tAS 0ns Row address tRWD 14ns tAH 10ns tAD 15ns tAS 0ns Column address tRWH 0ns tRWD 14ns tAH 10ns A25-16 A15-0 RD/_WR 15ns 15ns _RAS tCASD1 15ns tCASD1 15ns _CASxx tRDS2 tRDH2 12ns 6ns (a) Time until CPU data read setup D31-0 CPU tRASD1 tRASD2 Tr + Trw + Tc1 + Tc2 - tRDS2 = 121.2 ns tRC 104ns tRAS 60ns tRP 40ns _RAS tCSH 48ns tRCD 20ns tRSH 15ns tCRP 5ns In case of 2-wait/5-cycle access to DRAM, (b) (a), and the setup time is satisfied. _UCAS, _LCAS tRAD 15ns tASR 0ns tRAH 10ns R tRCHR 60ns tRCS 0ns tASC 0ns tCAS 10ns tRAL 30ns tCAL 30ns tCAH 10ns C tRCH 0ns A9:0 _WE tCAC 15ns tAA 30ns tRAC 60ns (b) Time until DRAM outputs data tOHR 3ns Dout Viewed from _RAS: Tr / 2 + tRASD1 + tRAC = 91.65 ns Viewed from _CAS: Tr + Trw + Tc1 / 2 + tCASD1 + tCAC = 113.25 ns Worst case Viewed from address: Tr + Trw + tAD + tAA = 111.6 ns DRAM 69 (5) SH7708 DRAM Normal Access Write Timing (EDO Mode) _CAS assert cycle Tc1 33.3ns _RAS precharge interval (Tpc) (Tpc) 33.3ns 33.3ns _RAS assert cycle Tr Trw 33.3ns 33.3ns Tc2 33.3ns CKIO tAD 15ns tAD 15ns Row address tAD 15ns tAS 0ns Row address tRWD 14ns tAH 10ns tAD tAS tAH 10ns A25-16 15ns 0ns Column address A15-0 tRWH 0ns tRWD 14ns tRASD1 15ns tRASD2 15ns tCASD1 15ns tCASD1 15ns tWDH3 0ns tWDH1 0ns _RAS _CASxx D31-0 (a) Time until CPU data write setup tWDS tWDD2 0ns 16ns CPU RD/_WR Tr + Trw + tWDD2 = 33.3 + 33.3 + 16 = 82.6 ns tRC 104ns tRAS 60ns tRP 40ns In case of 2-wait/5-cycle access to DRAM, (b) > (a), and the setup time is satisfied. _RAS tCSH 48ns tRCD 20ns tCRP 5ns tRSH 15ns tCAS 10ns _UCAS, _LCAS tASR 0ns A9:0 R tWCS 0ns C tWCH 10ns _WE tDS 0ns tDH 10ns (b) Time until DRAM inputs data Dout Tr + Trw + Tc1 / 2 + tCASD1 - tDS = 33.3 + 33.3 + (33.3/2) + 15 - 0 = 98.25 ns 70 DRAM tRAH 10ns tASC 0ns tCAH 10ns (6) SH7708 DRAM Burst Access Read Timing (EDO Mode) Burst cycle = 2 cycles _CAS Read data _CAS Read data assert cycle latch cycle assert cycle latch cycle Tc1 33.3ns Tc2 33.3ns Tc1 33.3ns Tc2 33.3ns _RAS assert cycle Tr 33.3ns Trw 33.3ns _RAS precharge interval (Tpc) 33.3ns (Tpc) 33.3ns CKIO tAD 15ns tAD 15ns Row address tAD tAS 15ns 0ns tAD tAS 15ns 0ns Column address tAH 10ns tAD 15ns Column address tRWH 0ns tRWD 14ns tAH 10ns A25-16 A15-0 tRWD 14ns Row address tAH 10ns RD/_WR tRASD1 15ns tRASD2 15ns _RAS tCASD1 15ns tCASD1 15ns tCASD1 15ns tCASD1 15ns _CASxx tRDS2 tRDH2 12ns 6ns tRDS2 tRDH2 12ns 6ns D31-0 tRASP 10000ns(max) tRP 40ns _RAS tCSH 48ns tCAS 10ns tCP 10ns tRSH 15ns tCAS 10ns tCRP 5ns _UCAS, _LCAS tCAL 30ns tASR 0ns tRAH 10ns tASC 0ns tCAH 10ns C tRCS 0ns tASC 0ns tCAH 10ns C tRCH 0ns A9:0 R _WE tCAC 15ns tCAC 15ns tRAC 60ns tAA 30ns tAA 30ns tCPA 35ns tOHR 3ns Dout DRAM tRAL 30ns tCAL 30ns CPU 71 (7) SH7708 DRAM Burst Access Write Timing (EDO Mode) Burst cycle = 2 cycles _CAS assert cycle Tc2 33.3ns Tc1 33.3ns Tc2 33.3ns _RAS assert cycle Tr 33.3ns Trw 33.3ns _CAS assert cycle Tc1 33.3ns _RAS precharge interval (Tpc) 33.3ns (Tpc) 33.3ns CKIO tAD 15ns tAD 15ns Row address tAD tAS 15ns 0ns tAD tAS 15ns 0ns Column address tAH 10ns tAD 15ns Column address tRWH 0ns tRWD 14ns tAH 10ns A25-16 A15-0 tRWD 14ns Row address tAH 10ns RD/_WR tRASD1 15ns tRASD2 15ns _RAS tCASD1 15ns tCASD1 15ns tWDD2 tWDH3 0ns 16ns tCASD1 15ns tCASD1 15ns tWDH3 0ns tWDH1 0ns _CASxx 16ns tWDS tWDD2 0ns D31-0 tRASP 10000ns tRP 40ns _RAS tCSH 48ns tRCD 20ns tCAS 10ns tCP 10ns tRSH 15ns tCAS 5ns tCRP 5ns _UCAS, _LCAS tASR 0ns tRAH 10ns tASC 0ns tCAH 10ns C tWCS 0ns tASC 0ns tCAH 10ns C tWCH 10ns A9:0 R _WE tDS 0ns tDH 10ns tDS 0ns tDH 10ns Dout 72 DRAM CPU (8) SH7708 Q2 Read Timing T1 33.3ns T2 33.3ns T3 33.3ns T4 33.3ns Tw 33.3ns Tw 33.3ns T5 33.3ns T1 33.3ns 33.3ns 33.3ns CKI0 tAD 15ns tAD 15ns A25:0 tCSD1 14ns tCSD2 14ns 10ns tAH _CS4 14ns tRSD tRSD 14ns _RD tRDS1 12ns D15:0 Decode circuit delay: 12 ns _CS1, 0 _RD Q2 tRDDH 4ns tWAD 20ns tWAD 20ns _WAIT tRDDWS 10ns tRDDRS 66.6ns D15:0 73 CPU (9) SH7708 Q2 Write Timing T1 33.3ns T2 33.3ns T3 33.3ns T4 33.3ns Tw 33.3ns Tw 33.3ns T5 33.3ns T1 33.3ns 33.3ns 33.3ns CKI0 tAD 15ns tAD 15ns A25:0 tCSD1 14ns tCSD2 14ns 10ns tAH _CS4 14ns tRSD tWED 14ns _WEn tWDD1 17ns D15:0 Decode circuit delay: 12 ns _CS1, 0 _WEn Q2 tWRDH 0ns tWAD 20ns tWAD 20ns _WAIT tWRDWS 0ns tWRDES 66.6ns D15:0 74 CPU SH Graphics/Speech Processing Demonstration System NAV-DS4 Application Note Publication Date: 1st Edition, January 1998 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Documentation Center Hitachi Microcomputer System Ltd. Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. |
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