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HI-7159A
Data Sheet January 1999 File Number 2936.4
Microprocessor-Compatible, 5- 1/2 Digit A/D Converter
The Intersil HI-7159A is a monolithic A/D converter that uses a unique dual slope technique which allows it to resolve input changes as small as 1 part in 200,000 (10V) without the use of critical external components. Its digital autozeroing feature virtually eliminates zero drift over temperature. The device is fabricated in Intersil' proprietary low noise BiMOS process, resulting in exceptional linearity and noise performance. The HI-7159A's resolution can be switched between a high resolution 200,000 count (51/2 digit) mode, and a high speed 20,000 count (41/2 digit) mode without any hardware modifications. In the 41/2 digit uncompensated mode, speeds of 60 conversions per second can be achieved. The HI-7159A is designed to be easily interfaced with most microprocessors through either of its three serial and one parallel interface modes. In the serial modes, any one of four common baud rates is available.
Features
* 200,000 Count A/D Converter * 2V Full Scale Reading With 10V Resolution * 15 Conversions Per Second in 51/2 Digit Mode * 60 Conversions Per Second in 41/2 Digit Mode * Serial or Parallel Interface Modes * Four Selectable Baud Rates * Differential Analog Input * Differential Reference Input * Digital Autozero
Applications
* Weigh Scales * Part Counting Scales * Laboratory Instruments
Ordering Information
PART NUMBER HI3-7159A-5 TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld PDIP PKG. NO. E28.6
* Process Control/Monitoring * Energy Management * Seismic Monitoring
Pinout
HI-7159A (PDIP) TOP VIEW
Functional Block Diagram
AGND VCC 1 INT OUT 2 INT IN 3 BUF OUT CREFGUARD CREFCREF+ 4 5 6 28 SEL 27 XTAL 26 DGND 25 P7/BRS1 24 P6/BRS0 23 P5/SAD3 22 P4/SAD2 21 P3/SAD1 20 P2/SAD0 19 P1/SMS1 18 P0/SMS0 17 CS/SAD4 16 WR/TXD 15 RD/RXD VREF HI VREF LO VIN HI VIN LO CREF RINT BUFFER CINT
VEE
VCC
XTAL
DGND
INTEGRATOR +
COMPARATOR +
-
-
CONTROL SECTION AND LATCHES
BUS INTERFACE UNIT I/O PORTS UART
8 BIT BUS
+
CS WR RD
7 CREF+ 8 GUARD VREF HI 9
-
VREF LO 10 AGND 11 VIN HI 12 VIN LO 13 VEE 14
ANALOG SWITCHES
ANALOG STATE MACHINE SEL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HI-7159A
Absolute Maximum Ratings
Supply Voltage VCC to GND (AGND/DGND) . . . . . . . . . . . . . . -0.3V < VCC < +6V VEE to GND (AGND/DGND) . . . . . . . . . . . . . . +0.3V < VCC < -6V Digital Pins, (pins 15 - 28) . . . . . . . . DGND -0.3V < VD Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature, TSTG . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: VCC = +5V, VEE = -5V, DGND = 0V, AGND = 0V, VREF HI = +1.00000V, VREF LO = AGND, fCLOCK = 2.40MHz, RINT = 400k, CINT = 0.01F, TA = 25oC, VIN LO = AGND, CREF = 1.0F, 51/2 Digit Compensated Mode, Unless Otherwise Specified TEST CONDITIONS 0V to +2V (Notes 2, 3, 4, 5) -2V to 0V (Notes 2, 3, 4, 5) MIN 99996 -1 VIN LO-2V VIN HI = 0.00000V VIN HI = 2.00000V TYP 0.0015 0.0015 100000 0 3 5 1 0 0.1 MAX 0.0035 0.0035 100003 1 1 VIN LO +2V 0.1 UNITS % FS % FS Counts Counts V V Counts A pF Counts Counts/oC Counts/oC
PARAMETER Integral Non-Linearity, INL
Ratiometric Reading Zero Error, ZE Voltage Range of VIN LO Input (Pin 13), VIN LO Voltage Range of VIN HI Input (Pin 12), VIN HI Common Mode Rejection, CMR Input Leakage Current, IIN Input Capacitance, CIN Noise (Peak-to-Peak Value, Not Exceeded 95% of Time), eN Zero Drift, TC(ZE) Full Scale Error Tempco, TC(FSE) Supply Range, VSUPPLY VCC VEE VCC Supply Current, ICC VEE Supply Current, IEE Digital GND Current, IDGND Analog GND Current, IAGND VCC , VEE Power Supply Rejection, PSR Guard Driver Pins 5, 8 Output Current, IOGD NOTES:
VIN HI = VREF HI = 1.00000V VIN HI = 0.00000V -2V VIN HI - VIN LO 2V -2V VIN HI - VIN LO 2V VIN HI = VIN LO = -3V to +3V Pins 9, 10, 12, 13, VIN = +3V, -3V Pins 9, 10, 12, 13
+4.75 -4.75 VIN HI = VREF HI = 1.00000V, VCC = +4.75V, VEE = -4.75V to VCC = +5.50V, VEE = -5.50V VIN (Pins 9, 10) = +3V, -3V 10
+5.0 -5.0 +3 3 -
+5.5 -5.5 10 4.5 5.5 -
V V mA mA mA A Counts A
2. All typical values have been characterized but are not production tested. 3. Not production tested, guaranteed by design and characterization. 4. Reference adjusted for correct full-scale reading. 5. VIN = VIN HI - VIN LO .
2
HI-7159A
DC Electrical Specifications
Test Conditions: VCC = +5V, VEE = -5V, DGND = 0V, AGND = 0V, VREF HI = +1.00000V, VREF LO = AGND, fCLOCK = 2.40MHz, RINT = 400k, CINT = 0.01F, TA = 25oC, VIN LO = AGND, CREF = 1.0F, 51/2 Digit Compensated Mode, Unless Otherwise Specified TEST CONDITIONS Pins 15-25, 28 Pins 15-25, 28 Pins 16, 18-25, IOL = 1.6mA Pins 16, 18-25, IOH = -400A All Digital Drivers In High Impedance State, Parallel Mode. CS = VCC , VIN = 0V, VCC VIN = 0V, VCC Pins 15, 17-25, 28 Pin 16 Input Pullup Current (Pins 18-25), IPU Pins 18-25 at DGND SEL = DGND (Serial Modes) MIN 2.0 2.4 TYP MAX 0.8 0.4 10 1 UNITS V V V V A A pF pF A
PARAMETER Input Low Voltage, VIL Input High Voltage, VIH Output Low Voltage, VOL Output High Voltage, VOH Three-State Leakage Current, Pins 18-25, IOL Leakage, Pins 15-17, 28, IIN Input Capacitance, CIN
-
5 10 -5
AC Electrical Specifications
TA = 0oC to 75oC; Test Conditions: VCC = +4.75V, VEE = -5.00V (Note 8), DGND = 0V, AGND = 0V, VIN LO = AGND , VREF HI = +1.00000V, VREF LO = AGND , fCLOCK = 2.40MHz, RINT = 400k , CINT = 0.01F, VIL = 0V, VIH = 4V, VOL = VOH = 1.5V, tr = tf < 10ns, 51/2 Digit Compensated Mode, Unless Otherwise Specified TEST CONDITIONS MIN 0 50 150 20 (Note 7) CL = 50pF, VO = 1.5V 25 (Note 7) (Note 7) (Note 7) 5/fCLOCK 200 60 40 100 TYP MAX 100 70 300 UNITS ns ns ns ns ns ns ns s ns ns ns ns ns
PARAMETER CS Setup/Hold of WR, t1 WR Setup of Data In, t2 WR Pulse Width, t3 Data Hold After WR, t4 CS Setup/Hold of RD, t5 RD to Data Out, t6 RD to Hi-Z State, t7 WR to RD, WR to WR, tA RD to WR, tB RXD Setup of Data In, tC Data Hold After EXT CLK, tD EXT CLK to DATA OUT, tE CS Setup of TXD, tf NOTES:
6. All typical values have been characterized but are not production tested. 7. Not production tested, guaranteed by design and characterization. 8. All AC characteristics are guaranteed for VCC = +5V 15%, VEE = -5V 15%, over TA = 0oC to 75oC.
3
HI-7159A Timing Waveforms
CS t1 WR t2 P0 - P7 t4 DATA IN t3 t1 WR tA RD
FIGURE 1A. WRITE
FIGURE 1B. WRITE TO READ CYCLE
WR tA
FIGURE 1C. WRITE TO WRITE CYCLE
CS t5 RD t6 P0 - P7 t7 DATA OUT WR t5 RD tB
FIGURE 1D. READ
FIGURE 1E. READ TO WRITE CYCLE FIGURE 1. PARALLEL MODE TIMING
CLK (PIN 15) RXD/TXD (PIN 16) D0 tC tD RXD/TXD (PIN 16) D0 D1 tE D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 (HI-7159A RECEIVING)
(HI-7159A TRANSMITTING)
FIGURE 2A. SERIAL MODE 0 TIMING
CS (SERIAL MODE 1) tf TXD OR RXD START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP
DATA CLOCK 0 BIT DETECTOR SAMPLE TIME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NOTE: All input timing shown is defined at 50% points. FIGURE 2B. SERIAL MODE TIMING
4
HI-7159A Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SYMBOL VCC INT OUT INT IN BUF OUT CREF - Guard CREF CREF + CREF + Guard VREF HI VREF LO AGND VIN HI VIN LO VEE RD/RXD WR/TXD CS/SAD4 P0/SMS0 P1/SMS1 DESCRIPTION Positive 5V Power Supply for analog and digital sections. Integrator Output; external component terminal. Integrator Input; external component terminal. VIN HI Voltage Buffer Output; external component terminal. Reference Capacitor guard ring terminal (negative). Reference Capacitor negative terminal. Reference Capacitor positive terminal. Reference Capacitor guard ring terminal (positive). Positive Reference Input terminal. Negative Reference Input terminal. Analog Ground (0V). Positive Analog Input Voltage terminal. Negative Analog Input Voltage terminal. Negative 5V Power Supply for analog section. Parallel Read; serial receive (modes 1 and 2), serial clock (mode 0). Parallel Write; serial transmit (modes 1 and 2), serial receive/transmit (mode 0). Chip Select (parallel and serial modes 0 and 1), serial address bit 4 (mode 2). Parallel I/O Port (P0); serial mode select pin. Parallel I/O Port (P1); serial mode select pin.
MODE Serial Mode 0 Serial Mode 1 Serial Mode 2 Reserved
SMS0 0 0 1 1
SMS1 0 1 0 1
20 21 22 23 24 25
P2/SAD0 P3/SAD1 P4/SAD2 P5/SAD3 P6/BRS0 P7/BRS1
Parallel I/O Port (P2); serial address bit 0. Parallel I/O Port (P3); serial address bit 1. Parallel I/O Port (P4); serial address bit 2. Parallel I/O Port (P5); serial address bit 3. Parallel I/O Port (P6); serial baud rate select. Parallel I/O Port (P7); serial baud rate select.
BAUD RATE 300 1200 9600 19200
BRS0 0 0 1 1
BRS1 0 1 0 1
26 27 28
DGND XTAL SEL
Digital Ground (0V). Oscillator Out; crystal connection pin (other crystal pin connected to VCC). Select pin for parallel or serial operation. Parallel SEL = 1 Serial Modes SEL = 0
5
HI-7159A Theory of Operation
The HI-7159A attains its 51/2 digit resolution through the use of multiple integrations per conversion, creating an effective integrator swing greater than the supply rails, and a successive integration technique used to measure the residue on the integrator capacitor to 51/2 digit accuracy. In the 51/2 digit mode, the input voltage is integrated and reference de-integrated four times. This results in a count with the same effective resolution as a single integration with four times the integrator swing amplitude. In this manner effective integrator swings of 12V or greater can be achieved with 5V supplies. The four integrations are spaced so that commonmode signals whose frequency is an integer multiple of fCRYSTAL/40,000 are rejected. In the 41/2 digit mode, only one input integration is performed, thus the minimum frequency for common-mode rejection becomes fCRYSTAL/10,000. These first four integrations measure the input voltage to an resolution of 31/2 digits, or 1mV/count. To achieve 51/2 digit accuracy (10V/count), the error voltage remaining on the integrator capacitor (representing the overshoot of the integrator due to comparator delay and clock quantization) must be measured and subtracted from the 31/2 digit result. This is accomplished by multiplying the residue by a factor of 10, then integrating and reference de-integrating the error. This error is subtracted from the 31/2 digit result, yielding a 41/2 digit accurate result. The error remaining from this step is then multiplied by 10 and subtracted, and the process is repeated a third time to achieve an internal accuracy of 61/2 digits. This result is rounded to 51/2 digits and transferred to the holding register, where it can be accessed by the user through one of the three communications modes.
Communication Modes
The HI-7159A A/D converter receives instructions from and transmits data to the user host processor through one of four communication modes. The modes are: parallel microprocessor (Parallel); synchronous serial (Serial Mode 0); serial non-addressed (Serial Mode 1); and serial addressed (Serial Mode 2). The mode is determined by the states of the SEL, SMS0, and SMS1 pins as shown in Table 1. The parallel mode allows the converter to be attached directly to a microprocessor data bus. Data is read and written to the device under control of the microprocessor's RD, WR and CS signals. Serial Mode 0 permits high speed serial data transfer at up to 1 megabits/s. Serial Mode 1 reads and writes industry standard serial data packets consisting of 1 start bit, 8 data bits, 1 parity bit (EVEN), and 1 stop bit, at one of 4 hardware selectable baud rates. Serial Mode 2 is identical to Serial Mode 1 with the addition of addressing capabilities which allow up to 32 HI-7159As to share the same serial line, with each assigned a unique address.
TABLE 1. COMMUNICATION MODE SELECTION COMMUNICATION MODE Parallel Serial 0 Serial 1 Serial 2 SEL PIN 28 VCC DGND DGND DGND SM S0 PIN 18 N/A DGND DGND VCC SM S1 PIN 19 N/A DGND VCC DGND
Conversion Types
The HI-7159A offers the user a choice of three different conversion types. They are: (1) the converter's internal offset voltage, measured by internally connecting VIN HI and VIN LO to AGND and doing a conversion (Error Only Mode); (2) the input voltage (VIN HI minus VIN LO) including the converter's internal offset (Uncompensated Mode); and (3) the input voltage including internal offset errors, minus the internal offset errors (Compensated Mode). This last measurement is a digital subtraction of an Error Only conversion from an Uncompensated conversion, and is the default conversion type. Since a Compensated conversion consists of two conversions, it takes twice as long to perform as the first two types. Under some conditions, it may be desirable to increase the conversion rate without loss of resolution or accuracy. Since the short term drift of the internal offset error is slight when temperature is controlled, it is not always necessary to convert the error voltage once for every input voltage conversion. It is possible for the host processor to do an error conversion periodically, store the result, and subtract the error from a stream of uncompensated input conversions with its own internal ALU. In this way the conversion rate can be effectively doubled. 6
All four modes follow the same interface protocol: a request or a command is sent from the host to the HI-7159A, and the converter responds with the requested data and, in the case of a command, begins a new conversion.
Parallel Mode Operation
The parallel communication mode (Figure 3) is selected when SEL (Pin 28) is high. Pins 18-25 become the eight bidirectional data bits, P0-P7. Pins 15, 16, and 17 respectively become read (RD), write (WR), and chip select (CS). Timing parameters for the parallel mode are shown in Figure 1.
Serial Mode 0
Serial Mode 0 is the high speed synchronous serial interface, directly compatible with the MCS-51 series of microcontrollers. It is enabled by tying SEL (Pin 28), SMS0 (Pin 18) and SMS1 (Pin 19) low (Figure 4A). Pin 16 is the bidirectional serial data path, and pin 15 is the data clock input. Data sent to the HI-7159A is latched on the rising edge of the serial clock. See Figure 2A for detailed timing information. Only 8 data bits are used in this mode - no start, stop, or parity bits are transmitted or received. CS must either be tied to DGND or pulled low to access the device. The SAD0 - SAD3 and BRS0 - BRS1 pins are unused in this mode and should be tied high.
HI-7159A Serial Mode 1
Serial Mode 1 is selected by tying SMS0 (Pin 18) low, SMS1 (Pin 19) high, and SEL (Pin 28) low (Figure 4B). In this mode the HI-7159A interface emulates a UART, reading and writing data in serial data packets of 1 start bit, 8 data bits, 1 parity bit (EVEN), and 1 stop bit. The baud rate is determined by the state of BRS0 and BRS1 (Pins 24 and 25) as shown in Table 2. Pin 15 becomes the serial receiver pin (RXD) and pin 16 the serial transmitter pin (TXD). CS (Pin 17) remains a chip select and must either be tied to DGND or pulled low (see Figure 2B) to access the device. SAD0-SAD3 (Pins 20-23) are unused in this mode and should be tied high.
TABLE 2. BAUD RATE SELECTION FOR MODES 1 AND 2 BRS0 PIN 24 DGND DGND VCC VCC BRS1 PIN 25 DGND VCC DGND VCC BAUD RATE (fXTAL = 2.4576MHz) 300 1200 9600 19200 BAUD RATE vs fXTAL fXTAL/8192 fXTAL/2048 fXTAL/256 fXTAL/128
TXD RXD +5V -5V VEE P RD WR RD WR 14 15 16 ADDRESS BUS D0 DATA BUS D7 D7 ADDRESS DECODER CS +5V SEL 28 VCC 1 27 XTAL UART/P 20K 20K BRS0 BRS1 SM0 +5V SM1 HI-7159A 24 25 18 19 17 CS D0 18 25 20 - 23 +5V RXD -5V VEE 14 TXD 15 16 1 27 +5V VCC XTAL XTAL -5V VEE 10 11 CLK RXD/TXD CLK RXD/TXD 14 15 16 1 27 +5V VCC XTAL XTAL
8051 P SM0 SM1 18 19 17
HI-7159A
+5V
20-25 26 28
CS
DGND SEL
FIGURE 4A. SERIAL MODE 0
26 DGND
28 SEL
17
HI- 7159A
FIGURE 4B. SERIAL MODE 1
26 DGND
FIGURE 3. PARALLEL MODE CONFIGURATION
TO UP TO 31 ADDITIONAL HI-7159As
-5V VEE
+5V VCC 1 27 XTAL XTAL
Design Hints for Operating in the Parallel Mode
1. Always read the status byte twice to make sure that it is cleared. 2. Make sure the status byte is cleared before issuing a command to change modes. 3. Read each digit pair five times before reading the next byte to ensure that the output data is correct. 4. Use a watchdog timer to monitor conversion time. If conversion time is either too long or too short, reissue the conversion command.
UART/P
TXD RXD +5V 20K
RXD TXD
14 15 16
20K BRS0 BRS1 +5V SM0 SM1
HI-7159A 24 25 18 19 20 21 22 23 17 26 DGND 28 SEL ADDRESS SELECT
FIGURE 4C. SERIAL MODE 2 FIGURE 4. SERIAL MODE CONFIGURATIONS
7
HI-7159A Serial Mode 2
Serial Mode 2 is selected by tying SEL (pin 28) low, SMS0 (pin 18) high, and SMS1 (pin 19) low, as shown in Figure 4C. This mode of operation is identical to Serial Mode 1, except that each device now has one of 32 unique addresses determined by the state of pins 20-23 and 17, as shown in Table 3. This allows multiple HI-7159As to be attached to the same pair of serial lines. When the microprocessor sends out an Address Byte (Table 4) that matches one of the HI-7159As' hardwired addresses, that particular HI-7159A is selected for all further I/O until another Address Byte with a different address is transmitted.
TABLE 3. HARDWARE ADDRESS SELECTION FOR MODE 2 PIN 17 B4 (MSB) PIN 23 B3 PIN 22 B2 PIN 21 B1 PIN 20 B0 (LSB)
digits), and type of conversion (Compensated, Uncompensated, or Error Only). Bit D0 = 0 indicates that this is a command byte and a new conversion(s) should be started. A request byte (Table 6) asks for either the status of the converter or the result of a conversion. All bits of a request should be set to 0 except D3, D2, and D0. D3 and D2 determine the type of request (status or digit pair), and D0 = 1 indicates to the HI-7159A that this is a request byte. Serial Mode 2 uses a slightly modified request byte, shown in Table 7, allowing it to individually select each of the six digit bytes. Upon receipt of a request, the HI-7159A will respond with either a status or a digit byte. The status byte (Table 8) returns the current state of the converter. Bit D6 = 1 indicates that a new conversion has been completed since the last time the status byte was read. Bit D6 is cleared after it is read. Bit D4 shows the current continuity (single or continuous). Bit D3 indicates the resolution (51/2 or 41/2 digits) of the conversion, and bits D2 and D1 indicate the type (Compensated, Uncompensated, or Error Only). Bit D0 = 0 indicates that there was no parity error detected in the last request byte. The three digit bytes (Table 9) each contain two nibbles representing two digits of the conversion. The sixth nibble contains the MSD (most significant digit), polarity (1 = positive) and overrange (1 = overrange) information. In Serial Mode 2 the digits (Table 10) are requested and received individually, so a total of six requests and six reads is necessary to obtain all 51/2 digits.
Reading the HI-7159A
Despite the wide variety of interface options available on the HI-7159A, the procedure for communicating with it is essentially the same in all four modes. (Serial Mode 2 differs from the rest in two respects: the chip to be communicated with must first be sent an address byte to select it, and the digit bytes are sent one by one, for a total of six bytes, instead of in pairs.) There are two types of bytes that can be sent to the converter, commands and requests. A command byte (Table 5) sets the parameters of and initiates a conversion. Those parameters are: continuity of the conversion (single or continuous), resolution (51/2 or 41/2
TABLE 4. SERIAL MODE 2 ADDRESS BYTE FORMAT (SENT TO HI-7159A) ADDRESS BIT D7 1 (RESERVED) D6 0 D5 0 (MSB) D4 B4 D3 B3 D2 B2 D1 B1 (LSB) D0 B0
TABLE 5. COMMAND BYTE FORMAT (SENT TO HI-7159A) (RESERVED) D7 0 D6 0 D5 0 Single Continuous CONTINUITY D4 0 1 51/2 41/2 RESOLUTION D3 1 0 Comp Uncomp Error Only CONVERSION TYPE D2 1 1 0 D1 1 0 1 COMMAND BIT D0 0
TABLE 6. REQUEST BYTE FORMAT, PARALLEL AND SERIAL MODE 1 (SENT TO HI-7159A) (RESERVED) D7 0 D6 0 D5 0 D4 0 Digit Pair 0, 1 Digit Pair 2, 3 Digit Pair 4, 5 Converter Status BYTE REQUEST D3 0 0 1 1 D2 0 1 0 1 (RESERVED) D1 0 REQUEST BIT D0 1
8
HI-7159A
TABLE 7. REQUEST BYTE FORMAT, SERIAL MODE 2 (SENT TO HI-7159A) (RESERVED) D7 0 D6 0 D5 0 D4 0 Digit 0 Digit 1 Digit 2 Digit 3 Digit 4 Digit 5 Converter Status BYTE REQUEST D3 0 0 0 0 1 1 1 D2 0 0 1 1 0 0 1 D1 0 1 0 1 0 1 0 REQUEST BIT D0 1
TABLE 8. STATUS BYTE FORMAT (RECEIVED FROM HI-7159A) CONVERTER UPDATE STATUS D6 No Update Updated 0 1 PARITY ERROR D1 1 0 1 No Yes D0 0 1
() D7 0
() D5 0
CONTINUITY D4 Single Continuous 0 1
RESOLUTION D3 51/2 41/2 1 0 Comp
CONVERSION TYPE D2 1 1 0
Uncomp Error
( = Reserved)
TABLE 9. DIGIT BYTE FORMAT, PARALLEL AND SERIAL MODE 1 (RECEIVED FROM HI-7159A) DIGIT BYTE Digit Pair 0, 1 Digit Pair 2, 3 Digit Pair 4, 5 D7 MSB1 MSB3 Polarity (1 = POS) Overrange (1 = OR) MSB5 D6 D5 D4 LSB1 LSB3 LSB5 D3 MSB0 MSB2 MSB4 D2 D1 D0 LSB0 LSB2 LSB4
TABLE 10. DIGIT BYTE FORMAT, SERIAL MODE 2 (RECEIVED FROM HI-7159A) DIGIT BYTE Digits 0 - 4 Digit 5 D7 0 0 D6 0 0 D5 1 1 D4 1 1 D3 MSB Polarity (1 = POS) Overrange (1 = OR) D2 D1 LSB MSB LSB D0
Single Conversion Mode
The suggested algorithm for reading the HI-7159A in its single conversion mode of operation is shown in Figure 5. Essentially it consists of initiating a conversion, waiting until the conversion is complete, and then reading the results. Since no further conversions take place, the data may be read out at any time and at any speed. This is the most straightforward method of reading the HI-7159A.
Continuous Conversion Mode
Once a command byte is sent to the HI-7159A initiating the continuous conversion mode, the output data registers will be updated continuously after every conversion. This makes obtaining a valid reading more difficult, since the possibility exists that the current data could be overwritten by a new conversion before all the digit bytes are read. To prevent this, the status byte should be read before and after the data is read from the converter, to ensure that the converter has not updated during the reads. This is demonstrated in Figure 6.
9
HI-7159A
SEND COMMAND BYTE (INITIATE SINGLE CONVERSION)
Percentages in the 20-50% range indicate that it is possible to get valid data out with very tight code. In all cases the status byte should be checked before and after the reading to ensure data integrity.
TABLE 11. SERIAL MODES 1/2 CONVERSION TYPE
GET STATUS BYTE
NO D6 = 1?
BAUD RATE 300
51/2 COMP
51/2 UNCOMP
41/2 COMP
41/2 UNCOMP
*/*
54%/* 7%/13% 4%/7%
YES GET DIGIT BYTES
1200 9600 19200
*/* */*
14%/25% 7%/13%
*/* */*
27%/50% 14%/25%
*/* */*
54%/* 27%/50%
CONVERSION RESULT IS VALID
Crystal Oscillator
The HI-7159A uses a single pin crystal oscillator design (Figure 7). The crystal is connected between Pin 27 and VCC ; no load capacitors or other components are necessary. The user has a choice of crystal frequencies: 2.4576MHz or 2.4MHz. An off-the-shelf 2.4576MHz crystal works well and provides baud rates of exactly 19.2K, 9600, 1200, and 300. However its total integration period will be 16.28ms, or 0.39ms shorter than a 60Hz cycle. This effectively reduces the normal mode AC rejection.
+5V VCC
FIGURE 5. READING THE HI-7159A IN THE SINGLE CONVERSION MODE
GET STATUS BYTE
NO D6 = 1?
YES GET DIGIT BYTES HI-7159A 1 CRYSTAL (2MHz TO 2.5MHz) 27 XTAL GET STATUS BYTE
FIGURE 7. SINGLE-PIN OSCILLATOR
CONVERSION RESULT IS VALID
YES D6 = 0?
NO
CONVERSION RESULT MAY BE INVALID: DISCARD RESULT
FIGURE 6. READING THE HI-7159A IN THE CONTINUOUS CONVERSION MODE
A 2.4MHz crystal results in an integration period of 16.67ms, exactly the length of one 60Hz AC cycle. Normal mode AC rejection is greatest at this frequency. At 2.4MHz, however, the Baud rates will be off by -2.34%. This error is not large enough to cause any errors with most peripherals, and only applies to operation in Serial Modes 1 and 2. Communication in Serial Mode 0 and the Parallel Mode is independent of the crystal frequency. For this mode a 2.4MHz crystal is recommended. While the oscillator was designed to operate at 2MHz - 2.5MHz, the HI-7159A itself will operate reliably down to less than 600kHz when driven with an external clock. Benefits at lower clock frequencies include reduced rollover error (gain error for negative input voltages) and lower noise. The baud rates mentioned throughout this data sheet correspond to a crystal frequency of 2.4576MHz. At 1.2MHz, the actual baud rates will be half the speed they were at 2.4MHz, i.e., 9600, 4800, 600 and 150 baud. At 600kHz they will be one-fourth.
Due to the wide range of baud rates available in the serial modes, some of the lower baud rates will take longer to transfer the output data than it takes to perform a conversion. In these cases the continuous mode should not be used. Table 11 shows the percentage of the total conversion time that it takes to read all the data from the converter for the two serial modes. These are best case numbers, assuming that the bytes are transmitted and received end-to-end. An asterisk indicates that it is impossible to get all the data out within one conversion.
10
HI-7159A
It may also be possible to directly program the host's serial hardware for operation at nonstandard baud rates, allowing HI-7159A operation at any arbitrary frequency. For example: 50Hz AC rejection requires a 2MHz clock. At this frequency the "9600" baud rate becomes 7812.5 baud. The host's UART must be programmed with the proper divider to operate at this baud rate. The data clock (see Figure 2) is defined as 16 times the baud rate, so the data clock of this configuration would be 125kHz. The data clock can also be determined by dividing the oscillator (clock) frequency by the correct divider from Table 12.
TABLE 12. CRYSTAL DIVIDER RATIOS BAUD RATE SELECTED "300" "1200" "9600" "19200" CRYSTAL DIVIDER 512 128 16 8
AGND 11 26 DGND AGND DGND +5V -5V VCC 1 XTAL 27 14 2 9
REF LO
VEE INT OUT INT IN BUF OUT RINT CINT
VREF HI
3 4 5 6 7 8
10 VIN HI VIN LO HI-7159A 12 13
CREF - GUARD CREFCREF CREF+ REFERENCE CAPACITOR GUARD RINGS
CREF+ GUARD
The following equation determines the divider needed to operate the HI-7159A at any given crystal frequency:
f CLOCK ( 7159A ) f CRYSTAL ( Host UART ) ------------------------------------------- = --------------------------------------------------------------- = Data Clock Divider ( 7159A ) Divider ( Host UART )
FIGURE 8. ANALOG COMPONENTS AND INPUTS TABLE 14. RECOMMENDED COMPONENT VALUES vs CLOCK FREQUENCY fCLOCK 2.4MHz 1.2MHz 600kHz RINT 400k 360k 330k CINT 0.01F 0.022F 0.047F CREF 1.0F 2.2F 4.7F
Once determined, the new divider must be written directly to the Host's UART. Most PC compatibles use an 8250 UART with a 1.8432MHz crystal, so the proper divider for the 2MHz example given above would be 15. Again, these considerations apply only to Serial Modes 1 and 2. Parallel and Serial Mode 0 communication rates are independent of crystal frequency.
NOTE: CINT MUST be a high quality polypropylene capacitor or performance may be degraded.
Conversion Time
The conversion time of the HI-7159A is a function of the crystal frequency and the type of conversion being made. The conversion times for fCLOCK = 2.4MHz are shown in Table 13. At other clock frequencies the times may be calculated from the following formula:
C t CONV = -------------------f CLOCK
The reference capacitor and integrating components can either be selected from Table 14, or calculated from the following equations. CREF acts as a voltage source at different times during a conversion. Its value is determined by two considerations: it must be small enough to be fully charged from its discharged state at power-on; yet it also must be large enough to supply current to the circuit during conversion without significantly drooping from its initial value. For 2.4MHz operation, a 1F capacitor is recommended. The equation for other frequencies is:
2.5 C REF = -------------------f CLOCK
where the constant C is determined from Table 13.
TABLE 13. CONVERSION TIMES CONVERSION TYPE 51/ f = 2.4MHz C
2
COMP 133ms 320,000
51/2 UNCOMP 66.7ms 160,000
41/2 COMP 33.3ms 80,000
41/2 UNCOMP 16.7ms 40,000
Component Selection
Three external passive components must be chosen for the HI-7159A: the integrating capacitor (CINT), the integrating resistor (RINT), and the reference capacitor (CREF). They are chosen based on the crystal frequency, the reference voltage (VREF), and the desired integrating current. Figure 8 illustrates the analog components necessary for the HI-7159A to function. 11
The values of RINT and CINT are selected by choosing the maximum integration current and the maximum integrator output voltage swing. The maximum integration current and voltage swing occurs when VIN = full scale = 2 X VREF. The recommended integration current for the HI-7159A is 5mA - 10mA. This will help determine the value of RINT, since:
V IN I INT = ------------R INT V IN so R INT = ---------- , I INT
where VIN = VIN HI - VIN LO = 2 x VREF.
HI-7159A
Therefore values of RINT should be between 200k and 400k. The exact value of RINT may be altered to get the exact integrator swing desired after choosing a standard capacitor value for CINT. The most critical component in any integrating A/D converter is the integrating capacitor, CINT. For a converter of this resolution, it is imperative that this component perform as closely to an ideal capacitor as possible. Any amount of leakage or dielectric absorption will manifest itself as linearity errors. For this reason CINT must be a high quality polypropylene capacitor. Use of any other type may degrade performance. The value of CINT is determined by the magnitude of the desired maximum integrator output voltage swing as shown below:
( V IN ) ( t INT ) V SWING = ------------------------------------( R INT ) ( C INT )
200,000
100,000 OUTPUT COUNT
000,000
-100,000 -200,012 COUNTS -200,000 -2 -1 0 INPUT (V) 1 2
FIGURE 9. TYPICAL HI-7159A TRANSFER CHARACTERISTIC
Solving for CINT yields:
( V IN ) ( t INT ) C INT = ---------------------------------------------( R INT ) ( V SWING )
CREF Guard Pins
Depending on the polarity of the input signal, either the negative or the positive terminal of the reference capacitor will be connected to AGND to provide the correct polarity for reference deintegration. In systems where VREF LO is tied to analog ground, the reference capacitor is effectively shifted down by | VREF | for positive input voltages, and is not shifted at all for negative input voltages. This shift can cause some charge on the reference capacitor to be lost due to stray capacitance between the reference capacitor leads and ground traces or other fixed potentials on the board. The reference voltage will now be slightly smaller for positive inputs. This difference in reference voltages for positive and negative inputs appears as rollover error. The HI-7159A provides two guard ring outputs to minimize this effect. Each guard ring output is a buffered version of the voltage at its respective CREF pin. If the traces going to the CREF pins and under CREF itself are surrounded by their corresponding guard rings, no charge will be lost as CREF is moved. Figure 10 shows two slightly different patterns. The first one is for capacitors of symmetrical construction, the second is for capacitors with outside foils (one end of the capacitor is the entire outside.
where VSWING is the maximum output voltage swing of the integrator, VIN is the full scale input voltage (VIN HI - VIN LO) to the converter (equal to 2 X VREF), and tINT is the time in which VIN is integrated. The best results are achieved when the maximum integrator output voltage is made as large as possible, yet still less than the nonlinear region in the vicinity of the power supply limit. A full scale output swing of about 3V provides the greatest accuracy and linearity.
NOTE: The integrator is auto-zeroed to the voltage at VIN LO . If VIN LO is negative with respect to AGND, the integrator will have | VIN LO | less headroom for positive input voltages (inputs where VIN HI - VIN LO > 0). If VIN LO is positive with respect to AGND, the integrator will have | VIN LO | less headroom for negative input voltages (inputs where VIN HI - VIN LO < 0). In most applications VIN LO is at or near AGND and the above equations will be adequate. In applications where VIN LO may be more than 0.1V away from AGND, it should be included in the integrator swing considerations. The following formula combines all the above considerations:. ( V IN HI - V IN LO ) ( 10, 000 ) V IN LO - ---------------------------------------------------------------------- 3V (R )(C )(f )
INT INT OSC
(5) CREF- GUARD (6) CREFHI -7159A (7) CREF+ (8) CREF+ GUARD
Gain Error Adjustments
While the HI-7159A has a very linear transfer characteristic in both the positive and negative directions, the slope of the line is slightly greater for negative inputs than for positive. This results in the transfer characteristic shown in Figure 9. One end point of this curve, typically the positive side, can be adjusted to zero error by trimming the reference voltage. The other (negative) side will have a fixed gain error. This error can be removed in software by multiplying all negative readings by a scale factor, determined by dividing the ideal full scale reading (-200,000 counts) by the actual full scale reading when VIN = -2.00000V.
(5) CREF(6) CREF(7) CREF+
GUARD
HI -7159A
(8) CREF+ GUARD
FIGURE 10. TYPICAL GUARD RING LAYOUT
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HI-7159A Die Characteristics
DIE DIMENSIONS: 5817m x 3988m METALLIZATION: Type: SiAl Thickness: 10kA 1kA
HI-7159A
BUF OUT INT IN INT OUT
PASSIVATION: Type: PSG/Nitride Thickness: 15kA 1kA
Metallization Mask Layout
VCC
VCC
SEL
XTAL
DGND P7/BRS1
P6/BRS0 CREF GUARD
P5/SAD3
P4/SAD2
P3/SAD1 CREF CREF + P2/SAD0
P1/SMS1
CREF + GUARD VREF
HI
VREF
LO
P0/SMS0 AGND VIN VIN VEE
HI LO
RD/RXD
WR/TWD
CS/SAD4
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HI-7159A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
E28.6 (JEDEC MS-001-BF ISSUE D)
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.600 BSC 0.115 28 0.700 0.200
2.54 BSC 15.24 BSC 2.93 28 17.78 5.08
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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