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128K x 32, 128K x 36 SYNCHRONOUS .LOW-THROUGH STATIC RAM
.EATURES
.ast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 12 ns Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data inputs and control signals PentiumTM or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs JEDEC 100-Pin LQ.P and 119-pin PBGA package Single +3.3V +10%, -5% power supply Power-down snooze mode
DESCRIPTION The 1+51 IS61S.12832 and IS61S.12836 are high-speed
synchronous static RAM designed to provide a burstable, highperformance for high speed networking and communication applications. It is organized as 131,072 words by 32 bits or 36 bits, fabricated with 1+51's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61S.12832 and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
.AST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time .renquency 7.5 7.5 8.5 117 8 8 10 100 8.5 8.5 11 90 10 10 15 66 12 12 15 66 Units ns ns MHz
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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BLOCK DIAGRAM
MODE Q0 A0'
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
128K x 32, 128K x 36 MEMORY ARRAY
A16-A0
17
D
Q
15
17
ADDRESS REGISTER
CE CLK 32 or 36 32 or 36
GW BWE BW4
DQd BYTE WRITE REGISTERS
CLK
D
Q
BW3
D DQc Q BYTE WRITE REGISTERS CLK
BW2
DQb BYTE WRITE REGISTERS
CLK
D
Q
BW1
D DQa Q BYTE WRITE REGISTERS CLK
CE CE2 CE2 D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK OE
32 or 36 DQ[31:0] or DQ[35:0]
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
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PIN CON.IGURATION
119-pin PBGA (Top View)
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ NC A10 A11 A14 NC ZZ A5 MODE VCC GND A13 NC NC GND A0 GND NC DQa1 DQd7 GND A1 GND DQa3 DQa2 DQd5 GND BWE GND DQa4 VCCQ DQd3 BW4 NC BW1 DQa5 DQa6 DQd2 GND CLK GND DQa7 DQa8 VCC NC VCC NC VCC VCCQ DQc8 GND GW GND DQb2 DQb1 DQc6 BW3 ADV BW2 DQb4 DQb3 DQc4 GND OE GND DQb5 VCCQ DQc3 GND CE GND DQb6 DQb7 NC GND NC GND NC DQb8 A7 A2 VCC A12 A15 NC CE2 A3 ADSC A9 CE2 NC A6 A4 ADSP A8 A16 VCCQ
NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GNDQ VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC
100-Pin LQ.P
7
A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2
3
4
5
6
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCC DQa2 DQa1 NC
128K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GW OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable CE, CE2, CE2 Synchronous Chip Enable
A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE
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MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
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PIN CON.IGURATION
119-pin PBGA (Top View)
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ NC A10 A11 A14 NC ZZ A5 MODE VCC GND A13 NC DQPd GND A0 GND DQPa DQa1 DQd7 GND A1 GND DQa3 DQa2 DQd5 GND BWE GND DQa4 VCCQ DQd3 BW4 NC BW1 DQa5 DQa6 DQd2 GND CLK GND DQa7 DQa8 VCC NC VCC NC VCC VCCQ DQc8 GND GW GND DQb2 DQb1 DQc6 BW3 ADV BW2 DQb4 DQb3 DQc4 GND OE GND DQb5 VCCQ DQc3 GND CE GND DQb6 DQb7 DQPc GND NC GND DQPb DQb8 A7 A2 VCC A12 A15 NC CE2 A3 ADSC A9 CE2 NC A6 A4 ADSP A8 A16 VCCQ
DQPc DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GNDQ VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd
100-Pin LQ.P
7
A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2
3
4
5
6
DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCC DQa2 DQa1 DQPa
128K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ DQPa-DQPd GW OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable Parity Data I/O CE, CE2, CE2 Synchronous Chip Enable
A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE
4
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
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TRUTH TABLE
Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L X X L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L H H L H H H H X X H X H H X X H X L X X L L X L L H H H H H H H H H H H H ADV WRITE X X X X X X X X L L L L L L H H H H H H X X X X X X Read Write Read Read Read Read Write Write Read Read Read Read Write Write OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z Q High-Z High-Z High-Z Q High-Z Q High-Z High-Z High-Z
PARTIAL TRUTH TABLE
.unction Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X BW3 BW4 X H H L X X H H L X
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INTERLEAVED BURST ADDRESS TABLE (MODE = V++3 or No Connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN VCC Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND Value -40 to +85 -55 to +150 1.6 100 -0.5 to VCCQ + 0.3 -0.5 to VCC + 0.5 -0.5 to 4.6 Unit o C o C W mA V V V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
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OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0oC to +70oC -40oC to +85oC VCC 3.3V +10%, -5% 3.3V +10%, -5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND < VIN < VCCQ(2) GND < VOUT < VCCQ, OE = VIH Com. Ind. Com. Ind. Test Conditions IOH = -4.0 mA IOL = 8.0 mA Min. 2.4 - 2.0 -0.3 -2 -5 -2 -5 Max. - 0.4 VCC + 0.3 0.8 2 5 2 5 Unit V V V V A A
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol ICC Parameter AC Operating Supply Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, Vcc = Max. Cycle Time > tKC min. Com. Ind. 7.5 Max. 270 - 8 Max. 250 260 8.5 Max. 230 240 10 Max. 190 200 12 Max. 170 180 Unit mA
ISB
Standby Current
Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time > tKC min. ZZ = VCCQ Com. Clock Running Ind. All Inputs < GND + 0.2V or > Vcc - 0.2V
50 -
50 60
50 60
50 60
50 60
mA
IZZ
Power-down Mode Current
10 -
10 15
10 15
10 15
10 15
mA
Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCCQ. 2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to < GND + 0.2V or > Vcc - 0.2V.
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CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 8 Unit p. p.
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25 C, f = 1 MHz, Vcc = 3.3V.
O
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and .all Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See .igures 1 and 2
AC TEST LOADS
3.3V
317
ZO = 50
OUTPUT
Output Buffer
30 pF
50
1.5V
5 pF Including jig and scope
351
.igure 1
.igure 2
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READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol fMAX tKC tKH tKL tKQ tKQX(1) tKQLZ tOEQ tOELZ(1,2) tOEHZ tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH
(1,2) (1,2) (1,2)
Parameter Clock .requency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time
Min. Max. - 8.5 3 3 - 2 0 2 - 0 - 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 117 - - - 7.5 - - 3.5 3.5 - 3.5 - - - - - - - - - -
7.5
8 Min. Max. - 10 4 4 - 2 0 2 - 0 - 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 100 - - - 8 - - 3.5 3.5 - 3.5 - - - - - - - - - -
8.5 Min. Max. - 11 4.5 4.5 - 2 0 2 - 0 - 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 90 - - - 8.5 - - 3.5 3.5 - 3.5 - - - - - - - - - -
10 Min. Max. - 15 4.5 4.5 - 2 0 2 - 0 - 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 66 - - - 10 - - 3.5 3.5 - 3.5 - - - - - - - - - -
12 Min. Max. - 15 4.5 4.5 - 2 0 2 - 0 - 4 4 4 4 4 1.5 1.5 1.5 1.5 1.5 66 - - - 12 - - 3.5 5 - 3.5 - - - - - - - - - -
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKQHZ
Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in .igure 2. 3. Tested with load in .igure 1.
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READ/WRITE CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP is blocked by CE inactive
ADSP
tSS tSH
ADSC
ADV
tAS tAH
A16-A0
RD1
tWS tWH
WR1
RD2
RD3
GW
tWS tWH
BWE
tWS tWH
BW4-BW1
tCES tCEH
WR1 CE Masks ADSP
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
CE2
tCES tCEH
Unselected with CE2
CE2
tOEQ tOEHZ
OE
tOELZ tOEQX tKQX
DATAOUT
High-Z
tKQLZ tKQ
1a
tKQX tKQHZ
2a
2b
2c
2d
tKQHZ
DATAIN
High-Z
tDS
1a
tDH
Single Read
Single Write
Burst Read
Unselected
10
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WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Min. Max. 8.5 3 3 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 - - - - - - - - - - - - - - -
7.5
8 Min. Max. 10 4 4 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 - - - - - - - - - - - - - - -
8.5 Min. Max. 11 4.5 4.5 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 - - - - - - - - - - - - - - -
10 Min. Max. 15 4.5 4.5 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 - - - - - - - - - - - - - - -
12 Min. Max. 15 4.5 4.5 4 4 4 4 4 4 1.5 1.5 1.5 1.5 1.5 1.5 - - - - - - - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Tested with load in .igure 1.
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WRITE CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP is blocked by CE inactive
ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV
tAS tAH tAVH
A16-A0
WR1
tWS tWH
WR2
WR3
GW
tWS tWH
BWE
tWS tWH tWS tWH
BW4-BW1
tCES tCEH
WR1
WR2 CE Masks ADSP
WR3
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
OE
DATAOUT
High-Z
tDS tDH
BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a
DATAIN
High-Z
1a
Single Write
Burst Write
Write
Unselected
12
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SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol tKC tKH tKL tKQ tKQX
(1) (1,2)
Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery
Min. Max. 8.5 3 3 - 2 0 2 - 0 - 2 2 2 0.5 0.5 0.5 2 2 - - - 7.5 - - 3.5 3.5 - 3.5 - - - - - - - -
7.5
8 Min. Max. 10 4 4 - 2 0 2 - 0 - 2 2 2 0.5 0.5 0.5 2 2 - - - 8 - - 3.5 3.5 - 3.5 - - - - - - - -
8.5 Min. Max. 11 4.5 4.5 - 2 0 2 - 0 - 2 2 2 0.5 0.5 0.5 2 2 - - - 8.5 - - 3.5 3.5 - 3.5 - - - - - - - -
10 Min. Max. 15 4.5 4.5 - 2 0 2 - 0 - 2 2 2 0.5 0.5 0.5 2 2 - - - 10 - - 3.5 3.5 - 3.5 - - - - - - - -
12 Min. Max. 15 4.5 4.5 - 2 0 2 - 0 - 4 4 4 1.5 1.5 1.5 2 2 - - - 12 - - 3.5 5 - 3.5 - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc
tKQLZ tOEQ tOELZ tAS tSS tCES tAH tSH tCEH tZZS
tKQHZ(1,2)
(1,2) (1,2)
tOEHZ
tZZREC
Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in .igure 2. 3. Tested with load in .igure 1.
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SNOOZE AND RECOVERY CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP
ADSC
ADV
tAS tAH
A16-A0
RD1
RD2
GW
BWE
BW4-BW1
tCES tCEH
CE
tCES tCEH
CE2
tCES tCEH
CE2
tOEQ tOEHZ
OE
tOELZ tOEQX
DATAOUT
High-Z
tKQLZ tKQ
1a
tKQX tKQHZ tZZS tZZREC
DATAIN ZZ
High-Z
Single Read
Snooze with Data Retention
Read
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ORDERING IN.ORMATION Commercial Range: 0oC to +70oC
.requency 7.5 8 8.5 10 12 Order Part Number IS61S.12832-7.5TQ IS61S.12832-7.5B IS61S.12832-8TQ IS61S.12832-8B IS61S.12832-8.5TQ IS61S.12832-8.5B IS61S.12832-10TQ IS61S.12832-10B IS61S.12832-12TQ IS61S.12832-12B Package 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA
Industrial Range: - oC to +85oC -40
.requency 8 8.5 10 12 Order Part Number IS61S.12832-8TQI IS61S.12832-8.5TQI IS61S.12832-10TQI IS61S.12832-12TQI Package 14*20*1.4mm LQ.P 14*20*1.4mm LQ.P 14*20*1.4mm LQ.P 14*20*1.4mm LQ.P
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ORDERING IN.ORMATION Commercial Range: 0oC to +70oC
.requency 7.5 8 8.5 10 12 Order Part Number IS61S.12836-7.5TQ IS61S.12836-7.5B IS61S.12836-8TQ IS61S.12836-8B IS61S.12836-8.5TQ IS61S.12836-8.5B IS61S.12836-10TQ IS61S.12836-10B IS61S.12836-12TQ IS61S.12836-12B Package 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA 14*20*1.4mm LQ.P 14*22mm PBGA
Industrial Range: - oC to +85oC -40
.requency 8 8.5 10 12 Order Part Number IS61S.12836-8TQI IS61S.12836-8.5TQI IS61S.12836-10TQI IS61S.12836-12TQI Package 14*20*1.4mm LQ.P 14*20*1.4mm LQ.P 14*20*1.4mm LQ.P 14*20*1.4mm LQ.P
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 .ax: 886-3-5783000 BRANCH O..ICE: 7., NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 .AX: 886-2-26962252 http://www.icsi.com.tw
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