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| Date Jun. 17. 2002 32M (x16) Flash + 16M (x16) SCRAM LRS1808A LRS1808A * Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. * When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * * * * * * Office electronics Instrumentation and measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * * * * Aerospace equipment Communications equipment for trunk lines Control equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. * Please direct all queries regarding the products covered herein to a sales representative of the company. LRS1808A 1 Contents 1. Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Identifier Codes for Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Functions of Block Lock and Block Lock-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 Block Locking State Transitions upon Command Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Block Locking State Transitions upon F-WP Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Status Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Write Cycle (F-WE / F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Block Erase, Full Chip Erase, (Page Buffer) Program Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. AC Electrical Characteristics for Smartcombo RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 Sleep Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 Address Skew Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7 Data Retention Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 Smartcombo RAM AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 21 22 23 26 27 27 27 28 29 29 29 29 30 14. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 15. Flash Memory Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 16. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 17. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18. Package and Packing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 LRS1808A 2 1. Description The LRS1808A is a combination memory organized as 2,097,152 x16 bit flash memory and 1,048,576 x16 bit Smartcombo RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and Smartcombo RAM has P-type bulk silicon Flash Memory - Access Time Read Word write Block erase Reset Power-Down Standby - Optimized Array Blocking Architecture Eight 4K-word Parameter Blocks Sixty-Three 32K-word Main Blocks Bottom Parameter Location - Extended Cycling Capability 100,000 Block Erase Cycles (F-VPP = 1.65V to 3.3V) 1,000 Block Erase Cycles and total 80 hours (F-VPP = 11.7V to 12.3V) - Enhanced Automated Suspend Options Word Write Suspend to Read Block Erase Suspend to Word Write Block Erase Suspend to Read Smartcombo RAM - Access Time - Cycle time - Power Supply current Operating current Standby current (Data retention current) Sleep Mode (Data non-retention current) **** **** **** 2.7V to 3.3V(Flash) 2.7V to 3.1V(Smartcombo RAM) -30C to +85C **** **** **** **** **** **** 85 ns 25 mA 60 mA 30 mA 25 A 25 A (Max.) (Max. tCYCLE = 200ns, CMOS Input) (Max.) (Max.) (Max. F-RST = GND 0.2V, IOUT (F-RY/BY) = 0mA) (Max. F-CE = F-RST = F-VCC 0.2V) - Power supply current (The current for F-VCC pin and F-VPP pin) **** **** **** **** **** 85 ns (Max.) 85 to 32,000 ns 20 mA 80 A 15 A (Max. tRC, tWC = Min.) (Max.) (Max.) LRS1808A 3 2. Pin Configuration INDEX (TOP View) 1 A NC B 2 3 A16 4 A8 5 A15 A10 6 A14 A9 7 A13 8 A12 9 GND 10 NC 11 NC 12 NC NC F-A20 A11 DQ15 S-WE DQ14 DQ7 DQ4 DQ5 C D E F FF-WE RY/BY NC GND F-RST T1 S-A17 DQ13 DQ6 T2 DQ12 S-CE2 S-VCC F-VCC T3 DQ10 DQ2 DQ3 DQ0 DQ1 A1 S-CE1 NC NC NC F-WP F-VPP A19 DQ11 S-LB S-UB S-OE A18 F-A17 NC NC A5 A7 A4 T4 A6 A0 DQ9 DQ8 A3 A2 G H NC F-CE GND F-OE Note) From T1 to T4 pins are needed to be open. Two NC pins at the corner are connected. Do not float any GND pins. LRS1808A 4 Pin A0 to A16, A18, A19 Address Inputs (Common) F-A17, F-A20 S-A17 F-CE S-CE1 S-CE2 F-WE S-WE F-OE S-OE S-LB S-UB Address Inputs (Flash) Address Input (Smartcombo RAM) Chip Enable Input (Flash) Description Type Input Input Input Input Input Input Input Input Input Input Input Input Chip Enable Input (Smartcombo RAM) Sleep State Input (Smartcombo RAM) Write Enable Input (Flash) Write Enable Input (Smartcombo RAM) Output Enable Input (Flash) Output Enable Input (Smartcombo RAM) Smartcombo RAM Byte Enable Input (DQ0 to DQ7) Smartcombo RAM Byte Enable Input (DQ8 to DQ15) Reset Power Down Input (Flash) Block erase and Write : VIH Read : VIH Reset Power Down : VIL Write Protect Input (Flash) When F-WP is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and locked-down. When F-WP is VIH, lock-down is disabled. Ready/Busy Output (Flash) During an Erase or Write operation : VOL Block Erase and Write Suspend : High-Z (High impedance) Data Inputs and Outputs (Common) Power Supply (Flash) Power Supply (Smartcombo RAM) Monitoring Power Supply Voltage (Flash) Block Erase and Write : F-VPP = VPPH1/2 All Blocks Locked : F-VPP < VPPLK GND (Common) Non Connection Test pins (Should be all open) F-RST Input F-WP Input F-RY/BY DQ0 to DQ15 F-VCC S-VCC F-VPP GND NC T1 to T4 Open Drain Output Input / Output Power Power Input Power - LRS1808A 5 3. Truth Table 3.1 Bus Operation(1) Flash Read Output Disable Write Read Output Disable Write Read Standby Output Disable Write Read Reset Power Output Disable Down Write Standby Reset Power Standby Down Standby Reset Power Sleep Down Notes: 1. L = VIL, H = VIH, X = H or L, High-Z = High impedance. Refer to the DC Characteristics. 2. Command writes involving block erase (page buffer) program are reliably executed when F-VPP = VPPH1/2 and F-VCC = 2.7V to 3.3V. Command writes involving full chip erase is reliably executed when F-VPP = VPPH1 and F-VCC = 2.7V to 3.3V. Block erase, full chip erase, (page buffer) program with F-VPP < VPPH1/2 (Min.) produce spurious results and should not be attempted. 3. Never hold F-OE low and F-WE low at the same timing. 4. Refer Section 5. Command Definitions for Flash Memory valid DIN during a write operation. 5. F-WP set to VIL or VIH. 6. Electricity consumption of Flash Memory is lowest when F-RST = GND 0.2V. 7. Flash Read Mode Mode Read Array Read Identifier Codes Read Query Address X See 5.2 DQ0 to DQ15 DOUT See 5.2 8. S-UB, S-LB Control Mode S-LB S-UB DQ0 to DQ7 L L H L H L DOUT/DIN DOUT/DIN High - Z DQ8 to DQ15 DOUT/DIN High - Z DOUT/DIN Sleep Standby Smart combo RAM Notes 3,5 5 2,3,4,5 3,5 5 2,3,4,5 5,6 5,6 5,6 5,6 5,6 5,6 5 5,6 5 5,6 H X H X H L H L X X X L X X X High - Z X X H H X X X High - Z X L X X L H H H X X L H L H L H H L L X H X L X H X H H H L H H H L H X H X (8) H X H X (8) (8) High - Z (8) High - Z X L X X X L H F-CE F-RST F-OE F-WE S-CE1 S-CE2 S-OE S-WE S-LB S-UB DQ0 to DQ15 L H H L H H X X X (7) High - Z DIN (7) High - Z DIN Refer to the Appendix Refer to the Appendix LRS1808A 6 3.2 Simultaneous Operation Modes Allowed with Four Planes(1, 2) THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS: Read Array Read ID Read Status Read Query Word Program Page Buffer Program Block Erase Full Chip Erase Program Suspend Block Erase Suspend Notes: 1. "X" denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing. Commands must be written to an address within the block targeted by that command. X X X X Read Array X X X X X X X Read ID X X X X X X X Read Status X X X X X X X X X X X X X X X X Read Query X X X X X X X Word Program X X X X Page Buffer Program X X X X Block Erase X X X X X Full Chip Program Erase Suspend X X X X Block Erase Suspend X X X X X X LRS1808A 7 4. Block Diagram F-VCC F-VPP F-A17, F-A20 A0 to A16, A18, A19 F-CE F-OE F-WE F-WP F-RST DQ0 to DQ15 S-A17 S-CE1 S-CE2 S-OE S-WE S-LB S-UB 16M (x16) bit Smartcombo RAM GND 32M (x16) bit Flash memory F-RY/BY S-VCC LRS1808A 8 5. Command Definitions for Flash Memory(11) 5.1 Command Definitions Command Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit Set Partition Configuration Register Notes: 1. Bus operations are defined in 3.1 Bus Operation. 2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle. X=Any valid address within the device. PA=Address within the selected partition. IA=Identifier codes address (See 5.2 Identifier Codes for Read Operation). QA=Query codes address. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. PCRC=Partition configuration register code presented on the address A0-A15. 3. ID=Data read from identifier codes (See 5.2 Identifier Codes for Read Operation). QD=Data read from query database. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details. SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first). N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code (See 5.2 Identifier Codes for Read Operation). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when F-RST is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target partition to be programmed and the confirm command (D0H). Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details. Bus Cycles Req'd 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 First Bus Cycle Notes 2 2,3,4 2,3,4 2,3 2 2,3,5 2,5,9 2,3,5,6 2,3,5,7 2,8,9 2,8,9 2 2,10 2 2,3 Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address(2) PA PA PA PA PA BA X WA WA PA PA BA BA BA PCRC Data(3) FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H 60H Write Write Write Write BA BA BA PCRC 01H D0H 2FH 04H Write Write Write Write BA X WA WA D0H D0H WD N-1 Read Read Read IA QA PA ID QD SRD Second Bus Cycle Oper(1) Address(2) Data(3) LRS1808A 9 8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase operation can not be suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F-WP is VIL. When F-WP is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LRS1808A 10 5.2 Identifier Codes for Read Operation Code Manufacturer Code Device Code Manufacturer Code 32M Bottom Parameter Device Code Block is Unlocked Block Lock Configuration Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code Notes: 1. Bottom parameter device has its parameter blocks in the plane 0 (The lowest address). 2. DQ15-DQ2 is reserved for future implementation. 3. PCRC=Partition Configuration Register Code. 4. The address A20-A16 are shown in below table for reading the manufacturer, device, lock configuration, device configuration code. The address to read the identifier codes is dependent on the partition which is selected when writing the Read Identifier Codes command (90H). See Chapter 6. Partition Configuration Register Definition (P.15) for the partition configuration register. Identifier Codes for Read Operation on Partition Configuration (32M-bit device) Partition Configuration Register PCR.10 0 0 0 1 0 1 1 1 PCR.9 0 0 1 0 1 1 0 1 PCR.8 0 1 0 0 1 0 1 1 00H 00H or 08H 00H or 10H 00H or 18H 00H or 08H or 10H 00H or 10H or 18H 00H or 08H or 18H 00H or 08H or 10H or 18H Address (32M-bit device) [A20-A16] Partition Configuration Register 0006H Block Address +2 Address [A15-A0](4) 0000H 0001H Data [DQ15-DQ0] 00B0H 00B5H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 PCRC 1 2 2 2 2 3 Notes LRS1808A 11 5.3 Functions of Block Lock and Block Lock-Down Current State State [000] [001] [011] [100] [101](3) [110](4) [111] Notes: 1. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked. DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down. 2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (F-WP = 0) or [101] (F-WP = 1), regardless of the states before power-off or reset operation. 4. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 5.4 Block Locking State Transitions upon Command Write(4) Current State State [000] [001] [011] [100] [101] [110] [111] Notes: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lockdown" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that F-WP is not changed and fixed VIL or VIH. F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after Lock Command Written (Next State) Set Lock(1) [001] No Change(3) No Change [101] No Change [111] No Change Clear Lock(1) No Change [000] No Change No Change [100] No Change [110] Set Lock-down(1) [011](2) [011] No Change [111](2) [111] [111](2) No Change (3) F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 (1) DQ0(1) 0 1 1 0 1 0 1 Locked State Name Unlocked Locked-down Unlocked Locked Lock-down Disable Lock-down Disable Erase/Program Allowed (2) Yes No No Yes No Yes No LRS1808A 12 5.5 Block Locking State Transitions upon F-WP Transition(4) Current State Previous State [110](2) Other than [110](2) Notes: 1. "F-WP = 01" means that F-WP is driven to VIH and "F-WP = 10" means that F-WP is driven to VIL. 2. State transition from the current state [011] to the next state depends on the previous state. 3. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. State [000] [001] [011] [100] [101] [110] [111] F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after F-WP Transition (Next State) F-WP = 01(1) [100] [101] [110] [111] F-WP = 10(1) [000] [001] [011](3) [011] LRS1808A 13 6. Status Register Definition Status Register Definition R 15 WSMS 7 R 14 BESS 6 R 13 BEFCES 5 R 12 PBPS 4 Notes: Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. R 11 VPPS 3 R 10 PBPSS 2 R 9 DPS 1 R 8 R 0 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM STATUS (PBPS) 1 = Error in (Page Buffer) Program 0 = Successful (Page Buffer) Program SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP LOW Detect, Operation Abort 0 = F-VPP OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Check SR.7 or F-RY/BY to determine block erase, full chip erase, (page buffer) program completion. SR.6 - SR.1 are invalid while SR.7= "0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit or set partition configuration register attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of F-VPP level. The WSM interrogates and indicates the F-VPP level only after Block Erase, Full Chip Erase, (Page Buffer) Program command sequences. SR.3 is not guaranteed to report accurate feedback when F-VPPVPPH1/2 or VPPLK. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock bit status. SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register. LRS1808A 14 R 15 SMS 7 R 14 R 6 R 13 R 5 Extended Status Register Definition R R 12 R 4 Notes: 11 R 3 R 10 R 2 R 9 R 1 R 8 R 0 XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not. XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register. LRS1808A 15 R 15 R 7 R 14 R 6 R 13 R 5 Partition Configuration Register Definition R R PC2 12 R 4 11 R 3 10 R 2 PC1 9 R 1 PC0 8 R 0 PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. 100 = Plane 0-2 are merged into one partition. (default in a top parameter device) 011 = Plane 2-3 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 110 = Plane 0-1 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 101 = Plane 1-2 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions. PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Notes: After power-up or device reset, PCR10-8 (PC2-0) is set to "001" in a bottom parameter device and "100" in a top parameter device. See the table below for more details. PCR.15-11 and PCR.7-0 are reserved for future use and should be masked out when polling the partition configuration register. Partition Configuration PC2 PC1PC0 PARTITIONING FOR DUAL WORK PARTITION0 PLANE3 PLANE2 PLANE1 PLANE0 PC2 PC1PC0 PARTITIONING FOR DUAL WORK PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 PLANE1 PLANE0 PLANE0 PLANE0 PLANE0 000 011 PARTITION1 PLANE3 PLANE2 PLANE1 PARTITION0 PLANE0 PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 001 110 PARTITION1 PLANE3 PLANE2 PARTITION0 PLANE1 PLANE0 PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 010 101 PARTITION1 PLANE3 PLANE2 PARTITION0 PLANE1 PLANE0 PARTITION3 PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE2 100 111 PLANE1 PLANE1 PLANE1 LRS1808A 16 7. Memory Map for Flash Memory BLOCK NUMBER ADDRESS RANGE 0F8000h - 0FFFFFh 0F0000h - 0F7FFFh 0E8000h - 0EFFFFh 0E0000h - 0E7FFFh 0D8000h - 0DFFFFh 0D0000h - 0D7FFFh 0C8000h - 0CFFFFh 0C0000h - 0C7FFFh 0B8000h - 0BFFFFh 0B0000h - 0B7FFFh 0A8000h - 0AFFFFh 0A0000h - 0A7FFFh 098000h - 09FFFFh 090000h - 097FFFh 088000h - 08FFFFh 080000h - 087FFFh Bottom Parameter 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD BLOCK NUMBER 70 69 68 67 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD ADDRESS RANGE 1F8000h - 1FFFFFh 1F0000h - 1F7FFFh 1E8000h - 1EFFFFh 1E0000h - 1E7FFFh 1D8000h - 1DFFFFh 1D0000h - 1D7FFFh 1C8000h - 1CFFFFh 1C0000h - 1C7FFFh 1B8000h - 1BFFFFh 1B0000h - 1B7FFFh 1A8000h - 1AFFFFh 1A0000h - 1A7FFFh 198000h - 19FFFFh 190000h - 197FFFh 188000h - 18FFFFh 180000h - 187FFFh PLANE3 (UNIFORM PLANE) 66 65 64 63 62 61 60 59 58 57 56 55 PLANE1 (UNIFORM PLANE) 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 078000h - 07FFFFh 070000h - 077FFFh 068000h - 06FFFFh 060000h - 067FFFh 058000h - 05FFFFh 050000h - 057FFFh 048000h - 04FFFFh 040000h - 047FFFh 038000h - 03FFFFh 030000h - 037FFFh 028000h - 02FFFFh 020000h - 027FFFh 018000h - 01FFFFh 010000h - 017FFFh 008000h - 00FFFFh 007000h - 007FFFh 006000h - 006FFFh 005000h - 005FFFh 004000h - 004FFFh 003000h - 003FFFh 002000h - 002FFFh 001000h - 001FFFh 000000h - 000FFFh 54 53 52 51 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 178000h - 17FFFFh 170000h - 177FFFh 168000h - 16FFFFh 160000h - 167FFFh 158000h - 15FFFFh 150000h - 157FFFh 148000h - 14FFFFh 140000h - 147FFFh 138000h - 13FFFFh 130000h - 137FFFh 128000h - 12FFFFh 120000h - 127FFFh 118000h - 11FFFFh 110000h - 117FFFh 108000h - 10FFFFh 100000h - 107FFFh PLANE2 (UNIFORM PLANE) 50 49 48 47 46 45 44 43 42 41 40 39 PLANE0 (PARAMETER PLANE) LRS1808A 17 8. Absolute Maximum Ratings Symbol VCC VIN TA TSTG F-VPP Notes: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F-VPP. 3. -1.0V undershoot is allowed when the pulse width is less than 5 nsec. 4. VIN should not be over VCC +0.3V. 5. Applying 12V 0.3V to F-VPP during erase/write can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V 0.3V for total of 80 hours maximum. +13.0V overshoot is allowed when the pulse width is less than 20 nsec. 9. Recommended DC Operating Conditions (TA = -30C to +85C) Symbol F-VCC S-VCC VPP VIH VIL Notes: 1. VCC is the lower of F-VCC or S-VCC. 2. VCC is the higher of F-VCC or S-VCC. 10. Pin Capacitance(1) (TA = 25C, f = 1MHz) Symbol CIN CI/O Note: 1. Sampled but not 100% tested. Parameter Input capacitance I/O capacitance Notes Min. Typ. Max. 15 25 Unit pF pF Condition VIN = 0V VI/O = 0V Parameter Supply Voltage Supply Voltage F-VPP Voltage (Write Operation) F-VPP Voltage (Read Operation) Input Voltage Input Voltage Notes Min. 2.7 2.7 1.65 0 VCC -0.3 -0.3 (2) Parameter Supply voltage Input voltage Operating temperature Storage temperature F-VPP voltage Notes 1,2 1,2,3,4 -0.2 -0.5 -30 -65 1,3,5 -0.2 Ratings to to to to to +3.6 VCC +0.3 +85 +125 +12.6 Unit V V C C V Typ. 3.0 Max. 3.3 3.1 3.3 3.3 VCC +0.3 0.3 (1) Unit V V V V V V LRS1808A 18 11. DC Electrical Characteristics(1) DC Electrical Characteristics (TA = -30C to +85C, F-VCC = 2.7V to 3.3V, S-VCC = 2.7V to 3.1V) Symbol ILI ILO ICCS Parameter Input Leakage Current Output Leakage Current F-VCC Standby Current 2,11 4 Notes Min. Typ. Max. 1.5 1.5 20 Unit A A A Test Conditions VIN = VCC or GND VOUT = VCC or GND F-VCC = F-VCC Max., F-CE = F-RST = F-VCC 0.2V, F-WP = F-VCC or GND F-VCC = F-VCC Max., F-CE = GND 0.2V, F-WP = F-VCC or GND F-RST = GND 0.2V IOUT (F-RY/BY) = 0mA F-VCC = F-VCC Max., F-CE = VIL, F-OE = VIH, f = 5MHz IOUT = 0mA F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-CE = VIH F-VPP F-VCC F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 ICCAS ICCD F-VCC Automatic Power Savings Current F-VCC Reset Power-Down Current Average F-VCC Read Current Normal Mode Average F-VCC 8 Word Read Read Current Page Mode F-VCC (Page Buffer) Program Current F-VCC Block Erase, Full Chip Erase Current F-VCC (Page Buffer) Program or Block Erase Suspend Current F-VPP Standby or Read Current F-VPP (Page Buffer) Program Current F-VPP Block Erase, Full Chip Erase Current F-VPP (Page Buffer) Program Suspend Current F-VPP Block Erase Suspend Current 2,5 4 20 A 2 2,10 4 15 20 25 A mA ICCR 2,10 2,6,10 2,6,10 2,6,10 2,6,10 2,3,10 2,7,10 2,6,7,10 2,6,7,10 2,6,7,10 2,6,7,10 2,7,10 2,7,10 2,7,10 2,7,10 5 20 10 10 10 10 2 2 10 2 5 2 10 2 10 10 60 20 30 30 200 5 5 30 5 15 5 200 5 200 mA mA mA mA mA A A A mA A mA A A A A ICCW ICCE ICCWS ICCES IPPS IPPR IPPW IPPE IPPWS IPPES LRS1808A 19 DC Electrical Characteristics (Continue) (TA = -30C to +85C, F-VCC = 2.7V to 3.3V, S-VCC = 2.7V to 3.1V) Symbol ISB ISLP ICC1 ICC2 VIL VIH VOL VOH VPPLK VPPH1 VPPH2 VLKO Notes: 1. VCC includes both F-VCC and S-VCC. 2. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC = 3.0V and TA = +25C unless VCC is specified. 3. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 4. Block erase, full chip erase, (page buffer) program are inhibited when F-VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.) , between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.). 5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 6. Sampled, not 100% tested. 7. F-VPP is not used for power supply pin. With F-VPP VPPLK, block erase, full chip erase, (page buffer) program cannot be executed and should not be attempted. Applying 12V 0.3V to F-VPP provides fast erasing or fast programming mode. In this mode, F-VPP is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the VCC power bus. Applying 12V 0.3V to F-VPP during erase/program can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V 0.3V for a total of 80 hours maximum. 8. Memory cell data is held. (S-CE2 = "VIH") 9. Memory cell data is not held. (S-CE2 = "VIL") 10. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane. 11. Includes F-RY/BY. Parameter S-VCC Standby Current S-VCC Sleep Mode Current S-VCC Operation Current S-VCC Operation Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage F-VPP Lockout during Normal Operations F-VPP during Block Erase, Full Chip Erase,(PageBuffer) Program F-VPP during Block Erase, (PageBuffer) Program F-VCC Lockout Voltage 6 6 6,11 6 4,6,7 7 7 1.65 11.7 1.5 3 12 VCC -0.3 0.4 3.3 12.3 -0.3 VCC -0.3 Notes 8 9 Min. Typ. Max. 80 15 20 3 0.3 VCC +0.3 0.3 Unit A A mA mA V V V V V V V V IOL = 0.5mA IOH = -0.5mA Conditions S-CE1 S-VCC - 0.2V S-CE2 0.2V tCYCLE = Min., II/O = 0mA tCYCLE = 1s, II/O = 0mA LRS1808A 20 12. AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load 12.2 Read Cycle (TA = -30C to +85C, F-VCC = 2.7V to 3.3V) Symbol tAVAV tAVQV tELQV tAPA tGLQV tPHQV tEHQZ, tGHQZ tELQX tGLQX tOH Notes: 1. Sampled, not 100% tested. 2. F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-CE without impact to tELQV. Read Cycle Time Address to Output Delay F-CE to Output Delay Page Address Access Time F-OE to Output Delay F-RST High to Output Delay F-CE or F-OE to Output in High - Z, Whichever Occurs First F-CE to Output in Low - Z F-OE to Output in Low - Z Output Hold from First Occurring Address, F-CE or F-OE change 1 1 1 1 0 0 0 2 2 Parameter Notes Min. 85 85 85 30 20 150 20 Max. Unit ns ns ns ns ns ns ns ns ns ns 0 V to 2.7 V 5 ns 1.35 V 1TTL + CL (50pF) LRS1808A 21 12.3 Write Cycle (F-WE / F-CE Controlled)(1,2) (TA = -30C to +85C, F-VCC = 2.7V to 3.3V) Symbol tAVAV tPHWL (tPHEL) tELWL (tWLEL) Write Cycle Time F-RST High Recovery to F-WE (F-CE) Going Low F-CE (F-WE) Setup to F-WE (F-CE) Going Low 3 4 4 8 8 Parameter Notes Min. 85 150 0 60 40 50 0 0 0 5 3 3 3, 6 3, 6 3, 7 3 30 0 200 30 0 0 tAVQV+40 100 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tWLWH (tELEH) F-WE (F-CE) Pulse Width tDVWH (tDVEH) Data Setup to F-WE (F-CE) Going High tAVWH (tAVEH) Address Setup to F-WE (F-CE) Going High tWHEH (tEHWH) F-CE (F-WE) Hold from F-WE (F-CE) High tWHDX (tEHDX) Data Hold from F-WE (F-CE) High tWHAX (tEHAX) Address Hold from F-WE (F-CE) High tWHWL (tEHEL) F-WE (F-CE) Pulse Width High tSHWH (tSHEH) F-WP High Setup to F-WE (F-CE) Going High tVVWH (tVVEH) F-VPP Setup to F-WE (F-CE) Going High tWHGL (tEHGL) Write Recovery before Read tQVSL tQVVL tWHR0 (tEHR0) Notes: F-WP High Hold from Valid SRD, F-RY/BY High-Z F-VPP Hold from Valid SRD, F-RY/BY High-Z F-WE (F-CE) High to SR.7 Going "0" tWHRL (tEHRL) F-WE (F-CE) High to F-RY/BY Going Low 1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program operations are the same as during read-only operations. See the AC Characteristics for read cycle. 2. A write operation can be initiated and terminated with either F-CE or F-WE. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of F-CE or F-WE (whichever goes low last) to the rising edge of F-CE or F-WE (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. 5. Write pulse width high (tWPH) is defined from the rising edge of F-CE or F-WE (whichever goes high first) to the falling edge of F-CE or F-WE (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. F-VPP should be held at F-VPP=VPPH1/2 until determination of block erase, (page buffer) program success (SR.1/3/4/5=0) and held at F-VPP=VPPH1 until determination of full chip erase success (SR.1/3/5=0). 7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes command=tAVQV+100ns. 8. See 5.1 Command Definitions for valid address and data for block erase, full chip erase, (page buffer) program or lock bit configuration. LRS1808A 22 12.4 Block Erase, Full Chip Erase, (Page Buffer) Program Performance(3) (TA = -30C to +85C, F-VCC = 2.7V to 3.3V) Symbol Parameter Page Buffer Command Notes is Used or not Used 2 2 2 2 2 2 2 2 2 4 4 5 500 Not Used Used Not Used Used Not Used Used F-VPP=VPPH1 (In System) Min. Typ. (1) F-VPP=VPPH2 (In Manufacturing) (2) Unit (2) Max. Min. Typ. (1) Max. tWPB tWMB 4K-Word Parameter Block Program Time 32K-Word Main Block Program Time 0.05 0.03 0.38 0.24 11 7 0.3 0.6 40 5 5 0.3 0.12 2.4 1 200 100 4 5 350 10 20 500 0.04 0.02 0.31 0.17 9 5 0.2 0.5 0.12 0.06 1 0.5 185 90 4 5 s s s s s s s s s tWHQV1/ Word Program Time tEHQV1 tWHQV2/ 4K-Word Parameter Block tEHQV2 Erase Time tWHQV3/ 32K-Word Main Block tEHQV3 Erase Time Full Chip Erase Time tWHRH1/ (Page Buffer) Program Suspend tEHRH1 Latency Time to Read tWHRH2/ Block Erase Suspend tEHRH2 Latency Time to Read tERES Notes: Latency Time from Block Erase Resume Command to Block Erase Suspend Command 5 5 10 20 s s s 1. Typical values measured at F-VCC = 3.0V, F-VPP = 3.0V or 12V, and TA= +25C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (F-WE or F-CE going high) until SR.7 going "1"or F-RY/BY going High-Z. 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished. LRS1808A 23 12.5 Flash Memory AC Characteristics Timing Chart AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes or Query Code A20-0 (A) VIH VIL tAVQV VALID ADDRESS tEHQZ tGHQZ F-CE (E) VIH VIL tELQV F-OE (G) VIH VIL F-WE (W) VIH VIL tGLQV tGLQX tELQX tOH DQ15-0 (D/Q) VOH VOL High - Z VALID OUTPUT tPHQV VIH F-RST (P) VIL LRS1808A 24 AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks A20-3 (A) VIH VIL VALID ADDRESS tAVQV A2-0 (A) VIH VIL VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS F-CE (E) VIH VIL tELQV tEHQZ tGHQZ F-OE (G) VIH VIL F-WE (W) VIH VIL tGLQV tGLQX tELQX tAPA tOH DQ15-0 (D/Q) VOH VOL High - Z tPHQV VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VIH F-RST (P) VIL LRS1808A 25 AC Waveform for Write Operations(F-WE / F-CE Controlled) NOTE 1 A20-0 (A) VIH VIL NOTE 2 VALID ADDRESS tAVAV NOTE 3 VALID ADDRESS tAVWH (tAVEH) NOTE 4 VALID ADDRESS NOTE 5 tWHAX VIH VIL tELWL (tWLEL) tWHEH (tEHWH) (tEHAX) F-CE (E) NOTES 5, 6 tWHGL (tEHGL) F-OE (G) VIH VIL tPHWL (tPHEL) tWHWL (tEHEL) NOTES 5, 6 F-WE (W) VIH VIL tWLWH (tELEH ) VIH VIL DATA IN DATA IN VALID SRD tWHDX (tEHDX) tDVWH (tDVEH) tWHQV1,2,3 (tEHQV1,2,3) DQ15-0 (D/Q) High - Z F-RY/BY (R) (SR.7) (1) VOL (0) tWHR0 (tEHR0) tWHRL (tEHRL) F-RST (P) VIH VIL tSHWH (tSHEH) tQVSL F-WP (S) VIH VIL tVVWH (tVVEH) tQVVL VPPH1,2 F-VPP (V) VPPLK VIL Notes: 1. F-VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, F-OE and F-CE must be driven active, and F-WE de-asserted. LRS1808A 26 12.6 Reset Operations (TA = -30C to +85C, F-VCC = 2.7V to 3.3V) Symbol tPLPH tPLRH tVPH tVHQV Notes: 1. A reset time, tPHQV, is required from the later of SR.7 (F-RY/BY) going "1" (High-Z) or F-RST going high until outputs are valid. See the AC Characteristics - read cycle for tPHQV. 2. 4. tPLPH is <100ns the device may still reset but this is not guaranteed. If F-RST asserted while a block erase, full chip erase or (page buffer) program operation is not executing, the reset will complete within 100ns. 3. Sampled, not 100% tested. Parameter F-RST Low to Reset during Read (F-RST should be low during power-up.) F-RST Low to Reset during Erase or Program F-VCC 2.7V to F-RST High F-VCC 2.7V to Output Delay Notes 1, 2, 3 1, 3, 4 1, 3, 5 3 100 1 Min. 100 22 Max. Unit ns s ns ms 5. When the device power-up, holding F-RST low minimum 100ns is required after F-VCC has been in predefined range and also has been in stable there. AC Waveform for Reset Operation tPHQV F-RST(P) VIH VIL VOH VOL tPLPH High-Z VALID OUTPUT DQ15-0 (D/Q) (A) Reset during Read Array Mode SR.7=1 ABORT tPLRH VIH F-RST (P) VIL VOH VOL tPLPH High-Z COMPLETE tPHQV DQ15-0 (D/Q) VALID OUTPUT (B) Reset during Erase or Program Mode 2.7V F-VCC GND tVPH VIH VIL VOH VOL tVHQV tPHQV F-RST(P) DQ15-0 (D/Q) High-Z VALID OUTPUT (C) F-RST rising timing LRS1808A 27 13. AC Electrical Characteristic for Smartcombo RAM 13.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle (1,2,3) (TA = -30C to +85C, S-VCC = 2.7V to 3.1V) Symbol tRC tAA tACE tOE tBE tASC tAHC tC1H tCLZ tCHZ tBLZ tBHZ tOLZ tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Byte Enable Access Time Address Setup to S-CE1 Low Address Hold to S-CE1 High S-CE1 High Pulse Width S-CE1 Low to Output Active S-CE1 High to Output in High-Z S-UB or S-LB Low to Output Active S-UB or S-LB High to Output in High-Z S-OE Low to Output Active S-OE High to Output in High-Z Output Hold from Address Change 5 0 30 0 30 0 0 30 0 30 Parameter Notes Min. 85 Max. 32,000 85 85 40 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.3 V to VCC - 0.3 V 3 ns 1/2 VCC 1TTL +CL (50pF)(1) Notes: It is possible to control data width by S-LB and S-UB pins. 1. Reading data from lower byte Data can be read when the address is set while holding S-CE1 = Low, S-CE2 = High, S-OE = Low, S-WE = High and S-LB = Low. 2. Reading data from upper byte Data can be read when the address is set while holding S-CE1 = Low, S-CE2 = High, S-OE = Low, S-WE = High and S-UB = Low. 3. Reading data from both bytes Data can be read when the address is set while holding S-CE1 = Low, S-CE2 = High, S-OE = Low, S-WE = High, S-LB = Low and S-UB = Low. LRS1808A 28 13.3 Write Cycle (1,2,3,4,5,6,7,8) (TA = -30C to +85C, S-VCC = 2.7V to 3.1V) Symbol tWC tCW tASC tAHC tC1H tAW tAS tWP tBW tWR tDW tDH tOW tWHZ Notes: 1. Writing data into lower byte (S-WE controlled) 1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = Low and S-UB = High. 2) The data on lower byte are latched up into the memory cell during S-WE = Low and S-LB = Low. 2. Witing data into lower byte (S-LB controlled) 1) Data can be written by adding Low pulse into S-LB when the address is set while holding S-CE1 = Low, S-CE2 = High, S-UB = High and S-WE = Low. 2) The data on lower byte are latched up into memory cell during S-WE = Low and S-LB = Low. 3. Writing data into upper byte (S-WE controlled) 1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = High and S-UB = Low. 2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low. 4. Writing data into upper byte (S-UB controlled) 1) Data can be written by adding Low pulse S-UB when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = High and S-WE = Low. 2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low. 5. Writing data into both byte (S-WE controlled) 1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = Low and S-UB = Low. 2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low. 6. Writing data into both byte (S-LB, S-UB controlled) 1) Data can be written by adding Low pulse into S-LB and S-UB when the address is set while holding S-CE1 = Low, S-CE2 = High and S-WE = Low. 2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low 7. Read or write with using both S-LB and S-UB, the timing edge of S-LB and S-UB must be same. 8. While DQ pins are in the output state, the data that is opposite to the output data should not be given. Write Cycle Time Chip Enable to End of Write Address Setup to S-CE1 Low Address Hold to S-CE1 High S-CE1 High Pulse Width Address Valid to End of Write Address Setup Time Write Pulse Width Byte Select Time Write Recovery Time Input Data Setup Time Input Data Hold Time S-WE High to Output Active S-WE Low to Output in High-Z Parameter Notes Min. 85 70 0 0 30 70 0 40 70 0 35 0 5 30 Max. 32,000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns LRS1808A 29 13.4 Power Up Timing (TA = -30C to +85C, S-VCC = 2.7V to 3.1V) Symbol tSHU tHPU Parameter S-CE1, S-CE2 Setup Time after Power Up Standby Hold Time after Power Up Notes Min. 0 300 Max. Unit ns s 13.5 Sleep Mode Timing(1) (TA = -30C to +85C, S-VCC = 2.7V to 3.1V) Symbol tSSP tSHP tC2LP tHPD Note: 1. When S-CE2 is low, the device will be in the Sleep Mode. In this case, an internal refresh stops and the data might be lost. 13.6 Address Skew Timing (TA = -30C to +85C, S-VCC = 2.7V to 3.1V) Symbol tSKEW Maximum Address Skew Parameter Notes Min. Max. 10 Unit ns Parameter S-CE1 High Setup Time for Sleep Mode Entry S-CE1 High Hold Time before Sleep Mode Exit S-CE2 Low Pulse Width S-CE1 High Hold Time after Sleep Mode Exit Notes Min. 0 0 30 300 Max. Unit ns ns ns s 13.7 Data Retention Timing(1) (TA = -30C to +85C, S-VCC = 2.7V to 3.1V) Symbol tBAH tCSH Note: 1. Either tBAH or tCSH required for data retention. Parameter Address Hold Time during Active S-CE1 Low Hold Time for Address Fix Notes Min. 85 85 Max. 32,000 32,000 Unit ns ns LRS1808A 30 13.8 Smartcombo RAM AC Characteristics Timing Chart Read Cycle Timing Chart Address S-CE1 S-LB S-UB S-OE DOUT VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z tASC tRC ADDRESS STABLE tAA tACE tBE tOE tOLZ tBLZ tCLZ tOH tAHC tCHZ tBHZ tOHZ VALID OUTPUT High-Z Note: 1. S-CE2 and S-WE must be High level for entire read cycle. LRS1808A 31 Write Cycle Timing Chart (S-WE Controlled) tWC VIH Address VIL tAW tCW ADDRESS STABLE VIH S-CE1 VIL tASC tAHC tBW VIH S-UB S-LB VIL tAS tWP tWR VIH S-WE VIL tWHZ tOW Data Undefined VOH DOUT VOL tDW tDH VIH DIN VIL High-Z High-Z V ALID INPUT Notes: 1. If S-OE = High, DOUT will be a High-Z state. 2. S-CE2 and S-WE must be High level for entire write cycle. LRS1808A 32 Write Cycle Timing Chart (S-UB, S-LB Controlled) Address S-CE1 S-UB S-LB S-WE DOUT DIN VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL High-Z tASC tAS tWC ADDRESS STABLE tAW tCW tBW tWP tBLZ tWR tAHC High-Z tWHZ tDW tDH VALID INPUT Notes: 1. If S-OE = High, DOUT will be a High-Z state. 2. S-CE2 and S-WE must be High level for entire write cycle. LRS1808A 33 Standby Mode Timing VIH Address VIL tC1H VIH S-CE1 VIL tAHC tASC Active Standby Active Note: 1. When S-CE1= High, the device will be in the standby cycle. In this case data DQ pins are High-Z and all input pins are inhibited. Power Up Timing VIH S-CE1 VIL tSHU tHPU VIH S-CE2 VIL VIH S-VCC VIL VCC (min.) LRS1808A 34 Sleep Mode Timing VIH S-CE1 VIL tSHP tHPD tC2LP VIH S-CE2 VIL tSSP Address Skew Timing 1 VIH Address VIL tSKEW tRC / tWC VIH S-CE1 VIL Note: 1. tSKEW is from first address change to last address change. LRS1808A 35 Address Skew Timing 2 VIH Address VIL tSKEW tRC / tWC VIH S-CE1 VIL Note: 1. tSKEW is from activate to last address change. Address Skew Timing 3 VIH Address VIL tSKEW VIH S-CE1 VIL Note: 1. tSKEW is from first address change to standby. LRS1808A 36 Data Retention Timing 1 tBAH VIH Address VIL VIH S-CE1 VIL Notes: 1. This applies for both read and write. Data Retention Timing 2 tCSH VIH Address VIL No Change VIH S-CE1 VIL Notes: 1. This applies for both read and write. LRS1808A 37 14. Notes This product is a stacked CSP package that a 32M (x16) bit Flash Memory and a 16M (x16) bit Smartcombo RAM are assembled into. - Supply Power Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3V. - Power Supply and Chip Enable of Flash Memory and Smartcombo RAM (F-CE, S-CE1, S-CE2) S-CE1 should not be low and S-CE2 should not be high when F-CE is low simultaneously. If the two memories are active together, possibly they may not operate normally by interference noises or data collision on DQ bus. Both F-VCC and S-VCC are needed to be applied by the recommended supply voltage at the same time except Smartcombo RAM data retention mode. - Power Up Sequence When turning on Flash memory power supply, keep F-RST low. After F-VCC reaches over 2.7V, keep F-RST low for more than 100 nsec. - Device Decoupling The power supply is needed to be designed carefully because one of the Smartcombo RAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between Smartcombo RAM and Flash Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2). LRS1808A 38 15. Flash Memory Data Protection Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as false commands and causes undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: ! The below describes data protection method. 1. Protection of data in each block * ny locked block by setting its block lock bit is protected against the data alternation. When F-WP is low, any lockeddown block by setting its block lock-down bit is protected from lock status changes. By using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). * For detailed block locking scheme, see Chapter 5.Command Definitions for Flash Memory. 2. Protection of data with F-VPP control * When the level of F-VPP is lower than VPPLK (F-VPP lockout voltage), write functions to all blocks are disabled. All blocks are locked and the data in the blocks are completely protected. 3. Protection of data with F-RST * Especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing F-RST to low, which inhibits write operation to all blocks. * For detailed description on F-RST control, see Chapter 12.6 AC Electrical Characteristics for Flash Memory, Reset Operations. ! Protection against noises on F-WE signal To prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on F-WE signal. LRS1808A 39 16. Design Considerations 1. Power Supply Decoupling To avoid a bad effect to the system by flash memory and Smartcombo RAM power switching characteristics, each device should have a 0.1F ceramic capacitor connected between F-VCC and GND, between F-VPP and GND and between S-VCC and GND. Low inductance capacitors should be placed as close as possible to package leads. 2. F-VPP Trace on Printed Circuit Boards Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the F-VPP Power Supply trace. Use similar trace widths and layout considerations given to the FVCC power bus. 3. The Inhibition of Overwrite Operation Please do not execute reprograming "0" for the bit which has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprograming "0" to the data which has been programed "1". * Program "0" for the bit in which you want to change data from "1" to "0". * Program "1" for the bit which has already been programed "0". For example, changing data from "1011110110111101" to "1010110110111100" requires "1110111111111110" programing. 4. Power Supply Block erase, full chip erase, word write with an invalid F-VPP (See Chapter 11. DC Electrical Characteristics) produce spurious results and should not be attempted. Device operations at invalid F-VCC voltage (See Chapter 11. DC Electrical Characteristics) produce spurious results and should not be attempted. 17. Related Document Information(1) Document No. FUM00701 Note: 1. International customers should contact their local SHARP or distribution sales offices. Document Name LH28F320BF, LH28F640BF, LH28F128BF Series Appendix i A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) F-VCC GND VIH F-RP (F-RST) (P) tVR tVPH tPHQV VIL VCCWH1/2 (VPPH1/2) GND tR VIH or F-VCCW *1 (V) (F-VPP) tF tAVQV Valid Address tF tELQV tR or tF ADDRESS (A) VIL VIH F-CE (F-BE) (E) tR VIL VIH F-WE (W) VIL tF VIH F-OE (G) tGLQV tR VIL VIH F-WP (S) VIL DATA VOH (D/Q) High-Z VOL Valid Output *1 To prevent the unwanted writes, system designers should consider the design, which applies F-V CCW (F-VPP) to 0V during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations. See the application note AP-007-SW-E for details. Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "AC Electrical Characteristics for Flash Memory" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. Rev. 1.10 ii A-1.1.1 Rise and Fall Time Symbol tVR tR tF F-VCC Rise Time Parameter Notes 1 1, 2 1, 2 Min. 0.5 Max. 30000 1 1 Unit s/V s/V s/V Input Signal Rise Time Input Signal Fall Time NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. Rev. 1.10 iii A-1.2 Glitch Noises Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal VIH (Min.) Input Signal VIH (Min.) VIL (Max.) VIL (Max.) Input Signal Input Signal (a) Acceptable Glitch Noises (b) NOT Acceptable Glitch Noises Figure A-2. Waveform for Glitch Noises See the "DC Electrical Characteristics" described in specifications for VIH (Min.) and VIL (Max.). Rev. 1.10 iv A-2 RELATED DOCUMENT INFORMATION(1) Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, VPP Electric Potential Switching Circuit NOTE: 1. International customers should contact their local SHARP or distribution sales office. Rev. 1.10 |
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