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DATA SHEET
PD789860, 789861
8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
The PD789860 and PD789861 are products of the PD789860, 789861 Subseries in the 78K/0S Series. In addition to an 8-bit CPU, they have on-chip hardware for keyless entry, including EEPROM , a key return function, and a timer with a carrier generator that can easily output waveforms for infrared remote control. The
TM
PD78E9860 and PD78E9861, EEPROM products that can operate using the same power supply voltage as mask
ROM products, and various development tools also are under development. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD789860, 789861 Subseries User's Manual:
78K/0S Series User's Manual Instructions:
U14826E U11047E
FEATURES
Internal ROM: 4 KB On-chip EEPROM needed for reading/writing by program in RAM area: 32 bytes System clock oscillator * PD789860: Crystal/ceramic oscillator * PD789861: RC oscillator (externally attached resistor and capacitor) Minimum instruction execution time * PD789860: 0.4 s/1.6 s (@ fX = 5.0 MHz operation) * PD789861: 2.0 s/8.0 s (@ fCC = 1.0 MHz operation) I/O ports: 14 Timer: 3 channels * 8-bit timer: 2 channels * Watchdog timer: 1 channel On-chip power-on-clear circuit On-chip bit sequential buffer Power supply voltage: VDD = 1.8 to 3.6 V
APPLICATIONS
Keyless entry and other automotive electrical equipment In this Data Sheet, the oscillation frequency of a crystal/ceramic oscillator (PD789860) is described as fX and the oscillation frequency of an RC oscillator (PD789861) is described as fCC.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U13917EJ1V1DS00 (1st edition) Date Published August 2001 N CP(K)
The mark
shows major revised points.
(c)
1999, 2000
PD789860, 789861
ORDERING INFORMATION
Part Number Package 20-pin plastic SSOP (7.62 mm (300)) 20-pin plastic SSOP (7.62 mm (300))
PD789860MC-xxx-5A4 PD789861MC-xxx-5A4
Remark xxx indicates ROM code suffix.
2
Data Sheet U13917EJ1V1DS
PD789860, 789861
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 30-pin 28-pin
PD789046 PD789026 PD789088 PD789074 PD789014
PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789074 with enhanced timer and increased ROM and RAM capacity PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation
Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
LCD drive
PD789177Y PD789167Y
PD789167 with enhanced A/D converter (10 bits) PD789104A with enhanced timer PD789146 with enhanced A/D converter (10 bits) PD789104A with added EEPROMTM PD789124A with enhanced A/D converter (10 bits) RC oscillation version of the PD789104A PD789104A with enhanced A/D converter (10 bits) PD789026 with added A/D converter and multiplier
144-pin 88-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 52-pin 52-pin
PD789835 PD789830 PD789488 PD789477 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327
USB
UART, 8-bit A/D converter, and dot LCD (Display output total: 96) UART and dot LCD (40 x 16) SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 x 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789407A with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 SIO and on-chip voltage booster type LCD (24 x 4) 8-bit A/D converter and on-chip voltage booster type LCD (23 x 4) SIO and resistance division type LCD (24 x 4)
78K/0S Series
64-pin 44-pin
PD789803 PD789800
Inverter control
For PC keyboard, on-chip USB HUB function For PC keyboard, on-chip USB function
44-pin
PD789842
On-chip bus controller
On-chip inverter controller and UART
30-pin
PD789850
Keyless entry
On-chip CAN controller
20-pin 20-pin
PD789861 PD789860
VFD drive
RC oscillation version of the PD789860 On-chip POC and key return circuit
52-pin
PD789871
Meter control
On-chip VFD controller (Display output Total: 25)
64-pin
PD789881
UART and resistance division type LCD (26 x 4)
TM
Remark VFD (Vacuum Fluorescent Display) is referred to as "FIP " (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.
Data Sheet U13917EJ1V1DS
3
PD789860, 789861
The major functional differences among the subseries are listed below.
Series for LCD drive, general-purpose applications
Function ROM Capacity Timer 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface I/O VDD MIN. Value 34 1.8 V 24 - Remarks
Subseries Name Small-scale PD789046 package, PD789026 generalPD789088 purpose applications PD789074 16 KB
4 KB to 16 KB
1 ch 3 ch 1 ch 2 ch 3 ch 1 ch
1 ch
1 ch -
1 ch
-
-
1 ch (UART: 1 ch)
16 KB to 32 KB
2 KB to 8 KB 2 KB to 4 KB
PD789014
Small-scale package, generalpurpose applications and A/D converter
- 1 ch 1 ch - 1 ch - 8 ch - 4 ch - 4 ch - 4 ch 8 ch - 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1 ch) 1 ch (UART: 1 ch)
22 31 1.8 V 20 - On-chip EEPROM RC oscillation version - 37 1.8 V Dot LCD Note supported 30 2.7 V 8 ch 8 ch - 7 ch - 7 ch - 6 ch - 6 ch - 2 ch (UART: 1 ch) - 1 ch 23 RC oscillation version - 40 2 ch (UART: 1 ch) 1 ch (UART: 1 ch) 45 1.8 V 43 30 -
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
16 KB to 24 KB 8 KB to 16 KB 2 KB to 8 KB
LCD drive
PD789835 PD789830 PD789488 PD789477 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327
24 KB to 60 KB 24 KB 32 KB 24 KB 12 KB to 24 KB 12 KB to 16 KB
6 ch 1 ch 3 ch
- 1 ch
1 ch
1 ch
3 ch -
2 ch
- 6 ch - 6 ch
8 KB to 16 KB 4 KB to 24 KB -
-
1 ch -
18 21
Note 10-bit timer: 1 channel
4
Data Sheet U13917EJ1V1DS
PD789860, 789861
Series for ASSP
Function ROM Capacity Timer 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface I/O VDD MIN. Value 41 3.6 V 31 4.0 V 30 4.0 V 18 4.0 V - - - Remarks
Subseries Name USB Inverter control On-chip bus controller Keyless entry
PD789803 PD789800 PD789842 PD789850
8 KB to 16 KB
2 ch 3 ch 1 ch
- Note 1 1 ch
- 1 ch -
1 ch 1 ch 1 ch
- 8 ch 4 ch
- - -
8 KB 8 KB to 16 KB 16 KB
2 ch (USB: 1 ch) 1 ch (UART: 1 ch) 2 ch (UART: 1 ch) -
PD789861
4 KB
2 ch
-
-
1 ch
-
-
14 1.8 V RC oscillation version, on-chip EEPROM On-chip EEPROM
PD789860
VFD drive Meter control
PD789871 PD789881
4 KB to 8 KB 16 KB
3 ch 2 ch
- 1 ch
1 ch -
1 ch 1 ch
- -
- -
1 ch 1 ch (UART: 1 ch)
33 2.7 V 28 2.7 V
Note 2
- -
Notes 1. 2.
10-bit timer: 1 channel Flash memory version: 3.0 V
Data Sheet U13917EJ1V1DS
5
PD789860, 789861
OVERVIEW OF FUNCTIONS
Part Number Item Internal memory ROM High-speed RAM EEPROM Oscillator Minimum instruction execution time 4 KB 128 bytes 32 bytes Ceramic/crystal oscillator 0.4 s/1.6 s (@ fX = 5.0 MHz operation) 8 bits x 8 registers * 16-bit operation * Bit manipulation (set, reset, test), etc. I/O ports Total: CMOS I/O: 14 10 RC oscillator 2.0 s/8.0 s (@ fCC = 1.0 MHz operation)
PD789860
PD789861
General-purpose registers Instruction set
CMOS input: 4 Timer * 8-bit timer: 2 channels
* Watchdog timer: 1 channel Power-on-clear circuit POC circuit Generates internal reset signal according to comparison of detection voltage to power supply voltage Generates interrupt request signal according to comparison of detection voltage to power supply voltage 8 bits x 8 bits = 16 bits Generates key return signal according to falling edge detection Maskable Non-maskable Internal: 5 Internal: 1, External: 1 VDD = 1.8 to 3.6 V TA = -40 to +85C 20-pin plastic SSOP (7.62 mm (300))
LVI circuit
Bit sequence buffer Key return function Vectored interrupt sources Power supply voltage Operating ambient temperature Package
6
Data Sheet U13917EJ1V1DS
PD789860, 789861
CONTENTS 1. PIN CONFIGURATION (TOP VIEW).......................................................................................................9 2. BLOCK DIAGRAM ................................................................................................................................10 3. PIN FUNCTIONS ..................................................................................................................................11
3.1 3.2 3.3 Port Pins .....................................................................................................................................................11 Non-Port Pins .............................................................................................................................................11 Pin I/O Circuits and Recommended Connection of Unused Pins .........................................................12
4. MEMORY SPACE..................................................................................................................................13 5. EEPROM................................................................................................................................................14 6. PERIPHERAL HARDWARE FUNCTIONS ...........................................................................................15
6.1 6.2 6.3 6.4 6.5 6.6 Ports............................................................................................................................................................15 Clock Generator .........................................................................................................................................16 Timer ...........................................................................................................................................................17 Power-On-Clear Circuits............................................................................................................................21 Bit Sequential Buffer .................................................................................................................................23 Key Return Circuit .....................................................................................................................................23
7. INTERRUPT FUNCTIONS ....................................................................................................................24
7.1 7.2 Types of Interrupt Functions ....................................................................................................................24 Sources and Configuration of Interrupts.................................................................................................24
8. STANDBY FUNCTION ..........................................................................................................................26 9. RESET FUNCTION ...............................................................................................................................26 10. MASK OPTIONS ...................................................................................................................................27 11. INSTRUCTION SET SUMMARY...........................................................................................................28
11.1 Conventions ...............................................................................................................................................28 11.1.1 Operand identifiers and description methods ..................................................................................28 11.1.2 Explanation of operation column .....................................................................................................29 11.1.3 Explanation of flags column.............................................................................................................29 11.2 List of Operations ......................................................................................................................................30
12. ELECTRICAL SPECIFICATIONS .........................................................................................................35 13. EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES)....47 14. PACKAGE DRAWING ..........................................................................................................................48 15. RECOMMENDED SOLDERING CONDITIONS ....................................................................................49
Data Sheet U13917EJ1V1DS
7
PD789860, 789861
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................... 50 APPENDIX B. RELATED DOCUMENTS................................................................................................... 52
8
Data Sheet U13917EJ1V1DS
PD789860, 789861
1. PIN CONFIGURATION (TOP VIEW)
* 20-pin plastic SSOP (7.62 mm (300))
PD789860MC-xxx-5A4 PD789861MC-xxx-5A4
RESET X1(CL1) X2(CL2) VSS IC VDD P00 P01 P02 P03
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
P21/TMI P20/TMO/BSFO P07 P06 P05 P04 P43/KR13 P42/KR12 P41/KR11 P40/KR10
Caution Connect the IC (Internally Connected) pin directly to V66. Remark Pin connections in parentheses apply to the PD789861. BSFO: CL1, CL2: IC: KR10 to KR13: P00 to P07: P20, P21: P40 to P43: Bit sequential buffer output RC oscillator Internally connected Key return Port 0 Port 2 Port 4 RESET: TMI: TMO: V'': V66: X1, X2: Reset Timer input Timer output Power supply Ground Crystal/ceramic oscillator
Data Sheet U13917EJ1V1DS
9
PD789860, 789861
2. BLOCK DIAGRAM
PORT 0
8-bit timer 30 Cascaded 16-bit timer counter 8-bit timer/event counter 40
P00 to P07
PORT 2 78K/0S CPU core ROM PORT 4
P20, P21
TMI/P21 TMO/P20 /BSFO
P40 to P43 RESET X1 (CL1) X2 (CL2)
Bit seq. buffer
System control
Watchdog timer RAM KR10/P40 to KR13/P43 Key return 10 EEPROM Power Power on clear on clear
Low voltage indicator
VDD
VSS
IC
Remark Items in parentheses apply to the PD789861.
10
Data Sheet U13917EJ1V1DS
PD789860, 789861
3. PIN FUNCTIONS
3.1 Port Pins
I/O I/O Function Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Port 2 2-bit I/O port Input/output can be specified in 1-bit units. Port 4 4-bit input-only port. An on-chip pull-up resistor can be specified by the mask option. After Reset Alternate Function Input -
Pin Name P00 to P07
P20 P21 P40 to P43
I/O
Input
TMO/BSFO TMI
Input
Input
KR10 to KR13
3.2
Non-Port Pins
I/O Input Output Output Input 8-bit timer (TM40) input 8-bit timer (TM40) output Bit sequential buffer (BSF10) output Key return input Function After Reset Alternate Function Input Input Input Input P21 P20/BSFO P20/TMO P40 to P43
Pin Name TMI TMO BSFO KR10 to KR13 X1Note 1 X2
Note 1
Input - Input - Input - - -
Connecting crystal resonator for system clock oscillation
- -
- - - - -
CL1
Note 2
Connecting resistor (R) and capacitor (C) for system clock oscillation
- -
CL2Note 2 RESET VDD VSS IC
System reset input Positive power supply Ground potential Internally connected. Connect directly to VSS.
Input - - -
- - -
Notes 1. PD789860 only. 2. PD789861 only.
Data Sheet U13917EJ1V1DS
11
PD789860, 789861
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type for each pin and recommended connections of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name P00 to P07 P20/TMO/BSFO P21/TMI P40/KR10 to P43/KR13 RESET IC 2-E 2 - - Connect directly to VSS. Input Connect directly to VDD or VSS. - Input/Output Circuit Type 5 8 I/O I/O Input: Recommended Connection of Unused Pins Independently connect to VDD or VSS via a resistor.
Output: Leave open.
Figure 3-1. Pin I/O Circuits
Type 2
Type 5
VDD Data IN Output disable N-ch VSS P-ch IN/OUT
Schmitt-triggered input with hysteresis characteristics
Input enable
Type 2-E
Type 8 VDD Pull-up resistor (Mask option) VDD Data P-ch IN/OUT Output disable IN N-ch VSS
12
Data Sheet U13917EJ1V1DS
PD789860, 789861
4. MEMORY SPACE
The PD789860 and PD789861 can each access a 64 KB memory space. Figure 4-1 shows the memory map. Figure 4-1. Memory Map
FFFFH
Special function registers (SFRs) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 128 x 8 bits FE80H FE7FH Reserved F820H F81FH
Data memory space
EEPROM 32 x 8 bits
F800H F7FFH Reserved 1000H 0FFFH 0080H 007FH Program memory space Internal ROM 4096 x 8 bits CALLT table area 0040H 003FH Program area 000EH 000DH 0000H 0000H Vector table area 0FFFH Program area
Data Sheet U13917EJ1V1DS
13
PD789860, 789861
5. EEPROM
Besides internal high-speed RAM, the PD789860 and PD789861 have 32 x 8 bits of electrically erasable PROM (EEPROM) on-chip as data memory. Unlike normal RAM, EEPROM can maintain its contents even if its power supply is cut. EPROM, its electrical contents can be erased without using ultraviolet rays. Figure 5-1. EEPROM Block Diagram In addition, unlike
Internal bus EEPROM write control register 10 (EEWC10) Data latch
EWCS102 EWCS101 EWCS100 ERE10 EWST10 EWE10
fCLK/23 to fCLK/28 EEPROM timer Address latch EEPROM (32 x 8 bits) Read/write controller INTEE0 Prescaler 8-bit timer 40 (TM40) output
Remark f&/.: f; or f&&
14
Data Sheet U13917EJ1V1DS
PD789860, 789861
6. PERIPHERAL HARDWARE FUNCTIONS
6.1 Ports
The PD789860 and PD789861 are provided with the ports shown in Table 6-1, by which many kinds of control are possible. Moreover, these have a variety of alternate functions besides their functions as digital I/O ports. Refer to 3 PIN FUNCTIONS for details of the alternate functions. Table 6-1. Port Functions
Name Port 0 Port 2 Port 4 Pin Name P00 to P07 P20, P21 P40 to P43 Function I/O port. Input/output can be specified in 1-bit units. I/O port. Input/output can be specified in 1-bit units. Input-only port. Use of an on-chip pull-up resistor can be specified by the mask option.
Figure 6-1. Basic Configuration of CMOS Port
RDPORT
Selector
Internal bus
WRPORT Output latch Pmn WRPM
Pmn
PMmn
Caution Figure 6-1 is the basic configuration of a CMOS I/O port. The configuration varies according to the functions of alternate-function pins. Remarks PMmn: Bit n of port mode register m (m = 0, 2 n = 0 to 7) Pmn: RD: WR: Bit n of port m (m = 0, 2 n = 0 to 7) Port read signal Port write signal
Data Sheet U13917EJ1V1DS
15
PD789860, 789861
6.2 Clock Generator
The clock generator specifications differ as follows for the PD789860 and PD789861. * Ceramic/crystal oscillation: PD789860 Oscillates at frequency from 1.0 to 5.0 MHz. Minimum instruction execution time can be switched between 0.4
s and 1.6 s (@ 5.0 MHz operation).
* RC oscillation: PD789861 Oscillates at frequency of 1.0 MHz 15%. Minimum instruction execution time can be switched between 2.0 s and 8.0 s (@ 1.0 MHz operation). Figure 6-2. Clock Generator Block Diagram
Prescaler
X1 (CL1) X2 (CL2)
Clock to peripheral hardware System clock oscillator fX (fCC) Prescaler fX 22 fCC 22
Selector
Standby controller
Wait controller
CPU clock (fCPU)
STOP PCC0
Processor clock control register (PCC) Internal bus
Remark Items in the parentheses apply to the RC oscillation version (PD789861).
16
Data Sheet U13917EJ1V1DS
PD789860, 789861
6.3 Timer
Three channels of timers are incorporated. * 8-bit timer: * Watchdog timer: 2 channels 1 channel Table 6-2. Timer Operation
8-Bit Timer 30 Operating mode Function Interval timer External event counter Timer output Square wave output PWM output Interrupt request 1 channel - - - - 1 8-Bit Timer 40 1 channel 1 channel 1 output 1 output 1 output 1 Watchdog Timer 1 channel - - - - 1
Data Sheet U13917EJ1V1DS
17
Selector
Selector
18
8-bit timer mode control register (TMC30) Selector Bit 7 of TM40 (From Figure 6-4 (A)) fCLK/26 fCLK/28 Timer 40 interrupt request signal (From Figure 6-4 (B)) Carrier clock (In carrier generator mode) or timer 40 output signal (Other than carrier generator mode) (From Figure 6-4 (C))
Data Sheet U13917EJ1V1DS
)LJXUH %LW 7LPHU %ORFN 'LDJUDP
Internal bus
TCE30 TCL302 TCL301 TCL300 TMD301 TMD300
Decoder
8-bit compare register 30 (CR30) Match
8-bit timer counter 30 (TM30) Clear
OVF
Internal reset signal
From Figure 6-4 (D) Count operation starting signal (In cascade connection)
Selector Cascade connection mode INTTM30
PD789860, 789861
From Figure 6-4 (E) Timer 40 match signal (In cascade connection mode)
To Figure 6-4 (G) Timer 30 match signal (In carrier generator mode) To Figure 6-4 (F)
5HPDUN I&/. I; RU I&&
Timer 30 match signal (In cascade connection mode)
)LJXUH %LW 7LPHU %ORFN 'LDJUDP
Internal bus 8-bit timer mode control register 40 (TMC40) TCE40 TCL402 TCL401 TCL400TMD401 TMD400 TOE40 Carrier generator output control register 40 (TCA40) RMC40 NRZB40 NRZ40
8-bit compare register H40 (CRH40)
8-bit compare register 40 (CR40)
Decoder Selector From Figure 6-3 (G) Counter match signal from timer 30 (In carrier generator mode) Output controllerNote TMO/P20/BSFO To Figure 6-3 (C) Carrier clock (In carrier generator mode) or timer 40 output signal (Other than carrier generator mode) To Figure 6-3 (A) Bit 7 of TM40 (In cascade connection mode)
Match
Data Sheet U13917EJ1V1DS
F/F
fCLK fCLK/22 TMI/P21
Prescaler Selector
8-bit timer counter 40 (TM40) Clear Carrier generator mode PWM mode Cascade connection mode
OVF
TMI/2 TMI/22 TMI/23
Reset
Internal reset signal To Figure 6-3 (D) Count operation starting signal to timer 30 (In cascade connection mode) From Figure 6-3 (E) TM40 timer counter match signal (In cascade connection mode) INTTM40
PD789860, 789861
To Figure 6-3 (B) Timer 40 interrupt request signal (Count clock input signal to TM30)
From Figure 6-3 (F) TM30 match signal (In cascade connection mode)
1RWH )RU GHWDLOV UHIHU WR )LJXUH 5HPDUN I&/. I; RU I&&
19
PD789860, 789861
Figure 6-5. Block Diagram of Output Controller (Timer 40)
TOE40 RMC40 NRZ40 P20 output latch
PM20
Selector
F/F
TMO/P20/ BSFO Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode)
Carrier generator mode
Figure 6-6. Watchdog Timer Block Diagram
Internal bus
fCLK 24 fCLK 26
Prescaler fCLK 28 fCLK 210
TMMK4
TMIF4
Selector
INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request
7-bit counter Clear
Controller
3
TCL22 TCL21 TCL20 Timer clock select register 2 (TCL2)
RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus
Remark f&/.: f; or f&&
20
Data Sheet U13917EJ1V1DS
PD789860, 789861
6.4 Power-On-Clear Circuits
The power-on-clear circuits include the following two circuits, which have the following functions. (1) Power-on-clear (POC) circuit * Compares the detection voltage (V32&) with the power supply voltage (V'') and generates an internal reset signal if V'' < V32&. * By using a mask option, it is possible to select a POC switching circuit, normally operating circuit, or normally halted circuit. When a POC switching circuit is selected, POC operation can be controlled by software (refer to 10 MASK OPTIONS). * This circuit can operate even in STOP mode. (2) Low-voltage detection (LVI) circuit * Compares the detection voltage (V/9,) to the power supply voltage (V'') and generates an interrupt request signal (INTLVI) if V'' < V/9,. * Eight levels of detection voltage can be selected using software. * This circuit stops operation in STOP mode.
Data Sheet U13917EJ1V1DS
21
PD789860, 789861
Figure 6-7. Power-On-Clear Circuit Block Diagram
VDD VDD N ch N ch
+ -
Internal reset signal
Detection voltage source (VPOC)
POCOF1 POCMK1 POCMK0 Power-on-clear register 1 (POCF1) Internal bus
Figure 6-8. Low-Voltage Detection Circuit Block Diagram
VDD
Nch
Low-voltage detection level selector
VDD LVI stop signal (set during STOP instruction execution or reset signal generation) INTLVI1 N-ch
Detection voltage source (VLVI)
Nch + -
LVS12 LVS11 LVS10
Low-voltage detection level selection register 1 (LVIS1) Internal bus
LVION1 LVF10
Low-voltage detection register 1 (LVIF1)
22
Data Sheet U13917EJ1V1DS
PD789860, 789861
6.5 Bit Sequential Buffer
The PD789860 and PD789861 have an on-chip bit sequential buffer of 8 bits x 8 bits = 16 bits. The functions of the bit sequential buffer are shown below. * If the value of the bit sequential buffer 10 data register (BSFRL10, BSFRH10) is shifted 1 bit to the lower side, the LSB can be output to the port at the same time. * It is possible to write to BSFRL10 and BSFRH10 using an 8-bit or 16-bit manipulation instruction. * Overwriting is enabled during a shift operation on the higher 8 bits only (the period in which shift clock is low level). Figure 6-9. Bit Sequential Buffer Block Diagram
Internal bus
TM40 match interrupt request signal
BSFRH10
BSFRL10
BSFO/P20 /TMO
BSFE10
Bit sequential buffer output control register 10 (BSFC10) Internal bus
6.6
Key Return Circuit
In STOP mode, this circuit generates a key return interrupt by inputting a P40/KR10 to P43/KR13 falling edge. It can be used in judging the cause of a STOP mode release in software. Caution The key return interrupt is a non-maskable interrupt that is in effect only in STOP mode. In addition, P40/KR10 to P43/KR13 key input cannot be controlled by the mask options. Figure 6-10. Key Return Circuit Block Diagram
P40/KR10 P41/KR11 P42/KR12 P43/KR13 STOP mode Falling edge detector Key return signal
Data Sheet U13917EJ1V1DS
23
PD789860, 789861
7. INTERRUPT FUNCTIONS
7.1 Types of Interrupt Functions
The following two kinds of interrupt functions are available. (1) Non-maskable interrupts A non-maskable interrupt is an interrupt that is accepted unconditionally even in a state in which interrupts are disabled. In addition, it is not subject to interrupt priority control and has a greater priority than all other interrupt requests. A non-maskable interrupt generates a standby release signal. Non-maskable interrupts have one internal interrupt source and one external interrupt source. (2) Maskable interrupts A maskable interrupt is an interrupt that is mask controlled. The order of priority when multiple interrupt requests are generated at the same time is determined as shown in Table 7-1. A maskable interrupt generates a standby release signal. Maskable interrupts have 5 internal interrupt sources. 7.2 Sources and Configuration of Interrupts
There are a total of seven sources of interrupts for non-maskable interrupts and maskable interrupts combined (see Table 7-1). Table 7-1. List of Interrupt Sources
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Notes 1. Priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and 4 is the lowest. 2. Remark (A) and (B) in Basic Configuration Type above correspond to (A) and (B) in Figure 7-1. Non-maskable and maskable interrupts (internal) are available as the watchdog timer interrupt sources (INTWDT), and either one can be selected.
24
Data Sheet U13917EJ1V1DS
PD789860, 789861
Figure 7-1. Basic Configuration of Interrupt Functions (A) External/internal non-maskable interrupt
Internal bus
Interrupt request
Vector table address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
Interrupt request
IF
Vector table address generator
Standby release signal
IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag
Data Sheet U13917EJ1V1DS
25
PD789860, 789861
8. STANDBY FUNCTION
The following two standby modes are available for further reduction of system current consumption. * HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation. * STOP mode: In this mode, oscillation of the system clock is stopped. All operations performed on the system clock are suspended resulting in extremely small power consumption. Figure 8-1. Standby Function
System clock operation STOP instruction Interrupt request HALT instruction
Interrupt request
(
9. RESET FUNCTION
STOP mode System clock oscillation stopped
(
(
HALT mode Clock supply to CPU halted, oscillation maintained
(
The following three reset methods are available. * External reset by RESET pin * Internal reset by watchdog timer program loop time detection * Internal reset by the POC circuit according to comparison of the detection voltage to the power supply voltage
26
Data Sheet U13917EJ1V1DS
PD789860, 789861
10. MASK OPTIONS
The PD789860 and PD789861 have the following mask options. * P40 to P43 mask options On-chip pull-up resistors can be selected. <1> Specify on-chip pull-up resistors in bit units <2> Do not specify on-chip pull-up resistors * POC circuit mask options The POC circuit can be selected. <1> Select POC switching circuit (POC circuit operation control by software is possible) <2> Select POC circuit normally operating <3> Select POC circuit normally halted * Oscillation stabilization wait time (PD789860 only) The oscillation stabilization wait time after the release of STOP mode by RESET or the release of reset by POC can be selected. <1> 2 /fX <2> 2 /fX Caution The oscillation stabilization wait time of the PD789861 is fixed to 2 /fCC.
7 17 15
Data Sheet U13917EJ1V1DS
27
PD789860, 789861
11. INSTRUCTION SET SUMMARY
This section lists the PD789860 and PD789861 instruction set. 11.1 Conventions 11.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). and must be described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols #, !, $, and [ ] are key words
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 11-1. Operand Identifiers Forms and Description Methods
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28
Data Sheet U13917EJ1V1DS
PD789860, 789861
11.1.2 Explanation of operation column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): : : : : jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Non-maskable interrupt processing flag Contents of memory represented by contents of register or address in parentheses Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data Signed 8-bit data (displacement value)
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
addr16: 16-bit immediate data or label
11.1.3 Explanation of flags column (blank): No change 0: 1: x: R: Cleared to 0 Set to 1 Set or cleared according to result Previously stored value is stored
Data Sheet U13917EJ1V1DS
29
PD789860, 789861
11.2 List of Operations
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Notes 1. Excludes r = A 2. Excludes r = A, X 3. rp = BC, DE, HL only Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC).
30
Data Sheet U13917EJ1V1DS
PD789860, 789861
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2SHUDQG
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Note
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E\WH E\WH
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VDGGU &< VDGGU $ &< $ $ &< $ $ &< $ $ &< $ $ &< $ $ &< $ U VDGGU DGGU +/ +/ E\WH
$ VDGGU $ DGGU $ >+/@ $ >+/ $''& $ E\WH E\WH
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VDGGU &< VDGGU $ &< $ $ &< $ $ &< $ $ &< $ $ &< $ U &<
$ VDGGU $ DGGU $ >+/@ $ >+/ 68% $ E\WH E\WH
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&< E\WH
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VDGGU $U
$ VDGGU $ DGGU $ >+/@ $ >+/
Note
rp = BC, DE, HL only
Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC).
Data Sheet U13917EJ1V1DS
31
PD789860, 789861
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x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
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$ VDGGU $ DGGU $ >+/@ $ >+/ 25 $ E\WH E\WH
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VDGGU VDGGU U U
VDGGU VDGGU
Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC).
32
Data Sheet U13917EJ1V1DS
PD789860, 789861
0QHPRQLF
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Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC).
Data Sheet U13917EJ1V1DS
33
PD789860, 789861
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Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC).
34
Data Sheet U13917EJ1V1DS
PD789860, 789861
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
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Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U13917EJ1V1DS
35
PD789860, 789861
System Clock Oscillator Characteristics Ceramic or crystal oscillation (PD789860) (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution When using a ceramic or crystal oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
36
Data Sheet U13917EJ1V1DS
PD789860, 789861
Recommended Oscillator Constant Ceramic Resonator (TA = -40 to +85C)
0DQXIDFWXUHU 3DUW 1XPEHU )UHTXHQF\ Recommended Circuit Constant 0+] (pF) & 0XUDWD 0IJ &R /WG &6%/$0-% &6%&6%)%0-% &6%)&67/60*% &67&&0*% &67&&0*+ &67/60*% &6760* &67&50*5 &67/60*% &6760* &67&50*5 &67/60*% &6760* &67&50*5 &67/60*% &6760* &67&50*5 - - - - - - - - - - & - - - - - - - - - - 2VFLOODWLRQ 9ROWDJH 5DQJH 9DD 0,1 0$; 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 2QFKLS FDSDFLWRU 5HPDUN
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. Remark Part numbers in the parentheses indicate old part numbers.
Data Sheet U13917EJ1V1DS
37
PD789860, 789861
RC oscillation (PD789861) (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. 3. Variations in external resistance and external capacitance are not included. Caution When using an RC oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
38
Data Sheet U13917EJ1V1DS
PD789860, 789861
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 2. Items in parentheses apply to the PD789861.
Data Sheet U13917EJ1V1DS
39
PD789860, 789861
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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Note Port current (including current flowing in on-chip pull-up resistors) is not included. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
40
Data Sheet U13917EJ1V1DS
PD789860, 789861
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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TCY1 vs. VDD (System Clock: Ceramic/Crystal Oscillation)
TCY2 vs. VDD (System Clock: RC Oscillation)
60
60
20 10
Cycle time TCY [s] Cycle time TCY [s]
20 10
Guaranteed operation range 2.0 1.0
Guaranteed operation range 2.0 1.0
0.4
0.4
0.1 1 2 3 4 5 6 Supply voltage VDD (V)
0.1 1 2 3 4 5 6 Supply voltage VDD (V)
Data Sheet U13917EJ1V1DS
41
PD789860, 789861
(2) RC frequency oscillation characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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Note Does not include variations due to external resistance and external capacitance AC Timing Test Points (excluding X1 and CL1 inputs)
0.8VDD 0.2VDD 0.8VDD 0.2VDD
Test points
Clock Timing
1/fCLK tXL tXH VIH3 (MIN.) VIL3 (MAX.)
X1 (CL1) input
Remark fCLK: fX or fCC TMI Timing
1/fTI tTIL tTIH
TMI
Key Return Input Timing
tKRIL
KR10 to KR13
RESET Input Timing
tRSL
RESET
42
Data Sheet U13917EJ1V1DS
PD789860, 789861
Power-On-Clear Circuit Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V) (1) POC (a) DC characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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Note Time from detecting voltage until output reverses and time until stable operation after transition from halted state to operating state (b) AC characteristics (TA = -40 to +85C)
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(2) LVI (a) DC characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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Notes 1. Time from detecting voltage until output reverses and time until stable operation after transition from halted state to operating state 2. Relativity: VLVI1 < VLVI2 < VLVI3 < VLVI4 < VLVI5 < VLVI6 3. VPOC < VLVI0
Data Sheet U13917EJ1V1DS
43
PD789860, 789861
EEPROM Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V)
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44
Data Sheet U13917EJ1V1DS
PD789860, 789861
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
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Data Retention Timing
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
HALT mode STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (interrupt request) tWAIT
Data Sheet U13917EJ1V1DS
45
PD789860, 789861
Oscillation Stabilization Wait Time (TA = -40 to +85C, VDD = 1.8 to 3.6 V) (a) Ceramic/crystal oscillation (PD789860)
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Notes 1. Time required to stabilize oscillation after reset or STOP mode release. 2. 2 /fX or 2 /fX can be selected using the mask option. 3. 2 /fX, 2 /fX, or 2 /fX can be selected using bits 0 to 2 of the oscillation stabilization time selection register (OSTS0 to OSTS2). (b) RC oscillation (PD789861)
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Note Time required to stabilize oscillation after reset or STOP mode release.
46
Data Sheet U13917EJ1V1DS
PD789860, 789861
13. EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES)
FCC vs. VDD (RC Oscillation: PD789861, R = 24 k, C = 30 pF)
(TA = 25C) CL1 CL2 24 kW 30 pF 1.05 Sample A 1.0 Sample B Sample C
1.10
System clock frequency fCC [MHz]
0.95
0.90
1.5
2.0
3.0 Supply voltage VDD [V]
4.0
Data Sheet U13917EJ1V1DS
47
PD789860, 789861
14. PACKAGE DRAWING
20-PIN PLASTIC SSOP (7.62 mm (300))
20 11
detail of lead end F G T
P E 1 A H I S 10
L U
J
N C D
NOTE
S K
M
M
B
ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.650.15 0.475 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 +5 3 -3 0.25 0.60.15 S20MC-65-5A4-2
Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
48
Data Sheet U13917EJ1V1DS
PD789860, 789861
15. RECOMMENDED SOLDERING CONDITIONS
The PD789860 and 789861 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions xxx-5A4: 20-pin plastic SSOP (7.62 mm (300)) PD789860MC-xxx xxx xxx-5A4: 20-pin plastic SSOP (7.62 mm (300)) PD789861MC-xxx xxx
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 --
Infrared reflow VPS Wave soldering Partial heating
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: three times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: three times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max. Time: 3 seconds max. (per pin row)
Caution Do not use different soldering method together (except for partial heating).
Data Sheet U13917EJ1V1DS
49
PD789860, 789861
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD789860 and PD789861. Language Processing Software
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Flash Memory Writing Tools
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Debugging Tools
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Notes 1,2
50
Data Sheet U13917EJ1V1DS
PD789860, 789861
Real-Time OS
MX78K0SNotes 1,2 OS for 78K/0S Series
Notes
1. 2. 3. 4.
PC-9800 series (Japanese Windows) based IBM PC/AT or compatibles (Japanese/English Windows) based HP9000 series 700
TM
(HP-UX ) based, SPARCstation
TM
TM
(SunOS , Solaris ) based
TM
TM
This is a product of Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191).
Remark
Use this in combination with RA78K0S, CC78K0S, SM78K0S, and DF789861.
Data Sheet U13917EJ1V1DS
51
PD789860, 789861
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. versions are not marked as such. Documents Related to Devices
Document Name Document No. This manual U14385E U14826E U11047E
However, preliminary
PD789860, 789861 Data Sheet PD78E9860, 78E9861 Preliminary Product Information PD789860, 789861 Subseries User's Manual
78K/0S Series Instructions User's Manual
Documents Related to Development Tools (Software) (User's Manuals)
Document Name RA78K0S Assembler Package Operation Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows Based SM78K Series System Simulator Ver. 2.10 or Later ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Based Operation Document No. U11622E U11599E U11623E U11816E U11817E U14611E
External Part User Open Interface Specification Operation
U15006E U14910E
Document Related to Development Tools (Hardware) (User's Manuals)
Document Name IE-78K0S-NS In-Circuit Emulator IE-78K0S-NS-A In-Circuit Emulator IE-789860-NS-EM1 Emulation Board Document No. U13549E U15207E To be prepared
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
52
Data Sheet U13917EJ1V1DS
PD789860, 789861
Other Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products & Packages Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U13917EJ1V1DS
53
PD789860, 789861
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM and FIP are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc.
54
Data Sheet U13917EJ1V1DS
PD789860, 789861
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U13917EJ1V1DS
55
PD789860, 789861
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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