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DATA SHEET
MOS INTEGRATED CIRCUITS
PD78F9116A
8-BIT SINGLE-CHIP MICROCONTROLLERS
The PD78F9116A is a PD789114A Subseries product of the 78K/0S Series. The PD78F9116A replaces the internal masked ROM of the PD789111A,789112A and 789114A with flash memory, which enables the writing/erasing of a program while the device is mounted on the board. Because the device can be programmed by the user, it is ideally suited to the evaluation stages of system development, the manufacture of small batches of multiple products, and the rapid development of new products. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD789104A, 789114A, 789124A, 789134A Subseries User's Manual: To be prepared 78K/0S Series User's Manual Instruction: U11047E
FEATURES
* Pin-compatible with masked ROM version (excluding VPP pin) * Flash memory: 16K bytes * Internal High-Speed RAM: 256 bytes * On-chip multiplier: 8 bits x 8 bits = 16 bits * Minimum instruction execution time can be changed from high-speed (0.4 s) to low-speed (1.6 s) (@ 5.0-MHz operation with system clock) * I/O ports: 20 * Serial interface: 1 channel: Switchable between 3-wire serial I/O and UART modes * 10-bit resolution A/D converter: 4 channels * Timers: 3 channels * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel * Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Cleaners, washing machines, refrigerators and battery-charger
ORDERING INFORMATION
Part number Package 30-pin plastic SSOP (7.62mm (300))
PD78F9116AMC-5A4
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14667EJ1V1DS00 (1st edition) Date Published March 2000 NS CP(K) Printed in Japan
The mark
shows major revised points.
(c)
2000
PD78F9116A
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products under mass production Products under development Y subseries supports SMB.
Small, general-purpose 44 pins 42/44 pins 28 pins
PD789046 PD789026 PD789014
PD789026 with subsystem clock added PD789014 with timer reinforced and ROM and RAM expanded
UART. Low-voltage (1.8-V) operation
Small, general-purpose + A/D 44 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
PD789177Y PD789167Y
PD789167 with improved A/D PD789104A with improved timer PD789146 with improved A/D PD789104A with EEPROM added PD789124A with improved A/D RC oscillation model of PD789104A PD789104A with improved A/D PD789026 with A/D and multiplier added
For inverter control 44 pins 78K/0S series 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins
PD789842
For driving LCD
Internal inverter control circuit and UART
PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306
PD789407A with improved A/D PD789456 with improved I/O PD789446 with improved A/D PD789426 with improved display output PD789426 with improved A/D PD789306 with A/D added RC oscillation model of PD789306
Basic subseries for driving LCD
For driving Dot LCD 144 pins 88 pins
PD789835 PD789830
For ASSP
Segment/common output: 96 pins Segment: 40 pins, common: 16 pins
52 pins 52 pins 44 pins 44 pins 20 pins 20 pins
PD789467 PD789327 PD789800 PD789840 PD789861 PD789860
PD789327 with A/D added For remote controller. Internal LCD controller/driver For PC keyboard. Internal USB function For key pad. Internal POC RC oscillation model of PD789860 For keyless entry. Internal POC and key return circuit
2
Data Sheet U14667EJ1V1DS00
PD78F9116A
The major differences between subseries are shown below.
Function Subseries Name Small, PD789046 16 K generalPD789026 4 K-16 K purpose PD789014 2 K-4 K Small, PD789177 16 K-24 K generalPD789167 purpose PD789156 8 K-16 K + A/D Timer 8-bit 1 ch 16-bit 1 ch Watch WDT 1 ch - 2 ch 3 ch - 1 ch 1 ch 1 ch - 8 ch 1 ch - - 4 ch 8 ch - 4 ch - 4 ch 4 ch - 4 ch 3 ch Note 1 ch 1 ch 8 ch - 4 ch - - 1 ch (UART: 1 ch) 30 pins 4.0 V - 20 pins Internal EEPROM RC oscillation version - 22 pins 1 ch (UART: 1 ch) 31 pins 1.8 V - 1 ch VDD MIN Value 1.8 V
ROM Capacity
8-bit A/D -
10-bit A/D -
Serial Interface
I/O
Remark -
1 ch (UART:1 ch)
34 pins
PD789146 PD789134A 2 K-8 K PD789124A PD789114A PD789104A
For inverter control
PD789842 8 K-16 K
For LCD PD789417A 12 K-24 K driving PD789407A
3 ch
1 ch
1 ch
1 ch 7 ch
7 ch - 6 ch - 6 ch -
1 ch (UART: 1 ch) 43 pins
1.8 V
-
PD789456 12 K-16 K PD789446 PD789436 PD789426 PD789316 8 K to 16K PD789306
For Dot LCD driving ASSP
2 ch
- 6 ch - 6 ch -
30 pins
40 pins
2 ch (UART: 1 ch) 23 pins
RC oscillation version -
PD789835 24 K-60 K PD789830 24 K PD789467 4 K-24 K PD789327 PD789800 8 K PD789840 PD789861 4 K
6 ch 1 ch 2 ch
- 1 ch -
1 ch
1 ch
2 ch -
-
1 ch
27 pins
1.8 V 2.7 V 1.8 V
-
1 ch (UART: 1 ch) 30 pins - 1 ch 2 ch (USB: 1 ch) 1 ch - - 18 pins 21 pins 31 pins 29 pins 14 pins
1 ch
1 ch
1 ch -
Internal LCD -
2 ch
1 ch
-
1 ch
- 4 ch
4.0 V 2.8 V 1.8 V
-
-
RC oscillation version, Internal EEPROM Internal EEPROM
PD789860
Note 10-bit timer: 1 channel
Data Sheet U14667EJ1V1DS00
3
PD78F9116A
OVERVIEW OF FUNCTIONS
Item Internal memory Flash memory High-speed RAM Minimum instruction execution time General-purpose registers Instruction set 16 Kbytes 256 bytes 0.4/1.6 s (@ 5.0-MHz operation with system clock) 8 bits x 8 registers * 16-bit operations * Bit manipulations (set, reset, and test) 8 bits x 8 bits = 16 bits Total: * CMOS input: * CMOS I/O: * N-ch open-drain (12-V withstand voltage): A/D converters Serial interface Timer 10-bit resolution x 4 channels Switchable between 3-wire serial I/O and UART modes * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel 1 output (16-bit/8-bit timer alternate function) Maskable Non-maskable Internal: 6, External: 3 Internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C 30-pin plastic SSOP (7.62 mm (300)) 20 4 12 4 function
Multiplier I/O ports
Timer output Vectored interrupt sources Power supply voltage Operating ambient temperature Package
4
Data Sheet U14667EJ1V1DS00
PD78F9116A
CONTENTS
1. 2. 3. 4.
PIN CONFIGURATION (TOP VIEW).............................................................................................. BLOCK DIAGRAM ........................................................................................................................... DIFFERENCES BETWEEN PD78F9116A AND MASKED ROM VERSION .................................. PIN FUNCTIONS ..............................................................................................................................
4.1 4.2 4.3 Port Pins.................................................................................................................................................. Non-Port Pins.......................................................................................................................................... Pin I/O Circuits and Recommended Connection of Unused Pins......................................................
6 7 8 9
9 10 11
5. 6.
MEMORY SPACE............................................................................................................................. FLASH MEMORY PROGRAMMING .................................................................................................
6.1 6.2 6.3 6.4 Selecting Communication Mode ........................................................................................................... Function of Flash Memory Programming ............................................................................................ Flashpro III Connection.......................................................................................................................... Example of Settings for Flashpro III (PG-FP3) .....................................................................................
13 14
14 15 15 17
7.
INSTRUCTION SET OVERVIEW ....................................................................................................
7.1 7.2 Conventions............................................................................................................................................ Operations ..............................................................................................................................................
18
18 20
8. 9.
ELECTRICAL SPECIFICATIONS .................................................................................................... PACKAGE DRAWING......................................................................................................................
25 37 38 39 41
10. RECOMMENDED SOLDERING CONDITIONS .............................................................................. APPENDIX A DEVELOPMENT TOOLS .............................................................................................. APPENDIX B RELATED DOCUMENTS..............................................................................................
Data Sheet U14667EJ1V1DS00
5
PD78F9116A
1. PIN CONFIGURATION (TOP VIEW)
* 30-pin plastic SSOP (7.62 mm (300))
PD78F9116AMC-5A4
P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 AVDD P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 AVSS IC0 P50 P51 P52 P53 P00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22/SI20/RXD20 P21/SO20/TXD20 P20/SCK20/ASCK20 P11 P10 VDD VSS X1 X2 IC0 VPP RESET P03 P02 P01
Cautions 1. Connect the IC0 (Internally Connected) pin directly to VSS. 2. Connect the VPP pin directry to VSS in normal operation mode. 3. Connect the AVDD pin to VDD. 4. Connect the AVSS pin to VSS. ANI0 to ANI3: ASCK20: AVDD: AVSS: CPT20: IC0: INTP0 to INTP2: P00 to P03: P10, P11: P20 to P25: P50 to P53: P60 to P63: Analog Input Asynchronous Serial Input Analog Power Supply Analog Ground Capture Trigger Input Internally Connected Interrupt from Peripherals Port0 Port1 Port2 Port5 Port6 RESET: RXD20: SCK20: SI20: SO20: SS20: TI80: TO20, TO80: TXD20: VDD: VPP: VSS: X1, X2: Reset Receive Data Serial Clock Input/Output Serial Data Input Serial Data Output Chip Select Input Timer Input Timer Output Transmit Data Power Supply Programing Power Supply Ground Crystal 1, 2
6
Data Sheet U14667EJ1V1DS00
PD78F9116A
2. BLOCK DIAGRAM
TI80/INTP2/P25 TO80/TO20 /INTP1/P24 8-BIT TIMER/ EVENT COUNTER 80 PORT 0 P00 to P03
TO20/TO80 /INTP1/P24 CPT20/INTP0 /SS20/P23
16-BIT TIMER 20
PORT 1
P10, P11
PORT 2 WATCHDOG TIMER 78K/0S CPU CORE SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 SS20/INTP0 /CPT20/P23 RAM ANI0/P60 to ANI3/P63 AVDD AVSS A/D CONVERTER SYSTEM CONTROL SERIAL INTERFACE 20 PORT 6 FLASH MEMORY PORT 5
P20 to P25
P50 to P53
P60 to P63
RESET X1 X2
INTERRUPT CONTROL
VDD VSS VPP IC0
INTP0/CPT20 /P23/SS20 INTP1/TO80 /TO20/P24 INTP2/TI80/P25
Remark
The internal ROM capacity varies depending on the product.
Data Sheet U14667EJ1V1DS00
7
PD78F9116A
3. DIFFERENCES BETWEEN PD78F9116A AND MASKED ROM VERSION
The PD78F9116A is a product that substitutes flash memory for the internal ROM of the masked ROM version. The differences between the PD78F9116A and the masked ROM versions are shown in Table 3-1. Table 3-1. Types of Pin Input/Output Circuits
Flash memory version Item Internal memory ROM High-speed RAM Masked ROM version
PD78F9116A
16Kbytes (Flash memory) 256 bytes 12 ( software control only ) Provided See the relevant data sheet
PD789111A
2 Kbytes
PD789112A
4 Kbytes
PD789114A
8 Kbytes
Pull-up resistor VPP pin Electric characteristics
16 ( software control : 12, mask option specification : 4 ) Not provided
Caution
There are differences in the amount of noise tolerance and noise radiation between flash memory versions and masked ROM versions. When considering changing from a flash memory version to a masked ROM version during process from experimental manufacturing to mass production, make sure to sufficiently evaluate the masked ROM versions using commercial samples (CS) (not engineering samples (ES)).
8
Data Sheet U14667EJ1V1DS00
PD78F9116A
4. PIN FUNCTIONS 4.1 Port Pins
I/O I/O Port 0 4-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of software. P10, P11 I/O Port 1 2-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of software. P20 P21 P22 P23 I/O Port 2 6-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input SCK20/ASCK20 SO20/TxD20 SI20/RxD20 INTP0/CPT20 /SS20 INTP1/TO80/TO20 INTP2/TI80 I/O Port 5 4-bit N-ch open-drain input/output port Input/output can be specified in 1-bit units An on-chip pull-up resistor can be specified by the mask option. P60 to P63 Input Port 6 4-bit input-only port Input ANI0 to ANI3 Input - Input - Function After Reset Input Alternate Function -
Pin Name P00 to P03
P24 P25 P50 to P53
Data Sheet U14667EJ1V1DS00
9
PD78F9116A
4.2 Non-Port Pins
I/O Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Serial interface serial data input Serial interface serial data output Serial interface serial clock input/output Serial clock input for asynchronous serial interface Chip select input for serial interface Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface External count clock input to 8-bit timer/event counter 80 8-bit timer/event counter 80 output 16-bit timer 20 output Capture edge input A/D converter analog input A/D converter analog power supply A/D converter ground potential Connecting crystal resonator for main system clock oscillation After Reset Input Alternate Function P23/CPT20/SS20 P24/TO80/TO20 P25/TI80 Input Input Input Input Input Input Input Input Input Input Input Input - - - - System reset input Positive power supply Ground potential Sets flash memory programming mode. Applies high voltage when a program is written or verified. Connect directly to VSS in normal operation mode. Internally connected. Connect directly to VSS. Input - - - P22/RxD20 P21/TxD20 P20/ASCK20 P20/SCK20 P23/CPT20/INTP0 P22/SI20 P21/SO20 P25/INTP2 P24/INTP1/TO20 P24/INTP1/TO80 P23/INTP0/SS20 P60 to P63 - - - - - - - -
Pin Name INTP0 INTP1 INTP2 SI20 SO20 SCK20 ASCK20 SS20 RxD20 TxD20 TI80 TO80 TO20 CPT20 ANI0 to ANI3 AVDD AVSS X1 X2 RESET VDD VSS VPP
Input Output I/O Input Input Input Output Input Output Output Input Input Input Input -
IC0
-
-
-
10
Data Sheet U14667EJ1V1DS00
PD78F9116A
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 4-1. For the input/output circuit configuration of each type, refer to Figure 4-1. Table 4-1. Types of Pin Input/Output Circuits
Pin Name Input/Output Circuit Type 5-A I/O Recommended Connection of Unused Pins
P00 to P03 P10, P11 P20/SCK20/ASCK20 P21/SO20/TXD20 P22/SI20/RXD20 P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 P50 to P53
I/O
Input: Independently connect to VDD or VSS via a resistor. Output: Leave open
8-A
Input: Independently connect to VSS via a resistor. Output: Leave open
13-V
Input: Independently connect to VDD via a resistor. Output: Leave open Input - Connect directly to VDD or VSS. Connect to VDD. Connect to VSS.
P60/ANI0 to P63/ANI3 AVDD AVSS RESET VPP IC0
9-C -
2 -
Input - Connect directly to VSS.
-
Data Sheet U14667EJ1V1DS00
11
PD78F9116A
Figure 4-1. Pin Input/Output Circuits
Type 2
Type 9-C
IN IN
P-ch N-ch AVSS
Comparator
+ -
VREF (Threshold voltage) Schmitt-triggered input with hysteresis characteristics
Input enable
Type 5-A
VDD
Type 13-V
Pull-up enable VDD Data P-ch
P-ch IN/OUT Output data Output disable IN/OUT N-ch
VSS Input enable Middle-voltage input buffer
Output disable
N-ch VSS
Input enable Type 8-A VDD
Pull-up enable VDD Data P-ch
P-ch
IN/OUT Output disable N-ch VSS
12
Data Sheet U14667EJ1V1DS00
PD78F9116A
5. MEMORY SPACE
Figure 5-1 shows the memory map of the PD78F9116A. Figure 5-1. Memory Map
FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH
Reserved Data memory space 3FFFH 4000H 3FFFH Program area
Program memory space
Flash memory 16384 x 8 bits
0080H 007FH CALLT table area 0040H 003FH 0016H 0015H Program area Vector table area 0000H
0000H
Data Sheet U14667EJ1V1DS00
13
PD78F9116A
6. FLASH MEMORY PROGRAMMING
The on-chip program memory in the PD78F9116A is a flash memory. The flash memory can be written with the PD78F9116A mounted on the target system (on-board). Connect the dedicated flash programmer (Flashpro III (model number: FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory. Remark FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd..
6.1
Selecting Communication Mode
The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 6-1. To select a communication mode, the format shown in Figure 6-1 is used. Each communication mode is selected by the number of VPP pulses shown in Table 6-1. Table 6-1. Communication Mode List
Communication mode 3-wired serial I/O mode SCK20/ASCK20/P20 SO20/TxD20/P21 SI20/RxD20/P22 TxD20/SO20/P21 RxD/SI20/P22
Note
Pins used 0
Number of VPP pulses
UART
8
Pseudo 3-wire mode
P00 (Serial clock input) P01 (Serial data output) P02 (Serial data input)
12
Note Serial transfer is performed by controlling a port by software. Caution Be sure to select a communication mode depending on the VPP pulse number shown in Table 6-1. Figure 6-1. Communication Mode Selection Format
10 V VPP VDD VSS 1 2 n
VDD RESET VSS
14
Data Sheet U14667EJ1V1DS00
PD78F9116A
6.2 Function of Flash Memory Programming
By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 6-2 shows the major functions of flash memory programming. Table 6-2. Functions of Flash Memory Programming
Function Batch erase Batch blank check Data write Batch verify Erases all contents of memory Checks erased state of entire memory Write to flash memory based on write start address and number of data written (number of bytes) Compares all contents of memory with input data Description
6.3
Flashpro III Connection
How the Flashpro III is connected to the PD78F9116A differs depending on the communication mode (3-wired serial I/O or pseudo 3-wire mode). Figures 6-2 to 6-4 show the connection in the respective mode. Figure 6-2. Flashpro III Connection in 3-wired Serial I/O Mode
Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND VPP VDD, AVDD RESET X1 SCK20 SI20 SO20 VSS, AVSS
PD78F9116A
Note n = 1, 2
Data Sheet U14667EJ1V1DS00
15
PD78F9116A
Figure 6-3. Flashpro III Connection in UART Mode
Flashpro III VPPnNote VDD RESET CLK SO SI GND VPP
PD78F9116A
VDD, AVDD RESET X1 RxD20 TxD20 VSS, AVSS
Note n= 1, 2 Figure 6-4. Flashpro III Connection in Pseudo 3-Wire Mode (When Port 0 is Used)
Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND VPP VDD, AVDD RESET X1 P00 (Serial clock) P02 (Serial input) P01 (Serial output) VSS, AVSS
PD78F9116A
Note n= 1, 2
16
Data Sheet U14667EJ1V1DS00
PD78F9116A
6.4 Example of Settings for Flashpro III (PG-FP3)
Set as follows when writing to flash memory using the Flashpro III (PG-FP3). <1> Download the parameter file. <2> Select the serial mode and the serial clock using the type command. <3> The following is a setting example using the PG-FP3. Table 6-3. Example Using PG-FP3
Communication mode 3-wired serial I/O mode Setting example using PG-FP3 COMM PORT CPU CLK SIO ch-0 On target board In Flashpro On target board SIO CLK In Flashpro SIO CLK UART COMM PORT CPU CLK 4.1943 MHz 1.0 MHz 4.0 MHz 1.0 MHz UART-ch0 On target board In Flashpro On target board UART BPS Pseudo 3-wire mode COMM PORT CPU CLK 4.1943 MHz 9600 bps Port B On target board In Flashpro On target board SIO CLK In Flashpro SIO CLK 4.1943 MHz 1 kHz 4.0 MHz 1 kHz
Note2
Number of VPP pulses 0
Note1
8
12
Notes
1. The number of VPP pulses supplied from the Flashpro III during serial communication initialization. The pins to be used in communication are determined by this number of pulses. 2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps.
Remark
COMM PORT: Selection of serial port SIO CLK CPU CLK : Selection of serial clock frequency : Selection of CPU clock source to be input
Data Sheet U14667EJ1V1DS00
17
PD78F9116A
7. INSTRUCTION SET OVERVIEW
The instruction set for the PD78F9116A is listed later.
7.1
Conventions
7.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords and must be described as they are. Each symbol has the following meaning. * * #: Immediate data specification !: Absolute address specification * * $: Relative address specification
[ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #,!, $, or [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 7-1. Operand Identifiers and Description Methods
Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7), AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol FE20H to FF1FH immediate data or label FE20H to FF1FH immediate data or label (even address only) 0000H to FFFFH immediate data or label (Only even addresses for 16-bit data transfer instructions) 0040H to 007FH immediate data or label (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
18
Data Sheet U14667EJ1V1DS00
PD78F9116A
7.1.2 Descriptions of the operation field A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): XH, XL: : : : : addr16: jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive OR Inverted data 16-bit immediate data or label Signed 8-bit data (displacement value)
7.1.3 Description of the flag operation field (Blank): 0: 1: x: R: Not affected Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
Data Sheet U14667EJ1V1DS00
19
PD78F9116A
7.2 Operations
Operand Byte Clock Operation Flag Z AC CY MOV r, #byte saddr , #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A XCH A, X A, r A, saddr A, sfr A, [DE] A, [HL] A, [HL + byte] MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX XCHW AX, rp
Note 3 Note 2 Note 1
Mnemonic
3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 3 2 2 1 1 1
6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 6 6 8 4 4 8
r byte (addr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A X A r A (saddr) A (sfr) A (DE) A (HL) A (HL + byte) rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp xxx xxx
Note 1
Note 3
Note 3
Notes 1. Except r = A 2. Except r = A or X 3. Only when rp = BC, DE, HL Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
20
Data Sheet U14667EJ1V1DS00
PD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
ADD
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2
4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6
A, CY A + byte (saddr), CY (saddr) + byte A ,CY A + r A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte)
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x
ADDC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
SUB
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
SUBC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
AND
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
Data Sheet U14667EJ1V1DS00
21
PD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
OR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1
4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2
A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL + byte) AX, CY AX + word AX, CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 (CY, A0 A7, Am + 1 Am) x 1 (CY A0, A7 CY, Am - 1 Am) x 1 (CY A7, A0 CY, Am + 1 Am) x 1
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
XOR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
CMP
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
ADDW SUBW CMPW INC
AX, #word AX, #word AX, #word r saddr
DEC
r saddr
INCW DECW ROR ROL RORC ROLC
rp rp A, 1 A, 1 A, 1 A, 1
x x x x
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
22
Data Sheet U14667EJ1V1DS00
PD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
SET1
saddr. bit sfr. bit A. bit PSW. bit [HL]. bit
3 3 2 3 2 3 3 2 3 2 1 1 1 3
6 6 4 6 10 6 6 4 6 10 2 2 2 6
(saddr. bit) 1 sfr. bit 1 A. bit 1 PSW. bit 1 (HL) . bit 1 (saddr. bit) 0 sfr. bit 0 A. bit 0 PSW. bit 0 (HL) . bit 0 CY 1 CY 0 CY CY (SP - 1) (PC + 3)H,(SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H,(SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X RRR RRR 1 0 x x x x x x x
CLR1
saddr. bit sfr. bit A. bit PSW. bit [HL]. bit
SET1 CLR1 NOT1 CALL
CY CY CY !addr16
CALLT
[addr5]
1
8
RET
1
6
RETI
1
8
PUSH
PSW rp
1 1
2 4
POP
PSW rp
1 1
4 6
MOVW
SP, AX AX, SP
2 2 3 2 1
8 6 6 6 6
BR
!addr16 $addr16 AX
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
Data Sheet U14667EJ1V1DS00
23
PD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
BC BNC BZ BNZ BT
$addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16
2 2 2 2 4
6 6 6 6 10
PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr. bit) = 1 PC PC + 4 + jdisp8 if sfr. bit = 1 PC PC + 3 + jdisp8 if A. bit = 1 PC PC + 4 + jdisp8 if PSW. bit = 1 PC PC + 4 + jdisp8 if (saddr. bit) = 0 PC PC + 4 + jdisp8 if sfr. bit = 0 PC PC + 3 + jdisp8 if A. bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if(saddr) 0 No Operation IE 1(Enable Interrupt) IE 0(Disable Interrupt) Set HALT Mode Set STOP Mode
sfr. bit, $addr16 A. bit , $addr16 PSW. bit, $addr16 BF saddr. bit, $addr16
4 3 4 4
10 8 10 10
sfr. bit, $addr16 A. bit, $addr16 PSW. bit, $addr16 DBNZ B, $addr16
4 3 4 2
10 8 10 6
C, $addr16
2
6
saddr, $addr16
3
8
NOP EI DI HALT STOP
1 3 3 1 1
2 6 6 2 2
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
24
Data Sheet U14667EJ1V1DS00
PD78F9116A
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD, AVDD VPP Input voltage VI1 VI2 Output voltage Output current, high VO IOH Per pin Total for all pins Output current, low IOL Per pin Total for all pins Operating ambient temperature TA In normal operation mode During flash memory programming Storage temperature Tstg Pins other than P50 to P53 P50 to P53 With N-ch open drain VDD = AVDD Conditions Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to +13 -0.3 to VDD + 0.3 -10 -30 30 160 -40 to +85 10 to 40 -40 to +125 Unit V V V V V mA mA mA mA C C C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14667EJ1V1DS00
25
PD78F9116A
System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
VPP X1 X2
Parameter Oscillation frequency (fX)
Note 1
Conditions VDD = oscillation voltage range After VDD reaches oscillation voltage range MIN.
Note 1
MIN. 1.0
TYP.
MAX. 5.0
Unit MHz
C1
C2
Oscillation stabilization Note 2 time
4
ms
Crystal resonator
VPP X1
X2
Oscillation frequency (fX) Oscillation stabilization Note 2 time
1.0 VDD = 4.5 to 5.5 V
5.0 10 30
MHz ms
C1
C2
External clock
X1
X2
X1 input frequency (fX)
Note 1
1.0 85
5.0 500
MHz ns
X1 input high-/low-level width (tXH, tXL)
X1
X2
X1 input frequency (fX)
Note 1
VDD = 2.7 to 5.5 V
1.0
5.0
MHz
OPEN
X1 input high-/low-level width (tXH, tXL)
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use the resonator that stabilizes oscillation during the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
26
Data Sheet U14667EJ1V1DS00
PD78F9116A
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Output current, high Symbol IOH Per pin Total for all pins Output current, low IOL Per pin Total for all pins Input voltage, high VIH1 Pins other than described below P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V 0.7 VDD 0.9 VDD VDD = 2.7 to 5.5 V 0.7 VDD Conditions MIN. TYP. MAX. -1 -15 10 80 VDD VDD 12 12 Unit mA mA mA mA V V V V
VIH2
VDD = 1.8 to 5.5 V, 0.9 VDD TA = 25 to 85 C VIH3 RESET, P20 to P25 VDD = 2.7 to 5.5 V 0.8 VDD 0.9 VDD VIH4 X1, X2 VDD = 4.5 to 5.5 V VDD-0.5 VDD-0.1 Input voltage, low VIL1 Pins other than described below P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V 0 0 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V, TA = 25 to 85 C VIL3 RESET, P20 to P25 VDD = 2.7 to 5.5 V 0 0 VIL4 X1, X2 VDD = 4.5 to 5.5 V 0 0 Output voltage, high VOH1 VOH2 Output voltage, low VOL1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD = 1.8 to 5.5 V, IOH = -100 A Pins other than P50 to P53 P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA VDD-1.0 VDD-0.5 0 0
VDD VDD VDD VDD 0.3 VDD 0.1 VDD 0.3 VDD 0.1 VDD
V V V V V V V V
VIL2
0.2 VDD 0.1 VDD 0.4 0.1
V V V V V V
1.0
V
VDD = 1.8 to 5.5 V, IOL = 400 A VDD = 4.5 to 5.5 V, IOL = 10 mA VDD = 1.8 to 5.5 V, IOL = 1.6 mA
0.5 1.0 0.4
V V V
VOL2
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14667EJ1V1DS00
27
PD78F9116A
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Input leakage current, high Symbol ILIH1 ILIH2 ILIH3 Input leakage current, low ILIL1 ILIL2 ILIL3 Conditions Pins other than X1, X2, or P50 to P53 X1, X2 P50 to P53 (N-ch open drain) Pins other than X1, X2, or P50 to P53 X1, X2 P50 to P53 (N-ch open drain) VOUT = VDD VIN = 12 V VIN = 0 V VIN = VDD MIN. TYP. MAX. 3 20 20 -3 Unit
A A A A A A A A
-20 -3
Note 1
Output leakage current, high Output leakage current, low Software pull-up resistor Power supply current
ILOH
3
ILOL
VOUT = 0 V
-3
R1
Note 2
VIN = 0 V, for pins other than P50 to P53
Note 4
50
100
200
k
IDD1
5.0-MHz crystal oscillation operating mode (C1 = C2 = 22pF) 5.0-MHz crystal oscillation HALT mode (C1 = C2 = 22pF) STOP mode
VDD = 5.0 V10% VDD = 3.0 V10% VDD = 2.0 V10%
5.0 1.9 1.5 2.5 1.0 0.75 0.1 0.05 0.05 6.2 3.1 2.5
15.0 4.9 3.0 5.0 2.0 1.5 30 10 10 17.3 7.2 5.0
mA mA mA mA mA mA
Note 5
Note 5
IDD2
Note 2
VDD = 5.0 V10% VDD = 3.0 V10% VDD = 2.0 V10%
Note 4
Note 5
Note 5
IDD3
Note 2
VDD = 5.0 V10% VDD = 3.0 V10% VDD = 2.0 V10%
A A A
mA mA mA
IDD4
Note 3
5.0-MHz crystal oscillation A/D operating mode (C1 = C2 = 22pF)
VDD = 5.0 V10% VDD = 3.0 V10% VDD = 2.0 V10%
Note 4
Note 5
Note 5
Notes 1. When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not included. 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H.) 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
28
Data Sheet U14667EJ1V1DS00
PD78F9116A
FLASH MEMORY WRITE/DELETE CHARACTERISTICS (TA = 10C to 40C, VDD = 1.8 to 5.5 V)
Parameter Write current Note (VDD pin) Write current Note (VPP pin) Delete current Note (VDD pin) Delete current Note (VPP pin) Unit delete time Total delete time Write count VPP supply voltage VPP0 VPP1 Symbol IDDW IPPW IDDE IPPE ter tera Delete/write are regarded as 1 cycle In normal operation During flash memory programming 0 9.7 10.0 Conditions When VPP supply voltage = VPP1 ( 5.0-MHz crystal oscillation operating mode ) When VPP supply voltage = VPP1 When VPP supply voltage = VPP1 ( 5.0-MHz crystal oscillation operating mode ) When VPP supply voltage = VPP1 0.5 1 MIN. TYP. MAX. 18 22.5 18 115 1 20 20 0.2VDD 10.3 Unit mA mA mA mA s s Times V V
Note The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD current are not included.
Data Sheet U14667EJ1V1DS00
29
PD78F9116A
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) TI80 input high-/lowlevel width TI80 input frequency Symbol TCY VDD = 2.7 to 5.5 V Conditions MIN. 0.4 1.6 tTIH, tTIL fTI VDD = 2.7 to 5.5 V 0.1 1.8 VDD = 2.7 to 5.5 V 0 0 Interrupt input high/low-level width RESET low-level width CPT20 input high/low-level width tINTH, tINTL tRSL INTP0 to INTP2 10 4 275 TYP. MAX. 8 8 Unit
s s s s
MHz kHz
s s s
10
tCPH, tCPL
10
TCY vs VDD
60
10
Cycle time TCY [ s]
2.0 1.0 0.5 0.4
Guaranteed operation range
0.1 1 2 3 4 5 6 Supply voltage VDD [V]
30
Data Sheet U14667EJ1V1DS00
PD78F9116A
(2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...Internal clock output)
Parameter SCK20 cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK20 high-/lowlevel width SI20 setup time (to SCK20) SI20 hold time (from SCK20) SO20 output delay time from SCK20 tKH1, tKL1 tSIK1 VDD = 2.7 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 150 VDD = 2.7 to 5.5 V 150 500 tKSI1 VDD = 2.7 to 5.5 V 400 600 tKSO1 R = 1 k , Note C = 100 pF VDD = 2.7 to 5.5 V 0 0 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...External clock input)
Parameter SCK20 cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK20 high-/lowlevel width SI20 setup time (to SCK20) SI20 hold time (from SCK20) SO20 output delay time from SCK20 SO20 setup time (for SS20 when SS20 is used) SO20 disable time (for SS20 when SS20 is used) tKH2, tKL2 tSIK2 VDD = 2.7 to 5.5 V 400 1600 VDD = 2.7 to 5.5 V 100 150 tKSI2 VDD = 2.7 to 5.5 V 400 600 tKSO2 R = 1 k, Note C = 100 pF VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 0 0 300 1000 120 400 tKDS2 VDD = 2.7 to 5.5 V 240 800 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKAS2
Note R and C are the load resistance and load capacitance of the SO output line. (iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions VDD = 2.7 to 5.5 V MIN. TYP. MAX. 78125 19531 Unit bps bps
Data Sheet U14667EJ1V1DS00
31
PD78F9116A
(iv) UART mode (external clock input)
Parameter ASCK20 cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 ASCK20 high-/lowlevel width Transfer rate tKH3, tKL3 VDD = 2.7 to 5.5 V 400 1600 VDD = 2.7 to 5.5 V 39063 9766 ASCK20 rise/fall time tR, tF 1 TYP. MAX. Unit ns ns ns ns bps bps
s
32
Data Sheet U14667EJ1V1DS00
PD78F9116A
AC Timing Test Points (excluding X1 input)
0.8VDD 0.2VDD 0.8VDD 0.2VDD
Test points
Clock Timing
1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
TI Timing
1/fTI tTIL tTIH
TI80
Interrupt Input Timing
tINTL tINTH
INTP0 to INTP2
RESET Input Timing
tRSL
RESET
Data Sheet U14667EJ1V1DS00
33
PD78F9116A
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCK20
tSIKm
tKSIm
SI20
Input data
tKSOm
SO20
Output data
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20 tKAS2 tKDS2
SO20
Output data
UART mode (external clock input):
tKCY3 tKL3 tR ASCK20 tKH3 tF
34
Data Sheet U14667EJ1V1DS00
PD78F9116A
10-Bit A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error
Note1,2
Symbol
Conditions
MIN. 10
TYP. 10 0.2 0.4 0.8
MAX. 10 0.4 0.6 1.2 100 100 0.4 0.6 1.2 0.4 0.6 1.2 2.5 4.5 8.5 1.5 2.0 3.5
Unit bit %FSR %FSR %FSR
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Conversion time
tCONV
2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V
14 28
s s
%FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB LSB V
Zero-scale error
Note1,2
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Full-scale error
Note1,2
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Integral linearity Note1 error
ILE
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Differential linearity Note1 error
DLE
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Analog input voltage
VIAN
0
AVDD
Notes 1. Excludes quantization error (0.05%FSR). 2. It is indicated as a ratio to the full-scale value (%FSR).
Data Sheet U14667EJ1V1DS00
35
PD78F9116A
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Release signal set time Oscillation stabilization wait Note 1 time Symbol VDDDR Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
tSREL
0
s
2 /fX Note 2
15
tWAIT
Release by RESET Release by interrupt request
ms ms
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation.
12 15 17 2. Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register. Remark fX: System clock oscillation frequency
Data Retention Timing (STOP mode release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT mode STOP mode Data retention mode Operating mode
VDD
VDDDR STOP instruction execution Standby release signal (interrupt request)
tSREL
tWAIT
36
Data Sheet U14667EJ1V1DS00
PD78F9116A
9. PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30 16 detail of lead end F G T
P 1 A 15 E
L U
H I J
S
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P T U
MILLIMETERS 9.850.15 0.45 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S30MC-65-5A4-2
Data Sheet U14667EJ1V1DS00
37
PD78F9116A
10. RECOMMENDED SOLDERING CONDITIONS
The PD78F9116A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions
PD78F9116AMC-5A4: 30-pin plastic SSOP (7.62 mm (300))
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-3
Infrared reflow
Package peak temperature: 235C, Reflow time: 30 seconds or below (at 210C Note or higher), Number of reflow processes : 3 max., Exposure limit : 7days (after that, prebaking is necessary at 125C for 10 hours)
VPS
Package peak temperature: 215C, Reflow time: 40 seconds or below (at 200C Note or higher), Number of reflow processes : 3 max., Exposure limit : 7days (after that, prebaking is necessary at 125C for 10 hours)
VP15-107-3
Wave soldering
Solder bath temperature: 260C or below, Flow time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120C or below (package surface temperature), Note Exposure limit : 7days (after that, prebaking is necessary at 125C for 10 hours) Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row)
WS60-107-1
Partial heating
-
Note Caution
After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Do not use different soldering methods together (except for partial heating).
38
Data Sheet U14667EJ1V1DS00
PD78F9116A
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78F9116A. Language Processing Software
RA78K0S
Notes 1, 2, 3
Assembler package common to 78K/0S Series C compiler package common to 78K/0S Series Device file for PD78F9116A
CC78K0S
Notes 1, 2, 3
DF789136
Notes 1, 2, 3
Flash Memory Writing Tools
Flashpro lIl Note 4 (Model number: FL-PR3 , PG-FP3) FA-30MC
Note 4
Dedicated flash programmer for on-chip flash memory
Flash memory writing adapter
Debugging Tools (1/2)
IE-78K0S-NS In-circuit emulator In-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0S Series product. It supports the ID78K0S-NS integrated debugger. Used in combination with an AC adapter, emulation probe, and interface adapter connecting to the host machine. Adapter used to supply power from a power outlet of 100 V AC to 240 V AC. Adapter when PC-9800 series PC (except notebook type) is used as the IE-78K0S-NS host machine (C bus supported). PC card and interface cable when notebook PC is used as the IE-78K0S-NS host machine (PCMCIA socket supported). Adapter when using an IBM PC/ATTM or compatible as the IE-78K0S-NS host machine. Adapter when using PC that includes a PCI bus as the IE-78K0S-NS host machine. Board for emulation of the peripheral hardware peculiar to a device. Used in combination with an in-circuit emulator. Board used to connect the in-circuit emulator to the target system. For a 30-pin plastic SSOP (MC-5A4 type), used in combination with NGS-30.
Note 4
IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-789136-NS-EM1 Emulation board NP-36GS
Note 4
NGS-30 Conversion socket
Conversion socket used to connect the NP-36GS to the target system board designed to mount a 30-pin plastic SSOP (MC-5A4 type).
Notes 1. PC-9800 series (Japanese WindowsTM) based 2. IBM PC/AT or compatibles (Japanese/English Windows) based 3. HP9000 series 700TM (HP-UXTM), SPARCstationTM (SunOSTM, SolarisTM), or NEWSTM (NEWS-OSTM) based. 4. Products made by Naito Densei Machida Mfg. Co., Ltd. (Phone: +81-44-822-3813). Remark RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789136.
Data Sheet U14667EJ1V1DS00
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PD78F9116A
Debugging Tools (2/2)
SM78K0S
Notes 1, 2
System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for PD78F9116A
ID78K0S-NS DF789136
Notes 1, 2
Notes 1, 2
Real-time OS
MX78K0S
Notes 1, 2
OS for 78K/0S Series
Notes 1. PC-9800 series (Japanese Windows) based. 2. IBM PC/AT or compatibles (Japanese/English Windows) based.
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Data Sheet U14667EJ1V1DS00
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APPENDIX B RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices
Document No. Document Name Japanese English U14590E
PD789101A, 102A, 104A, 111A, 112A, 114A, 101A(A), 102A(A), 104A(A), 111A(A), 112A(A), 114A(A) Data Sheet PD78F9116A Data Sheet PD789104A, 789114A, 789124A, 789134A Subseries User's Manual
78K/0S Series User's Manual Instruction 78K/0, 78K/0S Series Application Note Flash Memory Write
U14590J
U14667J U14643J U11047J U14458J
This manual To be prepared U11047E U14458E
Documents Related to Development Tools (User's Manuals)
Document No. Document Name Japanese RA78K0S Assembler Package Operation Assembly Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K0S System Simulator Windows Based SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference U11622J U11599J U11623J English U11622E U11599E U11623E
U11816J U11817J U11489J U10092J
U11816E U11817E U11489E U10092E
ID78K0S-NS Integrated Debugger Windows Based IE-78K0S-NS In-circuit Emulator IE-789136-NS-EM1 Emulation Board
U12901J U13549J U14363J
U12901E U13549E U14363E
Documents Related to Embedded Software (User's Manuals)
Document No. Document Name Japanese 78K/0S Series OS MX78K0S Fundamental U12938J English U12938E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U14667EJ1V1DS00
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PD78F9116A
Other Related Documents
Document No. Document Name Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E - English
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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Data Sheet U14667EJ1V1DS00
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Data Sheet U14667EJ1V1DS00
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[ MEMO ]
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Data Sheet U14667EJ1V1DS00
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Data Sheet U14667EJ1V1DS00
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation.
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Data Sheet U14667EJ1V1DS00
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14667EJ1V1DS00
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PD78F9116A
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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