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DATA SHEET
MOS INTEGRATED CIRCUITS
PD78F9116B, 78F9116B(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The PD78F9116B is a PD789114A Subseries product of the 78K/0S Series. The PD78F9116B replaces the internal ROM of the PD789111A,789112A and 789114A with flash memory, which enables the writing/erasing of a program while the device is mounted on the board. A stricter quality assurance program (called special grade in NEC's grade classification) is applied to the
PD78F9116B(A), compared to the PD78F9116B, which are classified as standard grade. Because flash memory allows the program to be written and erased electrically with the device mounted on the board, this product is ideal for the evaluation stages of system development, small-scale production, and rapid development of new products.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD789104A, 789114A, 789124A, 789134A Subseries User's Manual: U14643E 78K/0S Series User's Manual Instruction: U11047E
FEATURES
* Pin-compatible with mask ROM version (excluding VPP pin) * Flash memory: * On-chip multiplier: 16 KB * Internal high-speed RAM: 256 bytes 8 bits x 8 bits = 16 bits * Minimum instruction execution time can be changed from high-speed (0.2 s) to low-speed (0.8 s) (@ 10.0 MHz operation with system clock, VDD = 4.5 to 5.5 V) * I/O ports: 20 * Serial interface: 1 channel: Switchable between 3-wire serial I/O and UART modes * 10-bit resolution A/D converter: 4 channels * Timers: 3 channels 1 channel * 16-bit timer: * 8-bit timer/event counter: 1 channel 1 channel * Watchdog timer: * Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Cleaners, washing machines, refrigerators and battery-charger
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U15929EJ1V0DS00 (1st edition) Date Published April 2002 N CP(K) Printed in Japan
(c)
2002
PD78F9116B, 78F9116B(A)
ORDERING INFORMATION
Part number Package 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) Quality grade Standard Special
PD78F9116BMC-5A4 PD78F9116BMC(A)-5A4
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Y subseries supports SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 30-pin 28-pin 20-pin 20-pin Products under development
PD789046 PD789026 PD789088 PD789074 PD789014 PD789062 PD789052
PD789074 with subsystem clock added PD789014 with enhanced timer function and expanded ROM and RAM PD789074 with enhanced timer function and expanded ROM and RAM PD789026 with enhanced timer function
On-chip UART and capable of low-voltage (1.8 V) operation RC oscillation version of PD789052 PD789860 without EEPROMTM, POC, and LVI
Small-scale package, general-purpose applications and A/D function 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
LCD drive
PD789177Y PD789167Y
PD789167 with 10-bit A/D PD789104A with enhanced timer PD789146 with 10-bit A/D PD789104A with EEPR OM added PD789124A with 10-bit A/D RC oscillation version of PD789104A PD789104A with 10-bit A/D PD789026 with 8-bit A/D and m ultiplier added
144-pin 88-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 52-pin 52-pin USB 64-pin 44-pin
78K/0S Series
PD789835 PD789830 PD789488 PD789478 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327
UART + 8-bit A/D + dot LCD (total display outputs: 96) UART + dot LCD (40 x 16) SIO + 10-bit A/D + internal voltage boosting method LCD (28 x 4) SIO + 8-bit A/D + resistance division method LCD (28 x 4)
PD789407A with 10-bit A/D PD789446 with 10-bit A/D PD789426 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (5 x 4) RC oscillation version of PD789306 SIO + internal voltage boosting method LCD (24 x 4) 8-bit A/D + internal voltage boosting method LCD (23 x 4) SIO + resistance division method LCD (24 x 4) SIO + 8-bit A/D + resistance division method LCD (28 x 4) SIO + 8-bit A/D + internal voltage boosting method LCD (15 x 4)
PD789803 PD789800
Inverter control
For PC keyboard. On-chip USB HUB function For PC keyboard. On-chip USB function
44-pin
PD789842
On-chip bus controller
On-chip inverter controller and UART
30-pin
PD789850
Keyless entry
On-chip CAN controller
30-pin 20-pin 20-pin
PD789862 PD789861 PD789860
VFD drive
PD789860 with enhanced timer function, added SIO, and expanded ROM and RAM RC oscillation version of PD789860
On-chip POC and key return circuit
52-pin
PD789871
Meter control
On-chip VFD controller (total display outputs: 25)
64-pin
PD789881
UART + resistance division method LCD (26 x 4)
Remark
VFD (Vacuum Fluorescent Display) is referred to as FIP documents, but the functions of the two are the same.
TM
(Fluorescent Indicator Panel) in some
Data Sheet U15929EJ1VDS
3
PD78F9116B, 78F9116B(A)
The major functional differences among the subseries are listed below. Series for General-Purpose and LCD Drive
Function Subseries Name Smallscale package, generalpurpose applications 8-Bit 10-Bit ROM Timer A/D Capacity 8-Bit 16-Bit Watch WDT A/D (Bytes) 16 K 4 K to 16 K 16 K to 32 K 3 ch 2 K to 8 K 2 K to 4 K 4K 1 ch 2 ch - - 22 14 RC-oscillation version - 16 K to 24 K 3 ch 8 K to 16 K 1 ch 2 K to 8 K 1 ch 1 ch - 1ch - 8 ch - 4 ch - 4 ch - 4 ch 24 K to 60 K 6 ch 24 K 32 K 24 K to 32 K 12 K to 24 K 12 K to 16 K 2 ch 1 ch 3 ch 8 ch - 7 ch - 6 ch - 6 ch 8 K to 16 K - - 1 ch 1 ch 1 ch 3 ch - 8 ch - 7 ch - 6 ch - 6 ch - 2 ch (UART: 1ch) 23 RC-oscillation version - 4 K to 24 K - 1 ch - 1 ch - 18 21 40 30 1 ch (UART: 1ch) 43 2 ch (UART: 1ch) 8 ch - 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1ch) 37 30 45 1.8 VNote Dot LCD supported 2.7 V 1.8 V - 20 On-chip EEPROM RC-oscillation version - 1 ch (UART: 1ch) 31 1.8 V - 1 ch 1 ch 1 ch - 24 1 ch - - Serial Interface I/O VDD
MIN.Value
Remarks
PD789046 PD789026 PD789088 PD789074 PD789014 PD789062 PD789052
1 ch (UART: 1ch)
34
1.8 V
-
Smallscale package, generalpurpose applications + A/D converter LCD drive
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789835 PD789830 PD789488 PD789478 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327
Note Flash memory version: 3.0 V
4
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
Series for ASSP
Function Subseries Name USB 8-Bit 10-Bit ROM Timer A/D Capacity 8-Bit 16-Bit Watch WDT A/D (Bytes) 8 K to 16 K 8K 8 K to 16 K 3 ch Note 1 1 ch 16 K 1 ch 1 ch - 1 ch 1 ch 8 ch 4 ch - - 1 ch (UART: 1 ch) 2 ch (UART: 1 ch) 2 ch - - 1 ch - - Serial Interface I/O VDD
MIN.Value
Remarks
PD789803 PD789800 PD789842 PD789850
2 ch (USB: 1 ch)
41 31 30 18
3.6 V 4.0 V 4.0 V 4.0 V
- - -
Inverter control On-chip bus controller
Keyless entry
PD789861
4K
2 ch
-
-
1 ch
-
-
-
14
1.8 V
RC-oscillation version, on-chip EEPROM
PD789860 PD789862
VFD drive Meter control 16 K 1 ch 2 ch - 1 ch 1 ch - 1 ch 1 ch - - - - 1 ch (UART: 1 ch) 1 ch 1 ch (UART: 1 ch) 22 33 2.7 V 28 2.7 VNote 2
On-chip EEPROM
PD789871 PD789881
4 K to 8 K 3 ch 16 K 2 ch
- -
Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V
Data Sheet U15929EJ1VDS
5
PD78F9116B, 78F9116B(A)
OVERVIEW OF FUNCTIONS
Item Internal memory Flash memory High-speed RAM Minimum instruction execution time General-purpose registers Instruction set 16 KB 256 bytes 0.2/0.8 s (@ 10.0 MHz operation with system clock, VDD = 4.5 to 5.5 V) 8 bits x 8 registers * 16-bit operations * Bit manipulations (set, reset, and test) 8 bits x 8 bits = 16 bits Total: * CMOS input: * CMOS I/O: * N-ch open-drain (12 V withstand voltage): A/D converters Serial interface Timer 10-bit resolution x 4 channels Switchable between 3-wire serial I/O and UART modes * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel 1 output (16-bit/8-bit timer alternate function) Maskable Non-maskable Internal: 6, External: 3 Internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C 30-pin plastic SSOP (7.62 mm (300)) 20 4 12 4 function
Multiplier I/O ports
Timer output Vectored interrupt sources Power supply voltage Operating ambient temperature Package
6
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
CONTENTS
1. 2. 3. 4.
PIN CONFIGURATION (TOP VIEW) .............................................................................................. BLOCK DIAGRAM............................................................................................................................
8 9
DIFFERENCES BETWEEN PD78F9116B, 78F9116B(A), AND MASK ROM VERSIONS ............ 10 PIN FUNCTIONS ............................................................................................................................... 11
4.1 4.2 4.3 Port Pins.................................................................................................................................................. Non-Port Pins.......................................................................................................................................... Pin I/O Circuits and Recommended Connection of Unused Pins...................................................... 11 12 13
5. 6.
MEMORY SPACE ............................................................................................................................. 15 FLASH MEMORY CHARACTERISTICS ........................................................................................... 16
6.1 6.2 6.3 6.4 Programming Environment ................................................................................................................... Communication Mode ............................................................................................................................ On-Board Pin Processing ...................................................................................................................... Connection When Using Flash Memory Writing Adapter ................................................................... 16 17 20 23
7.
INSTRUCTION SET OVERVIEW ..................................................................................................... 26
7.1 7.2 Conventions............................................................................................................................................ Operations............................................................................................................................................... 26 28
8. 9.
ELECTRICAL SPECIFICATIONS..................................................................................................... 33 PACKAGE DRAWING ...................................................................................................................... 45
10. RECOMMENDED SOLDERING CONDITIONS............................................................................... 46 APPENDIX A. DEVELOPMENT TOOLS.............................................................................................. 47 APPENDIX B. RELATED DOCUMENTS ............................................................................................. 49
Data Sheet U15929EJ1VDS
7
PD78F9116B, 78F9116B(A)
1. PIN CONFIGURATION (TOP VIEW)
* 30-pin plastic SSOP (7.62 mm (300))
PD78F9116BMC-5A4 PD78F9116BMC(A)-5A4
P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 AVDD P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 AVSS IC0 P50 P51 P52 P53 P00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P22/SI20/RXD20 P21/SO20/TXD20 P20/SCK20/ASCK20 P11 P10 VDD VSS X1 X2 IC0 VPP RESET P03 P02 P01
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Cautions 1. Connect the IC0 (Internally Connected) pin directly to VSS. 2. Connect the VPP pin directly to VSS in normal operation mode. 3. Connect the AVDD pin to VDD. 4. Connect the AVSS pin to VSS. ANI0 to ANI3: ASCK20: AVDD: AVSS: CPT20: IC0: INTP0 to INTP2: P00 to P03: P10, P11: P20 to P25: P50 to P53: P60 to P63: Analog input Asynchronous serial input Analog power supply Analog ground Capture trigger input Internally connected Interrupt from peripherals Port0 Port1 Port2 Port5 Port6 RESET: RXD20: SCK20: SI20: SO20: SS20: TI80: TO20, TO80: TXD20: VDD: VPP: VSS: X1, X2: Reset Receive data Serial clock input/output Serial data input Serial data output Chip select input Timer input Timer output Transmit data Power supply Programming power supply Ground Crystal 1, 2
8
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
2. BLOCK DIAGRAM
TI80/INTP2/P25 TO80/TO20 /INTP1/P24 8-bit timer/ event counter 80 Port 0 P00 to P03
TO20/TO80 /INTP1/P24 CPT20/INTP0 /SS20/P23
16-bit timer 20
Port 1
P10, P11
Port 2 Watchdog timer 78K/0S CPU core SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 SS20/INTP0 /CPT20/P23 RAM ANI0/P60 to ANI3/P63 AVDD AVSS A/D converter System control Serial interface 20 Port 6 Flash memory Port 5
P20 to P25
P50 to P53
P60 to P63
RESET X1 X2
Interrupt control
VDD VSS VPP IC0
INTP0/CPT20 /P23/SS20 INTP1/TO80 /TO20/P24 INTP2/TI80/P25
Data Sheet U15929EJ1VDS
9
PD78F9116B, 78F9116B(A)
3. DIFFERENCES BETWEEN PD78F9116B, 78F9116B(A), AND MASK ROM VERSIONS
The PD78F9116B and 78F9116B(A) are products in which flash memory is substituted for the internal ROM of the mask ROM version. The differences between the PD78F9116B, 78F9116B(A), and the mask ROM versions are shown in Table 3-1. Table 3-1. Differences Between PD78F9116B, 78F9116B(A), and Mask ROM Versions
Flash Memory Version Item Mask ROM Version
PD78F9116B PD78F9116B(A)
ROM High-speed RAM 16 KB (Flash memory) 256 bytes 12 (software control only) Provided See the relevant data sheet
PD789111A PD789111A(A)
2 KB
PD789112A PD789112A(A)
4 KB
PD789114A PD789114A(A)
8 KB
Internal memory
Pull-up resistor VPP pin Electric characteristics
16 (software control: 12, mask option specification: 4) Not provided
Caution
There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version.
10
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
4. PIN FUNCTIONS 4.1 Port Pins
I/O I/O Port 0 4-bit I/O port Input/output can be specified in 1-bit units When used as an input port, connection of an on-chip pull-up resistor can be specified by software. P10, P11 I/O Port 1 2-bit I/O port Input/output can be specified in 1-bit units When used as an input port, an connection of on-chip pull-up resistor can be specified by software. P20 P21 P22 P23 I/O Port 2 6-bit I/O port Input/output can be specified in 1-bit units When used as an input port, an connection of on-chip pull-up resistor can be specified by software. Input SCK20/ASCK20 SO20/TxD20 SI20/RxD20 INTP0/CPT20 /SS20 INTP1/TO80/TO20 INTP2/TI80 I/O Port 5 4-bit N-ch open-drain input/output port Input/output can be specified in 1-bit units. Port 6 4-bit input-only port Input - Input - Function After Reset Input Alternate Function -
Pin Name P00 to P03
P24 P25 P50 to P53
P60 to P63
Input
Input
ANI0 to ANI3
Data Sheet U15929EJ1VDS
11
PD78F9116B, 78F9116B(A)
4.2 Non-Port Pins
I/O Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Serial interface serial data input Serial interface serial data output Serial interface serial clock input/output Serial clock input for asynchronous serial interface Chip select input for serial interface Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface External count clock input to 8-bit timer/event counter 80 8-bit timer/event counter 80 output 16-bit timer 20 output Capture edge input A/D converter analog input A/D converter analog power supply A/D converter ground potential Connecting crystal resonator for main system clock oscillation After Reset Input Alternate Function P23/CPT20/SS20 P24/TO80/TO20 P25/TI80 Input Input Input Input Input Input Input Input Input Input Input Input - - - - System reset input Positive power supply Ground potential Sets flash memory programming mode. Applies high voltage when a program is written or verified. Internally connected. Connect directly to VSS. Input - - - P22/RxD20 P21/TxD20 P20/ASCK20 P20/SCK20 P23/CPT20/INTP0 P22/SI20 P21/SO20 P25/INTP2 P24/INTP1/TO20 P24/INTP1/TO80 P23/INTP0/SS20 P60 to P63 - - - - - - - -
Pin Name INTP0 INTP1 INTP2 SI20 SO20 SCK20 ASCK20 SS20 RxD20 TxD20 TI80 TO80 TO20 CPT20 ANI0 to ANI3 AVDD AVSS X1 X2 RESET VDD VSS VPP
Input Output I/O Input Input Input Output Input Output Output Input Input Input Input -
IC0
-
-
-
12
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 4-1. For the input/output circuit configuration of each type, refer to Figure 4-1. Table 4-1. Types of Pin Input/Output Circuits
Pin Name Input/Output Circuit Type 5-A I/O Recommended Connection of Unused Pins
P00 to P03 P10, P11 P20/SCK20/ASCK20 P21/SO20/TXD20 P22/SI20/RXD20 P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 P50 to P53
I/O
Input: Independently connect to VDD or VSS via a resistor. Output: Leave open
8-A
Input: Independently connect to VSS via a resistor. Output: Leave open
13-V
Input: Independently connect to VDD via a resistor. Output: Leave open Input - Connect directly to VDD or VSS. Connect directly to VDD. Connect directly to VSS.
P60/ANI0 to P63/ANI3 AVDD AVSS RESET IC0 VPP
9-C -
2 -
Input - Connect directly to VSS.
-
Connect a 10 k pull-down resistor or connect directly to VSS.
Data Sheet U15929EJ1VDS
13
PD78F9116B, 78F9116B(A)
Figure 4-1. Pin I/O Circuits
Type 2 Type 9-C
IN IN
P-ch N-ch AVSS
Comparator
+ -
VREF (Threshold voltage) Schmitt-triggered input with hysteresis characteristics
Input enable
Type 5-A
VDD
Type 13-V
Pull-up enable VDD Data P-ch
P-ch IN/OUT Output data Output disable IN/OUT N-ch
VSS Input enable Middle-voltage input buffer
Output disable
N-ch VSS
Input enable Type 8-A VDD
Pull-up enable VDD Data P-ch
P-ch
IN/OUT Output disable N-ch VSS
14
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
5. MEMORY SPACE
Figure 5-1 shows the memory map of the PD78F9116B and 78F9116B(A). Figure 5-1. Memory Map
FFFFH Special function register 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH
Reserved Data memory space 3FFFH 4000H 3FFFH Program area
Program memory space
Flash memory 16384 x 8 bits
0080H 007FH CALLT table area 0040H 003FH 0016H 0015H Program area Vector table area 0000H
0000H
Data Sheet U15929EJ1VDS
15
PD78F9116B, 78F9116B(A)
6. FLASH MEMORY CHARACTERISTICS
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV
Note
(part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the A flash memory writing adapter (program adapter), which is a target board used
target system (on-board).
exclusively for programming, is also provided. Note Under development Remark FL-PR3, FL-PR4, and the program adapter are the products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Programming using flash memory has the following advantages. * Software can be modified after the microcontroller is solder-mounted on the target system. * Distinguishing software facilities low-quantity, varied model production * Easy data adjustment when starting mass production
6.1
Programming Environment
The following shows the environment required for PD78F9116B and 78F9116B(A) flash memory programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (Part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1). For details, refer the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 6-1. Environment for Writing Program to Flash Memory
VPP RS-232C USB VDD VSS RESET Dedicated flash programmer 3-wire serial I/O Host machine or UART
PD78F9116B, 78F9116B(A)
16
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
6.2 Communication Mode
Use the communication mode shown in Table 6-1 to perform communication between the dedicated flash programmer and the PD78F9116B or 78F9116B(A). Table 6-1. Communication Mode List
Communication Mode TYPE SettingNote 1 COMM PORT SIO clock CPU clock Flash clock Multiple rate Pins used Number of VPP pulses
3-wire serial I/O (SIO3)
SIO ch-0 100 Hz to (3-wire, sync.) 1.25 MHzNote 2
Optional
1 to 10 MHzNote 2 1.0
SCK20/ASCK20/P20 SO20/TxD20/P21 SI20/RxD20/P22 P00 P01 P02
0
SIO ch-1 (3-wire, sync.) 1 to 10 MHzNote 2
1
UART (UART0)
UART ch-0
4800 to 76800 Optional bpsNote 2, 3
TxD20/SO20/P21 RxD20/SI20/P22
8
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (Part no. FL-PR4, PG-FP4)). 2. The possible setting range differs depending on the voltage. For details, refer to 8. ELECTRICAL SPECIFICATIONS. Caution Be sure to select a communication mode depending on the number of VPP pulses shown in Table 6-1. Figure 6-2. Communication Mode Selection Format
10 V VPP VDD VSS VPP pulses 1 2 n
VDD RESET VSS
Data Sheet U15929EJ1VDS
17
PD78F9116B, 78F9116B(A)
Figure 6-3. Example of Connection with Dedicated Flash Programmer (a) 3-Wired Serial I/O Mode (SIO ch-0)
Flashpro III VPP1 VDD RESET CLKNote SCK SO SI GND
PD78F9116B, 78F9116B(A)
VPP VDD, AVDD RESET X1 SCK20 SI20 SO20 VSS, AVSS
(b) 3-Wired Serial I/O Mode (SIO ch-1)
Flashpro III VPP1 VDD RESET CLKNote SCK SO SI GND
PD78F9116B, 78F9116B(A)
VPP VDD, AVDD RESET X1 P00 (Serial clock) P02 (Serial input) P01 (Serial output) VSS, AVSS
Note Connect this pin when the system clock is supplied by Flashpro III. When a resonator has already been connected to the X1 pin, the CLK pin does not need to be connected. Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. Before using the power supply connected to the VDD pin, supply voltage before starting programming.
18
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
(c) UART Mode
Flashpro III VPP1 VDD RESET CLKNote SO SI GND
PD78F9116B, 78F9116B(A)
VPP VDD, AVDD RESET X1 RxD20 TxD20 VSS, AVSS
Note Connect this pin when the system clock is supplied by Flashpro III. When a resonator has already been connected to the X1 pin, the CLK pin does not need to be connected. Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. Before using the power supply connected to the VDD pin, supply voltage before starting programming. If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the PD78F9116B and 78F9116B(A). III/Flashpro IV. Table 6-2. Pin Connection List
Signal Name I/O Pin Function Pin Name 3-Wire Serial I/O UART
For details, refer to the manual of Flashpro
VPP1 VPP2 VDD
Output - I/O - Output Output Input Output Output -
Write voltage - VDD voltage generation/voltage monitoring Ground Clock output Reset signal Reception signal Transmit signal Transfer clock -
VPP x VDD/AVDD
Note
x
Note
GND CLK RESET SI SO SCK HS
VSS/AVSS X1 RESET SO20/P01/TxD20 SI20/P02/RxD20 SCK20/P00 - x x x
Note VDD voltage must be supplied before programming is started. Remark : Pin must be connected. : If the signal is supplied on the target board, pin need not be connected. x: Pin need not be connected.
Data Sheet U15929EJ1VDS
19
PD78F9116B, 78F9116B(A)
6.3 On-Board Pin Processing
When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin, so perform the following. (1) Connect a pull-down resistor (RVPP = 10 k) to the VPP pin. (2) Use the jumper on the board to switch the VPP pin input to either the writer or directly to GND. A VPP pin connection example is shown below. Figure 6-4. VPP Pin Connection Example
PD78F9116B, 78F9116B(A)
Connection pin of dedicated flash programmer VPP
Pull-down resistor (RVPP)
The following shows the pins used by the serial interface.
Serial Interface 3-wire serial I/O (SIO3) Pins Used SCK20, SO20, SI20 P00, P01, P02 UART TxD20, RxD20
When connecting the dedicated flash programmer a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other devices may occur. Care must therefore be taken with such connections.
20
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
(1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 6-5. Signal Conflict (Input Pin of Serial Interface)
PD78F9116B, 78F9116B(A)
Signal conflict Input pin Other device Output pin
Connection pin of dedicated flash programmer
In the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device.
(2) Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. Figure 6-6. Abnormal Operation of Other Device
PD78F9116B, 78F9116B(A)
Connection pin of dedicated flash programmer Other device Input pin
Pin
If the signal output by the PD78F9116B or 78F9116B(A) affects another device in the flash memory programming mode, isolate the signals of the other device.
PD78F9116B, 78F9116B(A)
Connection pin of dedicated flash programmer Other device Input pin
Pin
If the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device.
Data Sheet U15929EJ1VDS
21
PD78F9116B, 78F9116B(A)
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash programmer. Figure 6-7. Signal Conflict (RESET Pin)
PD78F9116B, 78F9116B(A)
Signal Conflict RESET Reset signal generator Output pin Connection pin of dedicated flash programmer
The signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator.
When the PD78F9116B or 78F9116B(A) enters the flash memory programming mode, all the pins other than those that communicate in flash memory programming are in the same status as immediately after reset. If the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to VDD or VSS. When using the on-board clock, connect X1 and X2 as required in the normal operation mode. When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main resonator on-board, and leave the X2 pin open. When using the power supply output of the flash programmer, connect the VDD and VSS pins to VDD and GND of the flash programmer, respectively. When using the on-board power supply, connect it as required in the normal operation mode. Because the flash programmer monitors the voltage, however, VDD of the flash programmer must be connected. For the other power pins (AVDD and ASS), supply the same power supply as in the normal operation mode.
22
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
6.4 Connection When Using Flash Memory Writing Adapter
The following shows an example of the recommended connection when using the flash memory writing adapter. Figure 6-8. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch0)
VDD (2.7 to 5.5 V) GND
1 2 3 4 5
30 29 28 27 26
7 8 9 10 11 12 13 14 15
PD78F9116B PD78F9116B(A)
6
25 24 23 22 21 20 19 18 17 16
GND VDD LVDD
Flash programmer interface
SI
SO
SCK
CLKOUT
RESET
VPP RESERVE/HS
Data Sheet U15929EJ1VDS
23
PD78F9116B, 78F9116B(A)
Figure 6-9. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch1)
VDD (2.7 to 5.5 V) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDD LVDD
30 29 28 27 26 25
PD78F9116B PD78F9116B(A)
24 23 22 21 20 19 18 17 16
Flash programmer interface
SI
SO
SCK
CLKOUT
RESET
VPP RESERVE/HS
24
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
Figure 6-10. Example of Flash Memory Writing Adapter Connection When Using UART Mode
VDD (2.7 to 5.5 V) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDD LVDD
30 29 28 27 26 25
PD78F9116B PD78F9116B(A)
24 23 22 21 20 19 18 17 16
Flash programmer interface
SI
SO
SCK
CLKOUT
RESET
VPP RESERVE/HS
Data Sheet U15929EJ1VDS
25
PD78F9116B, 78F9116B(A)
7. INSTRUCTION SET OVERVIEW
This section shows a list of the instruction set for the PD78F9116B and 78F9116B(A).
7.1
Conventions
7.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords and must be described as they are. Each symbol has the following meaning. * * #: Immediate data specification !: Absolute address specification * * $: Relative address specification
[ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #,!, $, or [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 7-1. Operand Identifiers and Description Methods
Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7), AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol FE20H to FF1FH immediate data or label FE20H to FF1FH immediate data or label (even address only) 0000H to FFFFH immediate data or label (Only even addresses for 16-bit data transfer instructions) 0040H to 007FH immediate data or label (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
26
Data Sheet 15929EJ1V0DS
PD78F9116B, 78F9116B(A)
7.1.2 Descriptions of the operation field A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): XH, XL: : : : : addr16: jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive OR Inverted data 16-bit immediate data or label Signed 8-bit data (displacement value)
7.1.3 Description of the flag operation field (Blank): 0: 1: x: R: Not affected Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
Data Sheet 15929EJ1V0DS
27
PD78F9116B, 78F9116B(A)
7.2 Operations
Operand Byte Clock Operation Flag Z AC CY MOV r, #byte saddr , #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A XCH A, X A, r A, saddr A, sfr A, [DE] A, [HL] A, [HL + byte] MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX XCHW AX, rp
Note 3 Note 2 Note 1
Mnemonic
3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 3 2 2 1 1 1
6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 6 6 8 4 4 8
r byte (addr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A X A r A (saddr) A sfr A (DE) A (HL) A (HL + byte) rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp xxx xxx
Note 1
Note 3
Note 3
Notes 1. Except r = A 2. Except r = A or X 3. Only when rp = BC, DE, HL Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
28
Data Sheet 15929EJ1V0DS
PD78F9116B, 78F9116B(A)
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
ADD
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2
4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6
A, CY A + byte (saddr), CY (saddr) + byte A ,CY A + r A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte)
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x
ADDC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
SUB
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
SUBC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
AND
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
Data Sheet 15929EJ1V0DS
29
PD78F9116B, 78F9116B(A)
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
OR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1
4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2
A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL + byte) AX, CY AX + word AX, CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 (CY, A0 A7, Am + 1 Am) x 1 (CY A0, A7 CY, Am - 1 Am) x 1 (CY A7, A0 CY, Am + 1 Am) x 1
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
XOR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
CMP
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte]
ADDW SUBW CMPW INC
AX, #word AX, #word AX, #word r saddr
DEC
r saddr
INCW DECW ROR ROL RORC ROLC
rp rp A, 1 A, 1 A, 1 A, 1
x x x x
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
30
Data Sheet 15929EJ1V0DS
PD78F9116B, 78F9116B(A)
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
SET1
saddr. bit sfr. bit A. bit PSW. bit [HL]. bit
3 3 2 3 2 3 3 2 3 2 1 1 1 3
6 6 4 6 10 6 6 4 6 10 2 2 2 6
(saddr. bit) 1 sfr. bit 1 A. bit 1 PSW. bit 1 (HL) . bit 1 (saddr. bit) 0 sfr. bit 0 A. bit 0 PSW. bit 0 (HL) . bit 0 CY 1 CY 0 CY CY (SP - 1) (PC + 3)H,(SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H,(SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X RRR RRR 1 0 x x x x x x x
CLR1
saddr. bit sfr. bit A. bit PSW. bit [HL]. bit
SET1 CLR1 NOT1 CALL
CY CY CY !addr16
CALLT
[addr5]
1
8
RET
1
6
RETI
1
8
PUSH
PSW rp
1 1
2 4
POP
PSW rp
1 1
4 6
MOVW
SP, AX AX, SP
2 2 3 2 1
8 6 6 6 6
BR
!addr16 $addr16 AX
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
Data Sheet 15929EJ1V0DS
31
PD78F9116B, 78F9116B(A)
Mnemonic
Operand
Byte
Clock
Operation
Flag Z AC CY
BC BNC BZ BNZ BT
$addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16
2 2 2 2 4
6 6 6 6 10
PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr. bit) = 1 PC PC + 4 + jdisp8 if sfr. bit = 1 PC PC + 3 + jdisp8 if A. bit = 1 PC PC + 4 + jdisp8 if PSW. bit = 1 PC PC + 4 + jdisp8 if (saddr. bit) = 0 PC PC + 4 + jdisp8 if sfr. bit = 0 PC PC + 3 + jdisp8 if A. bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if(saddr) 0 No Operation IE 1(Enable Interrupt) IE 0(Disable Interrupt) Set HALT Mode Set STOP Mode
sfr. bit, $addr16 A. bit , $addr16 PSW. bit, $addr16 BF saddr. bit, $addr16
4 3 4 4
10 8 10 10
sfr. bit, $addr16 A. bit, $addr16 PSW. bit, $addr16 DBNZ B, $addr16
4 3 4 2
10 8 10 6
C, $addr16
2
6
saddr, $addr16
3
8
NOP EI DI HALT STOP
1 3 3 1 1
2 6 6 2 2
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC).
32
Data Sheet 15929EJ1V0DS
PD78F9116B, 78F9116B(A)
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD, AVDD VPP Input voltage VI1 VI2 Output voltage Output current, high VO IOH Per pin Total for all pins Per pin Total for all pins Output current, low IOL Per pin Total for all pins Per pin Total for all pins Operating ambient temperature TA In normal operation mode During flash memory programming Storage temperature Tstg Pins other than P50 to P53 P50 to P53 With N-ch open drain VDD = AVDD Conditions Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to +13 -0.3 to VDD + 0.3 Unit V V V V V mA mA mA mA mA mA mA mA C C C
PD78F9116B
-10 -30
PD78F9116B(A)
10 120
PD78F9116B
30 160
PD78F9116B(A)
-7 -22 -40 to +85 10 to 40 -40 to +125
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U15929EJ1V0DS
33
PD78F9116B, 78F9116B(A)
System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
VPP X1 X2
Parameter Oscillation frequency (fX)Note 1
Conditions VDD = 4.5 to 5.5 V VDD = 3.0 to 5.5 V VDD = 1.8 to 5.5 V
MIN. 1.0 1.0 1.0
TYP.
MAX. 10.0 6.0 5.0 4
Unit MHz MHz MHz ms
C1
C2
Oscillation stabilization timeNote 2
After VDD reaches oscillation voltage range MIN. VDD = 4.5 to 5.5 V VDD = 3.0 to 5.5 V VDD = 1.8 to 5.5 V 1.0 1.0 1.0
Crystal resonator
Oscillation frequency (fX)Note 1
VPP X1 X2
10.0 6.0 5.0 10 30
MHz MHz MHz ms
C1
C2
Oscillation stabilization timeNote 2 External clock X1 input frequency (fX)
Note 1
VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V VDD = 3.0 to 5.5 V VDD = 1.8 to 5.5 V 1.0 1.0 1.0 45 75 85 1.0
X1
X2
10.0 6.0 5.0 500 500 500 5.0
MHz MHz MHz ns ns ns MHz
X1 input high-/low-level width (tXH, tXL)
VDD = 4.5 to 5.5 V VDD = 3.0 to 5.5 V VDD = 1.8 to 5.5 V
X1
X2
X1 input frequency (fX)
Note 1
VDD = 2.7 to 5.5 V
OPEN
X1 input high-/low-level width (tXH, tXL)
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use the resonator that stabilizes oscillation during the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
34
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Output current, high Symbol IOH Per pin Total for all pins Per pin Total for all pins Output current, low IOL Per pin Total for all pins Per pin Total for all pins Input voltage, high VIH1 Pins other than described below P50 to P53 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 0.7 VDD 0.9 VDD 0.7 VDD 0.9 VDD Conditions MIN. TYP. MAX. -1 -15 Unit mA mA mA mA mA mA mA mA V V V V
PD78F9116B
PD78F9116B(A)
-1 -11
PD78F9116B
10 80
PD78F9116B(A)
3 60 VDD VDD 12 12
VIH2
N-ch open drain VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V, TA = 25 to 85 C
VIH3
RESET, P20 to P25
VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
0.8 VDD 0.9 VDD VDD - 0.5 VDD - 0.1 0 0 0 0
VDD VDD VDD VDD 0.3 VDD 0.1 VDD 0.3 VDD 0.1 VDD
V V V V V V V V
VIH4
X1, X2
VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V
Input voltage, low
VIL1
Pins other than described below P50 to P53
VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
VIL2
N-ch open drain VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V, TA = 25 to 85 C
VIL3
RESET, P20 to P25
VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
0 0 0 0 VDD - 1.0 VDD - 0.5
0.2 VDD 0.1 VDD 0.4 0.1
V V V V V V
VIL4
X1, X2
VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V
Output voltage, high
VOH1 VOH2
VDD = 4.5 to 5.5 V, IOH = -1 mA VDD = 1.8 to 5.5 V, IOH = -100 A Pins other than P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78F9116B) VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78F9116B(A)) VDD = 1.8 to 5.5 V, IOL = 400 A
Output voltage, low
VOL1
1.0
V
1.0
V
0.5 1.0
V V
VOL2
P50 to P53
VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78F9116B) VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78F9116B(A)) VDD = 1.8 to 5.5 V, IOL = 1.6 mA
1.0
V
0.4
V
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U15929EJ1V0DS
35
PD78F9116B, 78F9116B(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Input leakage current, high Symbol ILIH1 ILIH2 ILIH3 Input leakage current, low ILIL1 ILIL2 ILIL3 Output leakage current, high Output leakage current, low Power supply current ILOH ILOL Conditions Pins other than X1, X2, or P50 to P53 X1, X2 P50 to P53 (N-ch open drain) Pins other than X1, X2, or P50 to P53 X1, X2 P50 to P53 (N-ch open drain) VOUT = VDD VOUT = 0 V VIN = 0 V, for pins other than P50 to P53 10.0 MHz crystal oscillation operating mode 6.0 MHz crystal oscillation operating mode 5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) IDD2
Note 2
MIN.
TYP.
MAX. 3 20
Unit
VIN = VDD
A A A A A A A A
k mA mA mA mA mA mA mA mA mA mA
VIN = 12 V VIN = 0 V
20 -3 -20 -3Note 1 3 -3 50 100 10.0 6.0 4.0 1.0 0.8 1.2 0.9 0.6 0.3 0.2 0.1 0.05 0.05 11.0 7.0 5.0 2.0 1.8 200 20.0 12.0 10.0 2.5 2.0 6.0 2.8 2.5 2.0 1.5 30 10 10 22.5 14.5 12.5 5.0 4.5
Software pull-up resistor R1 IDD1Note 2
VDD = 5.0 V10%Note 4 VDD = 5.0 V10%Note 4 VDD = 5.0 V10%Note 4 VDD = 3.0 V10%Note 5 VDD = 2.0 V10%Note 5 VDD = 5.0 V10%Note 4 VDD = 5.0 V10%Note 4 VDD = 5.0 V10%Note 4 VDD = 3.0 V10%Note 5 VDD = 2.0 V10%Note 5 VDD = 5.0 V10% VDD = 3.0 V10% VDD = 2.0 V10%
10.0 MHz crystal oscillation HALT mode 6.0 MHz crystal oscillation HALT mode 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF)
IDD3
Note 2
STOP mode
A A A
mA mA mA mA mA
IDD4Note 3
10.0 MHz crystal oscillation A/D operating mode 6.0 MHz crystal oscillation A/D operating mode 5.0 MHz crystal oscillation A/D operating mode (C1 = C2 = 22 pF)
VDD = 5.0 V10%Note 4 VDD = 5.0 V10%Note 4 VDD = 5.0 V10%Note 4 VDD = 3.0 V10%Note 5 VDD = 2.0 V10%Note 5
Notes 1. When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not included. 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H.) 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
36
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V)
Parameter Operating frequency Symbol fX VDD = 4.5 to 5.5 V VDD = 3.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V Write current (VDD pin) Note Write current (VPP pin) Note Erase current (VDD pin) Note Erase current (VPP pin) Note Unit erase time Total erase time Write count VPP supply voltage VPP0 VPP1 IDDW IPPW IDDE IPPE ter tera Erase/write are regarded as 1 cycle In normal operation During flash memory programming 0 9.7 10.0 When VPP supply voltage = VPP1 ( 5.0 MHz crystal oscillation operating mode ) When VPP supply voltage = VPP1 When VPP supply voltage = VPP1 ( 5.0 MHz crystal oscillation operating mode ) When VPP supply voltage = VPP1 0.2 0.2 Conditions MIN. 1.0 1.0 1.0 1.0 TYP. MAX. 10.0 6.0 5.0 1.25 21 22.5 3 115 0.2 20 20 0.2VDD 10.3 Unit MHz MHz MHz MHz mA mA mA mA s s Times V V
Note The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD current are not included.
Data Sheet U15929EJ1V0DS
37
PD78F9116B, 78F9116B(A)
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) Symbol TCY VDD = 4.5 to 5.5 V VDD = 3.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V TI80 input high-/lowlevel width TI80 input frequency tTIH, tTIL fTI VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V Interrupt input high/low-level width RESET low-level width CPT20 input high/low-level width tINTH, tINTL tRSL INTP0 to INTP2 Conditions MIN. 0.2 0.33 0.4 1.6 0.1 1.8 0 0 10 4 275 TYP. MAX. 8 8 8 8 Unit
s s s s s s
MHz kHz
s s s
10
tCPH, tCPL
10
TCY vs VDD
60
10
Cycle time TCY [s]
Guaranteed operation range
1.0
0.4
0.1 1 2 3 4 5 6 Supply voltage VDD [V]
38
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
(2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...Internal clock output)
Parameter SCK20 cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V SCK20 high-/lowlevel width SI20 setup time (to SCK20) SI20 hold time (from SCK20) SO20 output delay time from SCK20 tKH1, tKL1 tSIK1 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKSI1 VDD = 2.7 to 5.5 V MIN. 800 3200 tKCY1/2 - 50 tKCY1/2 - 150 150 500 400 600 tKSO1 R = 1 k , C = 100 pFNote VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 0 0 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...External clock input)
Parameter SCK20 cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V SCK20 high-/lowlevel width SI20 setup time (to SCK20) SI20 hold time (from SCK20) SO20 output delay time from SCK20 SO20 setup time (for SS20 when SS20 is used) SO20 disable time (for SS20 when SS20 is used) tKH2, tKL2 tSIK2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKSI2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKSO2 R = 1 k, C = 100 pFNote VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKDS2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V MIN. 800 3200 400 1600 100 150 400 600 0 0 300 1000 120 400 240 800 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKAS2
Note R and C are the load resistance and load capacitance of the SO output line. (iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V MIN. TYP. MAX. 78125 19531 Unit bps bps
Data Sheet U15929EJ1V0DS
39
PD78F9116B, 78F9116B(A)
(iv) UART mode (external clock input)
Parameter ASCK20 cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V ASCK20 high-/lowlevel width Transfer rate tKH3, tKL3 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V ASCK20 rise/fall time tR, tF MIN. 800 3200 400 1600 39063 9766 1 TYP. MAX. Unit ns ns ns ns bps bps
s
40
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
AC Timing Test Points (excluding X1 input)
0.8VDD 0.2VDD 0.8VDD 0.2VDD
Test points
Clock Timing
1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
TI Timing
1/fTI tTIL tTIH
TI80
Interrupt Input Timing
tINTL tINTH
INTP0 to INTP2
RESET Input Timing
tRSL
RESET
Data Sheet U15929EJ1V0DS
41
PD78F9116B, 78F9116B(A)
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCK20
tSIKm
tKSIm
SI20
Input data
tKSOm
SO20
Output data
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20 tKAS2 tKDS2
SO20
Output data
UART mode (external clock input):
tKCY3 tKL3 tR ASCK20 tKH3 tF
42
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
10-Bit A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote1,2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V Conversion time tCONV 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V Zero-scale errorNote1,2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V Full-scale error
Note1,2
Symbol
Conditions
MIN. 10
TYP. 10 0.2 0.4 0.8
MAX. 10 0.4 0.6 1.2 100 100 100 0.4 0.6 1.2 0.4 0.6 1.2 2.5 4.5 8.5 1.5 2.0 3.5
Unit bit %FSR %FSR %FSR
12 14 28
s s s
%FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB LSB V
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Integral linearity errorNote1
ILE
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Differential linearity errorNote1
DLE
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V
Analog input voltage
VIAN
0
AVDD
Notes 1. Excludes quantization error (0.05%FSR). 2. It is indicated as a ratio to the full-scale value (%FSR).
Data Sheet U15929EJ1V0DS
43
PD78F9116B, 78F9116B(A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Release signal set time Oscillation stabilization wait timeNote 1 Symbol VDDDR Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
tSREL
0
s
215/fX Note 2 ms ms
tWAIT
Release by RESET Release by interrupt request
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 2. Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register. Remark fX: System clock oscillation frequency
12 15 17
Data Retention Timing (STOP mode release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT mode STOP mode Data retention mode Operating mode
VDD
VDDDR STOP instruction execution Standby release signal (interrupt request)
tSREL
tWAIT
44
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
9. PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30 16 detail of lead end F G T
P 1 A 15 E
L U
H I J
S
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P T U
MILLIMETERS 9.850.15 0.45 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S30MC-65-5A4-2
Data Sheet U15929EJ1V0DS
45
PD78F9116B, 78F9116B(A)
10. RECOMMENDED SOLDERING CONDITIONS
The PD78F9116B and 78F9116B(A) should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions
PD78F9116BMC-5A4: 30-pin plastic SSOP (7.62 mm (300)) PD78F9116BMC(A)-5A4: 30-pin plastic SSOP (7.62 mm (300))
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-3
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less: 3 max., Exposure limit: 7daysNote (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three time or less, Exposure limit: 7daysNote (after that, prebake at 125C for 10 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once Preheating temperature: 120C or below (package surface temperature), Exposure limit : 7daysNote (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 sec. max. (per pin row)
VPS
VP15-107-3
Wave soldering
WS60-107-1
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
46
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78F9116B and 78F9116B(A). Software package
SP78K0SNotes 1, 2 CD-ROM in which the development tools (software) common to the 78K/0S Series are included as a package
Language Processing Software
RA78K0SNotes 1, 2, 3 CC78K0S
Notes 1, 2, 3
Assembler package common to 78K/0S Series C compiler package common to 78K/0S Series Device file for PD78F9116B
DF789136
Notes 1, 2, 3
Flash Memory Writing Tools
Flashpro lIl (Model number: FL-PR3Note 4, PG-FP3) FA-30MCNote 4 Dedicated flash programmer for on-chip flash memory
Flash memory writing adapter
Debugging Tools (1/2)
IE-78K0S-NS In-circuit emulator In-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0S Series product. It supports the ID78K0S-NS integrated debugger. Used in combination with an AC adapter, emulation probe, and interface adapter connecting to the host machine. The IE-78K0S-NS-A provides a coverage function in addition to the IE-78K0S-NS functions, thus enhancing the debug functions, including the tracer and timer functions. Adapter used to supply power from a power outlet of 100 V AC to 240 V AC. Adapter when PC-9800 series PC (except notebook type) is used as the host machine (C bus supported). PC card and interface cable when notebook PC is used as the host machine (PCMCIA socket supported). Adapter when using an IBM PC/ATTM or compatible as the host machine. Adapter when using PC that includes a PCI bus as the IE-78K0S-NS host machine. Board for emulation of the peripheral hardware peculiar to a device. Used in combination with an in-circuit emulator. Board used to connect the in-circuit emulator to the target system. For a 30-pin plastic SSOP (MC-5A4 type), used in combination with NGS-30. Conversion socket used to connect the NP-36GS to the target system board designed to mount a 30-pin plastic SSOP (MC-5A4 type).
IE-78K0S-NS-A In-circuit emulator IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-789136-NS-EM1 Emulation board NP-36GSNote 4 NGS-30Note 4 Conversion socket
Notes 1. PC-9800 series (Japanese WindowsTM) based 2. IBM PC/AT or compatibles (Japanese/English Windows) based 3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based. 4. Products made by Naito Densei Machida Mfg. Co., Ltd. (Phone: +81-45-475-4191) Remark RA78K0S, CC78K0S, SM78K0S, and ID78K0S-NS are used in combination with the DF789136.
Data Sheet U15929EJ1V0DS
47
PD78F9116B, 78F9116B(A)
Debugging Tools (2/2)
SM78K0SNotes 1, 2 ID78K0S-NS DF789136
Notes 1, 2
System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for PD78F9116B
Notes 1, 2
Notes 1. PC-9800 series (Japanese Windows) based 2. IBM PC/AT or compatibles (Japanese/English Windows) based Remark RA78K0S, CC78K0S, SM78K0S, and ID78K0S-NS are used in combination with the DF789136.
48
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
APPENDIX B. RELATED DOCUMENTS
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Documents Related to Devices
Document Name Document No. U14590E
PD789101A, 102A, 104A, 111A, 112A, 114A, 101A(A), 102A(A), 104A(A), 111A(A), 112A(A), 114A(A) Data Sheet PD78F9116B, 78F9116B(A) Data Sheet PD789104A, 789114A, 789124A, 789134A Subseries User's Manual
78K/0S Series User's Manual Instructions
This manual U14643E U11047E
Documents Related to Development Software Tools (User's Manuals)
Document Name RA78K0S Assembler Package Operation Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later SM78K Series System Simulator Ver. 2.10 or Later ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Project Manager Ver. 3.12 or Later (Windows Based) External Part User Open Interface Specification Operation (Windows Based) U15006E U14910E Operation (Windows Based) Document No. U14876E U14877E U11623E U14871E U14872E U14611E
U14610E
Documents Related to Development Hardware Tools (User's Manuals)
Document Name IE-78K0S-NS In-Circuit Emulator IE-78K0S-NS-A In-Circuit Emulator IE-789136-NS-EM1 Emulation Board Document No. U13549E U15207E U14363E
Documents Related to Flash Memory Writing
Document Name PG-FP3 Flash Memory Programmer User's Manual Document No. U13502E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U15929EJ1V0DS
49
PD78F9116B, 78F9116B(A)
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products & Packages Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
50
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
[MEMO]
Data Sheet U15929EJ1V0DS
51
PD78F9116B, 78F9116B(A)
[MEMO]
52
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
[MEMO]
Data Sheet U15929EJ1V0DS
53
PD78F9116B, 78F9116B(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM and FIP are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc.
54
Data Sheet U15929EJ1V0DS
PD78F9116B, 78F9116B(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-58-00 Fax: 01-3067-58-99
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Representacion en Espana Madrid, Spain Tel: 091-504-27-87 Fax: 091-504-28-60
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
NEC Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327
* Branch The Netherlands
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80
* Branch Sweden
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
* Filiale Italiana
Milano, Italy Tel: 02-667541 Fax: 02-66754299
J02.3-1
Data Sheet U15929EJ1V0DS
55
PD78F9116B, 78F9116B(A)
* The information in this document is current as of January, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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