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W27C520 64K x 8 ELECTRICALLY ERASABLE EPROM
1. GENERAL DESCRIPTION
The W27C520 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65,536 x 8 bits. It includes latches for the lower 8 address lines to multiplex with the 8 data lines. To cooperate with the MCU, this device could save the external TTL component, also cost and space. It requires only one supply in the range of 3.0V to 3.6V or 4.5V to 5.5V in normal read mode. The W27C520 provides an electrical chip erase function. It will be a great convenient when you need to change/update the contents in the device.
2. FEATURES
* High speed access time: 70/90 nS (max.) * Read operating current: 8/20 mA (max.) * Erase/Programming operating current * High Reliability CMOS Technology - 2K V ESD Protection - 200 mA Latchup Immunity * Fully static operation * All inputs and outputs directly LVTTL/CMOS
30 mA (max.) * Standby current: 20/100 A (max.) * Unregulated battery power supply range, 3.0V to 3.6V and 4.5V to 5.5V * +13V erase and programming voltage
compatible
* Three-state outputs * Available packages: 20-pin TSSOP and 20-pin
SOP
3. PIN CONFIGURATIONS
A10 A12 A14 ALE VDD #OE/VPP A15 A13 A11 A9
1 2 3 4 5 6 7 8 9 10 20 19 18 17
4. BLOCK DIAGRAM
A8 AD1 AD3 AD5 AD7 GND AD6 AD4 AD2 AD0
VDD GND A15 - A8 AD7 - AD0
L A T C H E S
ALE #OE / V PP
CONTROL
OUTPUT BUFFER
TSSOP 16 Top View
15 14 13 12 11
DECODER
MEMORY ARRAY
#OE/VPP A15 A13 A11 A9 AD0 AD2 AD4 AD6 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VDD ALE A14 A12 A10 A8 AD1 AD3 AD5 AD7
5. PIN DESCRIPTION
SYMBOL AD0 - AD7 A8 - A15 ALE #OE/VPP VDD GND DESCRIPTION Address/Data Inputs/Outputs Address Inputs Address Latch Enable Output Enable, Program/Erase Supply Voltage Power Supply Ground
SOP 16 Top View
15 14 13 12
11
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Publication Release Date: May 28, 2002 Revision A2
W27C520
6. FUNCTIONAL DESCRIPTION
Read Mode
Unlike conventional UVEPROMs, which has #CE and #OE two control functions, the W27C520 has one #OE/VPP and one ALE (address_latch_enable) control functions. The ALE makes lower address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed. #OE/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from ALE to output (TCE), and data are available at the outputs TOE after the falling edge of #OE /VPP, if TACC and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C520 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. There are two ways to enter Erase mode. One is to raise #OE/VPP to VPE (13V), VDD = VDE (6.5V), A9 = VHH (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by programming two consecutive commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is 50 S, while the other is 100 mS. Please refer to the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the device can force the device enter Normal Read Mode again.
Program Mode
Programming is the only way to change cell data from "1" to "0." The program mode is entered when #OE/VPP is raised to VPP (13V), VDD = VDP (6.5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.
Program Verify Mode
The device will enter the Program Verify Mode automatically after Program Mode. Only power down the device can force the device enter Normal Read Mode again.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the ALE and #OE/VPP pins, the W27C520 may have common inputs.
Standby Mode
The standby mode significantly reduces VDD current. This mode is entered when ALE and #OE/VPP keep high. In standby mode, all outputs are in a high impedance state.
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W27C520
System Considerations
An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (IDD), and transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VDD and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VDD and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
7. TABLE OF OPERATING MODES
(VPP = 13V, VPE = 13V, VHH = 12V, VDP = 6.5V, VDE = 6.5V, VDD = 3.3V or 5.0V, VDI = 5.0V, X = VIH or VIL)
MODE ALE Address Latch Enable Read Output Disable Standby Program Erase 1 Erase 2 VIH VIL VIL/ VIH VIH VIH VIH VIH #OE/VPP VIH VIL VIH VIH VPP VPE VPE
PIN OTHER ADDRESS AIN AIN X X AIN A8&A11 = VIL, A9 = VPE, A10 = VIH, Others = X First command: Addr. = 5555 (hex) Second command: Addr. = 2AAA (hex) VDD VDD VDD VDD VDD VDP VDE VDE VDE VDI VDI AD[7:0] A[7:0] DOUT High Z A[7:0] DIN X AA(hex) 10(hex) DA(Hex) 1F(Hex)
Product Identifiermanufacturer Product Identifier-device
VIL VIL
VIL VIL
A8 = VIL, A9 = VHH, Others = X A8 = VIH, A9 = VHH, Others = X
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Publication Release Date: May 28, 2002 Revision A2
W27C520
8. DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Ambient Temperature with Power Applied Storage Temperature Voltage on all Pins with Respect to Ground Except #OE/VPP, A9 and VDD Pins Voltage on #OE/VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground Voltage VDD Pin with Respect to Ground RATING -55 to +125 -65 to +150 -2.0 to +7.0 -2.0 to +7.0 -2.0 to +7.0 -2.0 to +14.0 UNIT C C V V V V
Notes: 1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 nS. Maximum output pin voltage is VDD +0.75V DC which may overshoot to +7.0V for pulses of less than 20 nS.
DC Erase Characteristics
(TA = 25 C 5 C, VDD = 6.5V 0.25V)
PARAMETER Input Load Current VDD Erase Current
SYM. ILI ICP
CONDITIONS VIN = VIL or VIH ALE = VIH, #OE/VPP = VPE A8 & A11 = VIL, A9 = VPE, A10 = VIH, Others = X ALE = VIH, #OE/VPP = VPE A8 & A11 = VIL, A9 = VPE, A10 = VIH, Others = X IOL = 2.1 mA IOH = -0.4 mA VDD = 5V 10% -
LIMITS MIN. -10 TYP. MAX. 10 30
UNIT A mA
VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 SID Voltage A9 Erase Voltage VPP Erase Voltage VDD Supply Voltage (Erase & Erase Verify)
IPP VIL VIH VOL VOH
HH
-0.3 2.4 2.4 11.5 12.75 12.75 6.25
12 13 13 6.5
30 0.8 VDD+0.3 0.45 12.5 13.25 13.25 6.75
mA V V V V V V V
VPE VPE VDE
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
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W27C520
9. CAPACITANCE
(VDD = 3.0V to 3.6V or 4.5V to 5.5V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT VIN = 0V VOUT = 0V
MAX. 6 12
UNIT pF pF
10. AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V/3V 10 nS 1.5V/1.5V CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA CONDITIONS
AC Test Load and Waveforms
+1.3V (IN914)
3.3K ohm
DOUT
100 pF (Including Jig and Scope)
Input
Test Points 3V
1.5V
Output
Test Points
1.5V
0V
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Publication Release Date: May 28, 2002 Revision A2
W27C520
11. READ OPERATION DC CHARACTERISTICS
(VDD = 3.0V to 3.6V or 4.5V to 5.5V, TA = 0 to 70 C)
PARAMETER Input Load Current Output Leakage Current Standby VDD Current (CMOS input)
SYM. ILI ILO
CONDITIONS MIN. VIN = 0V to VDD VOUT = 0V to VDD
VDD = 3.0V to 3.6V ALE = VDD 0.3V, #OE /VPP = VDD 0.3V All others inputs = GND/ VDD 0.3V ALE = VIL, IOUT = 0 mA f = 5 MHz
LIMITS TYP. -0.6 2.0 2.4 MAX. 5 5 20
UNIT A A A 100 8 mA 20 0.8 VDD +0.3 0.4 V V V V
-5 -5 -
ISB
VDD = 4.5V to 5.5V VDD = 3.0V to 3.6V VDD = 4.5V to 5.5V
VDD Operating Current
IDD
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
VIL VIH VOL VOH IOL = 2.1 mA IOH = -0.4 mA
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12. READ OPERATION AC CHARACTERISTICS
(VDD = 3.0V to 3.6V or 4.5V to 5.5V, TA = 0 to 70 C)
PARAMETER Address Latch Enable Access Time Address Latch Enable Width Address Access Time Address Setup Time Address Hold Time Output Enable Access Time #OE/VPP High to High-Z Output Output Hold from Address Change
SYM. TCE TALE TACC TAS TAH TOE TDF TOH
W27C520-70 MIN. 45 15 15 0 MAX. 70 70 35 25 -
W27C520-90 MIN. 45 15 15 0 MAX. 90 90 35 25 -
UNIT nS nS nS nS nS nS nS nS
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
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W27C520
13. DC PROGRAMMING CHARACTERISTICS
(VDD = 6.5V 0.25V, TA = 25 C 5 C)
PARAMETER Input Load Current VDD Program Current VPP Program Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage VPP Program Voltage VDD Supply Voltage (Program)
SYM. ILI ICP IPP VIL VIH VOL VOH VHH VPP VDP
CONDITIONS VIN = VIL or VIH ALE = VIH, #OE/VPP = VPP ALE = VIH, #OE /VPP = VPP IOL = 2.1 mA IOH = -0.4 mA VDD = 5V 10% -
MIN. -10 -0.3 2.4 2.4 11.5 12.75 6.25
LIMITS TYP. 12.0 13.0 6.5
MAX. 10 30 30 0.8 VDD +0.5 0.45 12.5 13.25 6.75
UNIT A mA mA V V V V V V V
14. AC PROGRAMMING/ERASE CHARACTERISTICS
(VDD = 6.5V 0.25V, TA = 25 C 5 C)
PARAMETER #OE/VPP Pulse Rise Time Address Latch Enable Width ALE Program Pulse Width ALE Erase Pulse Width ALE Erase Pulse Width 1 ALE Erase Pulse Width 2 Latched Address Setup Time Latched Address Hold Time Address Setup Time Address Hold Time #OE/VPP Setup Time #OE /VPP Hold Time Data Setup Time Data Hold Time Data Valid from #OE/VPP Low during Erase Verify Data Valid from #OE/VPP Low during Program Verify #OE/VPP High to Output High Z #OE/VPP High Voltage Delay After ALE Low #OE/VPP Recovery Time
SYM. MIN. TPRT TALE TPPW TEPW TEPW1 TEPW2 TLAS TLAH TAS TAH TOES TOEH TDS TDH TEOE TPOE TDFP TVS TVR 50 500 47.5 95 47.5 95 100 100 2.0 0 2.0 2.0 2.0 2.0 0 2.0 2.0
LIMITS TYP. 50 100 50 100 MAX. 52.5 105 52.5 105 150 150 130 -
UNIT nS nS S mS S mS nS nS S S S S S S nS nS nS S S
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
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Publication Release Date: May 28, 2002 Revision A2
W27C520
15. TIMING WAVEFORMS
AC Read Waveform
VIH A8-A15 VIL TALE ALE VIH VIL VIH #OE/Vpp VIL AD0-AD7 High Z TAS Address TACC TAH TCE TOE
Address Valid
TDF TOH High Z Data
Programming Waveform
PROGRAM VIH V IL TRPT TAS Address Stable
PROGRAM (VERIFY) TAH
A[15:8]
13V VIH V IL
#OE/Vpp
TOES TOEH TVS TVR TALE TDH Add TPOE TDFP Data out
ALE
VIH V IL TALE TPPW TLAH Add T DS Data in TLAS
AD[7:0]
VIH V IL
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W27C520
Timing Waveforms, continued
Erase Waveform 1
Read Company SID Read Device SID
Chip Erase VDD = 6.5V A9 = 13.0V Others = VILor VIH A8, A11 = VIL A10 = VIH
Erase (Verify) VDD = 6.5V
VDD = 3.3 or 5.0V A9 = 12.0V V IH V IL V IH AD[7:0] V IL DA 1F TPRT Others = VIL or VIH A8 = VIL A8 = VIH
A[15:8]
Address Valid
Add TVR
DOUT
13.0V V #OE/Vpp IH V IL V IH ALE V IL
TEOE
TOEH TOES TEPW
Erase Waveform 2
Read Company SID
Read Device SID
Chip Erase Command 1 VDD =6.5V TAS
A[15:8] = 55 A[15:8] = 2A
Command 2 VDD =6.5V
Erase Verify VDD =6.5V
A[15:8]
V IH V IL
VDD =5.0V A9=12.0 V Others=VIL or VIH A8=VIL A8=V IH
Address Valid
13.0V #OE/Vpp V IH V IL
TRPT
TOES TVS TPRT
TOEH
V IH ALE V IL TOES V IH AD[7:0] V IL DA
TEOE TALE TLAH TLAS 1F
55
TEPW1 TDS
AA
TEPW2 TDH
AA 10
Add
DOUT
Note: First command Address = 5555(hex) with Data = AA(hex) Second command Address = 2AAA(hex) with Data = 10(hex)
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Publication Release Date: May 28, 2002 Revision A2
W27C520
16. SMART PROGRAMMING ALGORITHM 1
Start
Address = First Location
VDD = 6.5V #OE/Vpp = 13V
Program One 50 S Pulse
Increment Address
No
Last Address ? Yes Address = First Location
Increment Address No Last Address ? Pass
X=0
Verify Byte
Fail Increment X
Yes Power Down Program One 50 S Pulse
No
X = 25 ?
VDD = 3.3 or 5.0V #OE/Vpp = V IL Yes
Compare All Bytes to Original Data Pass Device Passed
Fail
Device Failed
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W27C520
17. SMART PROGRAMMING ALGORITHM 2
Start
Address = First Location
VDD = 6.5V
X=0
Program One 50 S Pulse #OE/Vpp = 13V
Increment X X = 25? No Fail
Verify One Byte #OE/Vpp = VIL Verify One Byte #OE/Vpp = VIL
Yes
Fail
Pass
Increment Address
Pass
No Last Address ? Yes Power Down
VDD =3.3or5.0V
Compare All Bytes to Original Data Pass
Device Passed
Fail
Device Failed
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Publication Release Date: May 28, 2002 Revision A2
W27C520
18. SMART ERASE ALGORITHM 1
Start
X=0
VDD= 6.5V #OE/Vpp = 13V
A9 = 13V; A8&A11 = V IL A10 = V IH
Chip Erase 100 mS Pulse
Address = First Location Increment X V DD = 6.5V #OE/Vpp = VIL No Erase Verify Pass Yes Increment Address No Last Address? Yes Power Down Fail X = 20?
V DD = 3.3 or 5.0V #OE/Vpp = V IL
Compare All Bytes to FFs (HEX) Pass Pass Device
Fail
Fail Device
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W27C520
19. SMART ERASE ALGORITHM 2
Start
X=0
VDD = 6.5V #OE/Vpp = 13V
Program One 50 S Pulse with Address = 5555(Hex) Data = AA(Hex)
Program One 100 mS Pulse with Address = 2AAA(Hex) Data = 10(Hex)
Increment X VDD = 6.5V #OE/Vpp = VIL No Erase Verify Pass Yes Increment Address No Last Address? Yes Power Down Fail X = 20?
VDD = 3.3 or 5.0V #OE/Vpp = V IL
Compare All Bytes to FFs (HEX) Pass Pass Device
Fail
Fail Device
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Publication Release Date: May 28, 2002 Revision A2
W27C520
20. ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 70 90 70 90 OPERATING CURRENT MAX. (mA) 8/20 8/20 8/20 8/20 STANDBY CURRENT MAX. (A) 20/100 20/100 20/100 20/100 PACKAGE
W27C520W-70* W27C520W-90 W27C520S-70* W27C520S-90
Notes:
173 mil TSSOP 173 mil TSSOP 300 mil SOP 300 mil SOP
1. The power supply for 70nS parts is 4.5V - 5.5V. 2. The Part No is preliminary and might be changed after project is consoled. 3. Winbond reserves the right to make changes to its products without prior notice. 4. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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W27C520
21. PACKAGE DIMENSIONS
20-pin TSSOP
c b
L
Dimension in Inches Dimension in mm
Symbol
Min.
Nom. Max.
0.043
Min.
Nom. Max.
1.10 0.15 0.70 6.60 6.50 4.48 0.30 0.18 0.256 BSC
E1
E
A A1 L D E E1 b c e
0.002 0.020 0.252 0.246 0.169 0.007 0.003 0.65 BSC 0
0.006 0.05 0.028 0.50 0.260 6.40 0.256 6.25 0.176 4.30
e D A A1
0.012 0.18 0.007 0.09
8
0
8
20-pin SOP
c b
L
Dimension in Inches Dimension in mm
Symbol
Min.
0.092 0.003 0.015 0.497 0.393 0.291 0.013 0.009
Nom. Max.
Min.
Nom. Max.
2.67 0.305 0.889 13.0 10.7 7.60 0.508 0.330
E1
E
A A1 L D E E1 b c e
0.105 2.34 0.012 0.076 0.035 0.381 0.513 12.6 0.420 9.98 0.299 7.39
e D A A1
0.020 0.330 0.013 0.229
0.50 BSC 0 8 0
1.27 BSC 8
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Publication Release Date: May 28, 2002 Revision A2
W27C520
22. VERSION HISTORY
VERSION A1 A2 DATE Sept. 2000 May 28, 2002 PAGE 17 Initial Issued Modify power supply for 70 nS parts as 4.5 - 5.5V DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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