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KS0647
256 CHANNEL TFT-LCD GATE DRIVER
November. 1999. Ver. 0.1
Prepared by:
Jae il Byeon
kerigma@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
KS0647
256 CH. TFT-LCD GATE DRIVER
KS0647 Specification Revision History Version 0.0 0.1 Original
The contents of page 9, 10 and 13 have been modified
Content
Date Aug.1999 Nov.1999
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256 CH. TFT-LCD GATE DRIVER
KS0647
CONTENTS
INTRODUCTION .................................................................................................... 4 FEATURES ............................................................................................................ 4 BLOCK DIAGRAM................................................................................................. 5 PIN ASSIGNMENTS .............................................................................................. 6 PIN DESCRIPTIONS.............................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................ 8 RECOMMENDED OPERATION RATINGS........................................................... 8 DC CHARACTERISTICS ....................................................................................... 9 AC CHARACTERISTICS ..................................................................................... 10 AC TIMING DIAGRAM......................................................................................... 11 OPERATION DESCRIPTION............................................................................... 12
OPERATION METHOD ........................................................................................................ 12 OUTPUT PIN ........................................................................................................................ 12 VOLTAGE BIASING ............................................................................................................. 13 RECOMMENDED TIMING.................................................................................................... 14
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KS0647
256 CH. TFT-LCD GATE DRIVER
INTRODUCTION
The KS0647 is a TFT-LCD gate driver having 256 outputs. It can drive TFT panel gate ON voltage up to 40 V. It can operate within the logic voltage 3.0 to 5.5 V.
FEATURES
* * * * * 256 outputs Maximum TFT panel gate ON voltage = 40 V Bi - directional shift register Logic supply voltage = 3.0 to 5.5 V TCP
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256 CH. TFT-LCD GATE DRIVER
KS0647
BLOCK DIAGRAM
VDD VLO VSS1 U/D CPV
DI/O
S/R S/R 001 002
256 Shift Register
S/R S/R 255 256
DO/I
OE1 OE2 OE3
Level Shifter
VGG VSS2
256 Ouput Buffer
G001 G002
G255 G256
Figure 1. Block Diagram
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KS0647
256 CH. TFT-LCD GATE DRIVER
PIN ASSIGNMENTS
G256 G255 G254 G253 VGG VSS2 VSS1 VDD DO/I OE3
KS0647 (Top View)
OE2 OE1 CPV VLO U/D DI/O VLO VSS1 VSS2 VGG
G004 G003 G002 G001
Figure 2. Pin Assignments
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256 CH. TFT-LCD GATE DRIVER
KS0647
PIN DESCRIPTIONS
Symbol Pin Name I/O Description
DI/O DO/I
Start pulse input/output
When these inputs operate as the input, the start pulse data is read at the rising edge of shift clock, CPV. When these inputs operate as the output, the start pulse output is the next chip's start pulse input. The output pulse is generated I/O at the falling edge of the 256th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation. (Input = DO/I and output = DI/O) I I When U/D = H, DI/O G001 ...... G256 DO/I When U/D = L, DO/I G256 ...... G001 DI/O The shift register operates in synchronization with the rising edge of this input These inputs control the state of the driver outputs. When OE = H, the driver output is fixed to VSS2. When OE = L, the driver output is VGG or VSS2 corresponding to the data. The output signals change in synchronization with the rising edge of shift clock input, CPV. The amplitude of the driver output is VGG - VSS2. The input is internally connected to the logic ground, VSS1. The input operates as the TFT panel gate OFF voltage. Logic input range: VDD - VLO The TFT gate ON voltage is VGG - VSS2. 3.0 to 5.5 V The logic negative power supply, VSS1, is internally connected to the driver negative power supply, VSS2.
U/D CPV OE1 OE2 OE3 G001 to G256 VSS2 VLO VGG VDD VSS1
Shift direction control input Shift clock input
Output enable input
I
Driver output
O
Driver negative power supply Logic input low voltage Driver positive power supply Logic positive power supply Logic negative power supply
I I I I I
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KS0647
256 CH. TFT-LCD GATE DRIVER
ABSOLUTE MAXIMUM RATINGS (VSS1 = VSS2 = 0 V)
Table 1. Absolute Maximum Ratings Parameter Logic positive power supply Driver positive power supply Logic input low voltage Input voltage Operation temperature Storage temperature Symbol VDD VGG VLO VIN Top Tstg Ratings - 0.3 to 21.0 - 0.3 to 45.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 20 to 75 - 55 to 150 Unit V V V V C C
CAUTIONS If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded. It is desirable to use this product within the range of the absolute maximum ratings. The power supplying order is as follows. ON: VLO VDD VSS1, VSS2 Control Input VGG OFF: VGG Control Input VSS1, VSS2 VDD VLO
RECOMMENDED OPERATION RATINGS (VLO = 0 V VSS1 = VSS2)
Table 2. Recommended Operation Ratings Parameter Logic positive power supply Driver positive power supply Logic negative power supply Driver negative power supply Power supply voltage Operation frequency Output load Symbol VDD VGG VSS1 VSS2 VGG - VSS2 fCPV CL Min. 3.0 6 - 15 - 15 21 Typ. Max. 5.5 40 0 0 40 100 500 Unit V V V V V kHz pF
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256 CH. TFT-LCD GATE DRIVER
KS0647
DC CHARACTERISTICS (VLO = 0 V VSS1 = VSS2)
Table 3. DC Characteristics (Ta = - 20 to 75 C, VGG - VSS2 = 21 to 40 V, VLO - VSS1 = 15 to 0 V, VDD - VLO = 3.0 to 5.5 V) Parameter High input voltage Low input voltage High output voltage Low output voltage LCD driver output ON resistance High output current Low output current Input leak current Symbol VIH VIL VOH VOL ROH ROL IGG IDD ILK VX = VDD - VLO IOH = - 40 A IOL = 40 A VOUT = VGG - 0.5 V, VGG = 40 V, VSS2 = 0 V VOUT = 0.5 V, VGG = 40 V, VSS2 = 0 V Without output load VDD - VSS1 = 3.3 V VDD - VSS1 = 19 V Condition Min. VLO + 0.9VX VSS1 VDD - 0.4 VSS1 -5 Max. VDD VLO + 0.1VX VDD VSS1 + 0.4 500 500 400 400 1000 5 Unit V
(1)
Pin used
V V V A A A A G001 to G256 G001 to G256 VGG
(1) (3) (1) (2)
NOTES: 1. DI/O, DO/I, CPV, OE1, OE2, OE3, U/D used. 2. When U/D = H, DO/I used, and when U/D = L, DI/O used. 3. Input swing voltage = VDD to VDD - 3.0 V
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KS0647
256 CH. TFT-LCD GATE DRIVER
AC CHARACTERISTICS (VLO = 0 V VSS1 = VSS2)
Table 4. AC Characteristics (Ta = - 20 to 75 C, VGG - VSS2 = 21 to 40 V, VLO - VSS1 = 15 to 0 V, VDD - VLO = 3.0 to 5.5 V) Parameter Operation frequency Clock pulse width Output enable input width Data setup time Data hold time Output delay time (1) Output delay time (2) Output delay time (3) Symbol fCPV tCPVH, tCPVL twOE tsDI thDI tpdDO tpdG tpdOE Condition Duty = 50 % CL = 30 pF CL = 300 pF Min. 10 4 1 700 700 Max. 800 800 800 ns s Unit
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tCPVH tCPV 50 % tCPVL tsDI 50 % tpdG 50 % thDI 50 % 50 % 50 % 50 %
256 CH. TFT-LCD GATE DRIVER
AC TIMING DIAGRAM
CPV
DI/O (U/D=H) DO/I (U/D=L)
G1 (U/D=H) G256 (U/D=L)
50 % tpdOE twOE 50 % 50 % 50 %
OE1~3
tpdOE 50 %
Figure 3. AC Timing Diagram
tpdDO 50 %
G2 to G255
G256 (U/D=H) G1 (U/D=L)
tpdDO
DO/I (U/D=H) DI/O (U/D=L)
50 %
KS0647
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KS0647
256 CH. TFT-LCD GATE DRIVER
OPERATION DESCRIPTION
OPERATION METHOD
The start pulse input, DI/O (when U/D is "H") or DO/I (when U/D = "L"), is synchronized with the rising edge of CPV and stored in the first shift register. While stored pulse is transferred to the next register at the next rising edge of CPV, a new pulse is stored simultaneously. Output pin (G1 to G256) supplies VGG voltage or VSS2 voltage to the TFT-LCD panel depending on the pulse of the shift register. The start pulse output, DO/I (when U/D is "H") or DI/O (when U/D = "L"), is synchronized with the falling edge of CPV and the pulse of the last register (G1 or G256) is transferred to the next IC. The voltage level of the start pulse output is VDD with "H" data, VSS1 with "L" data The relationship between U/D and shift data inout pin is as follows: Table 5. The relationship between U/D and the start pulse input / output U/D Pin "H" (VDD) "L" (VSS1 - VLO) Start pulse input / output Input DI/O DO/I Output DO/I DI/O Data shift direction G1 G2 G3 G4 G5 ...... G256 G256 G255 G254 G253 ...... G1
OUTPUT PIN (G1 TO G256)
If the data of the shift register to an output drive pin is "H", the voltage level of the output is VGG and if the data is "L", the level of the output is VSS2. But, when OE is "H", the voltage level of the output is VSS2 irrespective of the data of the shift register. Table 6. The voltage level of the output Condition Pin OE1 OE2 OE3 OE1 OE2 OE3 "L" "H" State Control pin to LCD panel Controlled output pin by OE signal G1, G4, G7, ...... , G250, G253, G256 G2, G5, G8, ...... , G251, G254 G3, G6, G9, ...... , G252, G255 G1, G4, G7, ...... , G250, G253, G256 G2, G5, G8, ...... , G251, G254 G3, G6, G9, ...... , G252, G255 Normal output (VGG or VSS2) VSS2 Output level
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256 CH. TFT-LCD GATE DRIVER
KS0647
VOLTAGE BIASING
The driver negative power supply, VSS2, can be any value between VLO and VLO - 15V. And VSS2 is internally connected to the logic negative power supply, VSS1.
G1 to G256 VGG (40 V) G1 to G256 VGG (33 V)
Input signal VDD (3.3 V)
Logic Output VDD (3.3 V)
Input signal
Logic Output
VLO (0 V)
VLO (0 V) = VOFF = VSS1
VSS1 (-7 V) = VOFF
Figure 4. Example of Voltage Biasing
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KS0647
256 CH. TFT-LCD GATE DRIVER
RECOMMENDED TIMING
When U/D = "H" Input DI/O CPV OE1 OE2 OE3 G1 G2 G3 G4 G256 Output DO/I VGG VDD VSS2 VSS1
When U/D = "L" Input DO/I CPV OE1 OE3 OE2 G256 G255 G254 G253 G1 Output DI/O VGG VDD VSS2 VSS1
Figure 5. Recommended Timing
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256 CH. TFT-LCD GATE DRIVER
KS0647
NOTES
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