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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
August. 1999. Ver. 0.0
Prepared by:
Myoung-Sik, Suh mail to: mssuh@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670 Specification Revision History Version 0.0 Original Content Date Aug.1999
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
CONTENTS
INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSIGNMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS........................................................................................................................................... 7 OPERATION DESCRIPTION .............................................................................................................................. 8 DISPLAY DATA TRANSFER............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE................................................. 8 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 14 RECOMMENDED OPERATION CONDITIONS ................................................................................................. 14 DC CHARACTERISTICS................................................................................................................................... 15 SINGLE EDGE AC CHARACTERISTICS.......................................................................................................... 16 DOUBLE EDGE AC CHARACTERISTICS ........................................................................................................ 17 SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) ................................................................... 18 DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1).................................................................. 19 RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD....................... 20
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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The KS0670 is a 384 / 402 channel output, TFT-LCD source driver for an 256 gray scale LCD panel. Data input is based on digital input consisting of 8 bits by 6 dots, which can realize a full-color display of 16,700,000 color by output of 256 values gamma-corrected. This device has an internal D/A (Digital-to-Analog) converter for each output and 16 (8-by-2) reference voltages. Because the output dynamic range is as large as 7.8 - 14.8 Vp-p, it is unnecessary to operate level inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side, output gray scale voltages with different polarity can be output to the odd number output pins and the even output pins. KS0670 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel connection conveniently. Maximum operation clock frequency is 75 MHz at 3.0 V logic operation, single edge and it can be applied to the TFT-LCD panel of UXGA standard.
FEATURES
* * * * * * * * * * * * * TFT active matrix LCD source driver LSI 256G/S is possible through 16 (8 by 2) reference voltages and D/A converter Both dot inversion display and N-line inversion display are possible CMOS level input Compatible with gamma-correction Input data inversion function (DATPOL1,2) Single edge, Double edge compatible (DEC) Logic supply voltage: 2.5 - 3.6 V LCD driver supply voltage: 8.0 - 15.0 V Output dynamic range: 7.8 - 14.8 Vp-p Maximum operating frequency: fMAX = 75 MHz (internal data transmission rate at 3.0 V operation, single edge) Output: 384 / 402 outputs TCP
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
BLOCK DIAGRAM
Y402 Y401 Y400 Y003 Y002 8 8 Y001 8 8
BIAS
Output Buffer
TEST
POL VGMA1 VGMA16
16
D/A Converter
8
8
8
8
CLK1
Data Latch
8
8
8
8
DATPOL1 DATPOL2 D00 - D07 D10 - D17 D20 - D27 D30 - D37 D40 - D47 D50 - D57 8 Data Control 8 8 8 8 8 24 24
Data Register
67bit Shift Register
CLK2
DIO2
SHL
SELT
DEC
DIO1
Figure 1. KS0670 Block Diagram
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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
DIO1 D00 D01 D02 D03 D04 D05 D06 D07 D10 D11 D12 D13 D14 D15 D16 D17 D20 D21 D22 D23 D24 D25 D26 D27 TEST DATPOL1 DATPOL2 POL CLK1 CLK2 DEC VSS1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VSS2 VDD2 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14 VGMA15 VGMA16 SELT SHL VDD1 D30 D31 D32 D33 D34 D35 D36 D37 D40 D41 D42 D43 D44 D45 D46 D47 D50 D51 D52 D53 D54 D55 D56 D57 DIO2
Y001 Y002 Y003 Y004
Y399 Y400 Y401 Y402
Figure 2. KS0670 Pin Assignments
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(Top View)
KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
PIN DESCRIPTIONS
2.5 - 3.6 V 8.0 - 15.0 V Ground (0 V) Ground (0 V) The D/A converted 256 gray-scale analog voltage is output. The display data is input with a width of 48 bits, Display data input gray-scale data (8 bits) by 6 dots (R,G,B) DX0: LSB, DX7: MSB This pin controls the direction of shift register in cascade connection. Shift direction control The shift direction of the shift registers is as follows. SHL input SHL = H: DIO1 input, Y1 Y402, DIO2 output SHL = L: DIO2 input, Y402 Y1, DIO1 output SHL = H: Used as the start pulse input pin. DIO1 Start pulse input/output SHL = L: Used as the start pulse output pin. SHL = H: Used as the start pulse output pin. DIO2 Start pulse input/output SHL = L: Used as the start pulse input pin. DATPOL1,2 = L: Display data is not inverted DATPOL1 Data inversion input DATPOL1 = H: Display data of D0<0:7> - D2<0:7> is inverted DATPOL2 DATPOL2 = H: Display data of D3<0:7> - D5<0:7> is inverted POL = H: The reference voltage for odd number outputs are VGMA9 - VGMA16 and those for even number outputs are VGMA1 - VGMA8. POL Polarity input POL = L: The reference voltage for odd number outputs are VGMA1 - VGMA8 and those for even number outputs are VGMA9 - VGMA16. Refer to the shift register's shift clock input. When DEC is Low, the display data is loaded to the data register at the rising edge of CLK2 Shift clock input CLK2.When DEC is High, the display data is loaded to the data register at the rising and falling edge of CLK2. Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 Latch input CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. Outputs the G/S data at falling edge. Input the gamma corrected power supplies from external source. VGMA1 Gamma corrected power VDD2 > VGMA1 > VGMA2 > ...... > VGMA15 > VGMA16 > VSS2 - supplies Keep gray-scale power supply unchanged during the gray-scale VGMA16 voltage output. SELT = L: 384 Output (Y193 - Y210 are disabled), SELT = H: 402 SELT Output selection input Output DEC = L: Single Edge, the display data is loaded to the data register at Double edge selection DEC the rising edge of CLK2. DEC = H: Double Edge, the display data is input loaded to the data register at the rising and falling edge of CLK2. TEST = L: Normal operation mode TEST Test input TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 10k) Symbol VDD1 VDD2 VSS1 VSS2 Y1 - Y402 D0<0:7> - D5<0:7> Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs Description
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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
(1) DEC = "L" When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2). (2) DEC = "H" When DIO1 (or DIO2) pulse is loaded into internal latch on the rising (or falling) edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer. display data is valid on the next falling (or rising) edge of CLK2. Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd edge of CLK2 after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device. (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 16 (8 by 2) gamma corrected power supplies (VGMA1 - VGMA16). Besides, to be able to deal with dot line inversion when mounted on a single-side, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 8-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 8 gamma corrected voltages of VGMA1 - VGMA8 and VGMA9 - VGMA16.
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
SHL = H
OUTPUT DATA D00 - D07 Y1 Y2 First D10 - D17 D20 - D27 ...... D30 - D37 Y3 ...... Y400 Y401 Last D40 - D47 D50 - D57 Y402
SHL = L
OUTPUT DATA D00 - D07 Y1 Y2 Last D10 - D17 D20 - D27 ...... D30 - D37 Y3 ...... Y400 Y401 First D40 - D47 D50 - D57 Y402
Figure 3. Relationship between Shift Direction and Output Data
VDD2 VGMA1
32
VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7,8 VGMA9,10 VGMA11 VGMA12 VGMA13 VGMA14 VGMA15
32 128 48 14
VCOM
14 48 128 32
32
VGMA16 VSS2 00H 20H 40H 60H 80H A0H C0H E0H FFH
Figure 4. Gamma Correction Curve
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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R254, unit: ) Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Value 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 Name R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R15 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 Value 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 Name R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 Value 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Name R96 R97 R98 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 Value 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
Table 1. Resistor Strings (R0 - R254, unit: ) (Continued) Name R128 R129 R130 R131 R132 R133 R134 R135 R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R150 R151 R152 R153 R154 R155 R156 R157 R158 R159 Value 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Name R160 R161 R162 R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 R181 R182 R183 R184 R185 R186 R187 R188 R189 R190 R191 Value 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Name R192 R193 R194 R195 R196 R197 R198 R199 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 Value 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 Name R224 R225 R226 R227 R228 R229 R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 Value 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 200 200 200 200 200 200 200 200 200 200 200 200 200 200 930
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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value Input data 00H 01H : 18H : 1FH 20H 21H : 28H 29H : 3FH 40H 41H : 60H 61H : 7FH 80H 81H : A0H A1H : BFH C0H C1H : D8H D9H : EFH F0H F1H : F9H : FDH FEH FFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 : 1 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 1 1 : 0 1 1 : 1 : 1 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 1 0 1 G/S VH0 VH1 : VH24 : VH31 VH32 VH33 : VH40 VH41 : VH63 VH64 VH65 : VH96 VH97 : VH127 VH128 VH129 : VH160 VH161 : VH191 VH192 VH193 : VH216 VH217 : VH239 VH240 VH241 : VH249 : VH253 VH254 VH255 Output voltage VGMA1 VGMA1 + (VGMA2 - VGMA1) x 218 / 6976 : VGMA1 + (VGMA2 - VGMA1) x (218 x 24) / 6976 : VGMA1 + (VGMA2 - VGMA1) x (218 x 31) / 6976 VGMA2 VGMA2 + (VGMA3 - VGMA2) x (70 x 1) / 2240 : VGMA2 + (VGMA3 - VGMA2) x (70 x 8) / 2240 VGMA2 + (VGMA3 - VGMA2) x (70 x 9) / 2240 : VGMA2 + (VGMA3 - VGMA2) x (70 x 31) / 2240 VGMA3 VGMA3 + (VGMA4 - VGMA3) x (32 x 1) / 2048 : VGMA3 + (VGMA4 - VGMA3) x (32 x 32) / 2048 VGMA3 + (VGMA4 - VGMA3) x (32 x 33) / 2048 : VGMA3 + (VGMA4 - VGMA3) x (32 x 63) / 2048 VGMA4 VGMA4 + (VGMA5 - VGMA4) x (32 x 1) / 2048 : VGMA4 + (VGMA5 - VGMA4) x (32 x 32) / 2048 VGMA4 + (VGMA5 - VGMA4) x (32 x 33) / 2048 : VGMA4 + (VGMA5 - VGMA4) x (32 x 63) / 2048 VGMA5 VGMA5 + (VGMA6 - VGMA5) x (50 x 1) / 2400 : VGMA5 + (VGMA6 - VGMA5) x (50 x24) / 2400 VGMA5 + (VGMA6 - VGMA5) x (50 x 25) / 2400 : VGMA5 + (VGMA6 - VGMA5) x (50 x 47) / 2400 VGMA6 VGMA6 + (VGMA7 - VGMA6) x (200 x 1) / 2800 : VGMA6 + (VGMA7 - VGMA6) x (200 x 9) / 2800 : VGMA6 + (VGMA7 - VGMA6) x (200 x 13) / 2800 VGMA7 VGMA8
NOTE: VDD2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5 > VGMA6 > VGMA7 > VGMA8
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 00H 01H : 18H : 1FH 20H 21H : 28H 29H : 3FH 40H 41H : 60H 61H : 7FH 80H 81H : A0H A1H : BFH C0H C1H : D8H D9H : EFH F0H F1H : F9H : FDH FEH FFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 : 1 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 1 1 : 0 1 1 : 1 : 1 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 1 0 1 G/S VL0 VL1 : VL24 : VL31 VL32 VL33 : VL40 VL41 : VL63 VL64 VL65 : VL96 VL97 : VL127 VL128 VL129 : VL160 VL161 : VL191 VL192 VL193 : VL216 VL217 : VL239 VL240 VL241 : VL249 : VL253 VL254 VL255 Output voltage VGMA16 VGMA16 + (VGMA15 - VGMA16) x (218 x 1) / 6976 : VGMA16 + (VGMA15 - VGMA16) x (218 x 24) / 6976 : VGMA16 + (VGMA15 - VGMA16) x (218 x 31) / 6976 VGMA15 VGMA15 + (VGMA14 - VGMA15) x (70 x 1) / 2240 : VGMA15 + (VGMA14 - VGMA15) x (70 x 8) / 2240 VGMA15 + (VGMA14 - VGMA15) x (70 x 9) / 2240 : VGMA15 + (VGMA14 - VGMA15) x (70 x 31) / 2240 VGMA14 VGMA14 + (VGMA13 - VGMA14) x (32 x 1) / 2048 : VGMA14 + (VGMA13 - VGMA14) x (32 x 32) / 2048 VGMA14 + (VGMA13 - VGMA14) x (32 x 33) / 2048 : VGMA14 + (VGMA13 - VGMA14) x (32 x 63) / 2048 VGMA13 VGMA13 + (VGMA12 - VGMA13) x (32 x 1) / 2048 : VGMA13 + (VGMA12 - VGMA13) x (32 x 32) / 2048 VGMA13 + (VGMA12 - VGMA13) x (32 x 33) / 2048 : VGMA13 + (VGMA12 - VGMA13) x (32 x 63) / 2048 VGMA12 VGMA12 + (VGMA11 - VGMA12) x (50 x 1) / 2400 : VGMA12 + (VGMA11 - VGMA12) x (50 x 24) / 2400 VGMA12 + (VGMA11 - VGMA12) x (50 x 25) / 2400 : VGMA12 + (VGM11 - VGMA12) x (50 x 47) / 2400 VGMA11 VGMA11 + (VGMA10 - VGMA11) x (200 x 1) / 2800 : VGMA11 + (VGMA10 - VGMA11) x (200 x 9) / 2800 : VGMA11 + (VGMA10 - VGMA11) x (200 x 13) / 2800 VGMA10 VGMA9
NOTE: VSS2 < VGMA16 < VGMA15 < VGMA14 < VGMA13 < VGMA12 < VGMA11 < VGMA10 < VGMA9
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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Input voltage Output voltage Operating power dissipation Operation temperature Storage temperature Symbol VDD1 VDD2 VGMA1 - 16 Others DIO1, 2 Y1 - Y402 Pd Top Tstg CAUTIONS: If LSIs are stressed beyond those listed above "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 control signal input VDD2 VGMA1 - VGMA16 Turn off power order: VGMA1 - VGMA16 VDD2 control signal input VDD1 Ratings -0.3 to 5.0 -0.3 to 16 -0.3 to VDD2+0.3 -0.3 to VDD1+0.3 -0.3 to VDD1+0.3 -0.3 to VDD2+0.3 300 (1) -20 to 75 -55 to 125 Unit V V V V mW C C
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = -20 to 75 C, VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Gamma corrected voltage Driver part output voltage Maximum clock frequency (Single edge/Double edge) Output load capacitance Symbol VDD1 VDD2
(1)
Min. 2.5 8.0 0.5 VDD2 VSS2 + 0.1 VSS2 + 0.1
Typ. 3.3 12.0 -
Max. 3.6 15.0 VDD2 - 0.1 0.5 VDD2 VDD2 - 0.1 55 / 40 75 / 55
Unit V V V V V MHz pF / PIN
VGMA1 - VGMA8 VGMA9 - VGMA16 Vyo fmax CL
(1)
VDD1 = 2.5 V VDD1 = 3.0 V 2
-
200
NOTE: 1. Relationship between TFT-LCD panel and Pd (Pd CL * (VDD2) * fCLK1)
TFT-LCD panel standard SXGA UXGA & WUXGA
CL = 140pF max. VDD2 = 15 V max. VDD2 = 14 V
CL = 200pF max. VDD2 = 13 V max. VDD2 = 12 V
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
DC CHARACTERISTICS
Table 5. DC Characteristics (Ta = -20 to 75 C, VDD1 = 2.5 to 3.6 V, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V) Parameter High level input voltage Low level input voltage Input leakage current High level output voltage Low level output voltage Resistor Symbol VIH VIL IL VOH VOL R0 R254 IVOH Driver output current IVOL Output voltage deviation Output RMS voltage deviation Output voltage range Logic part dynamic current Driver part dynamic current VO dVrms Vyo IDD1 IDD2
(2)
Condition SHL, CLK2, D00 - D57, CLK1, SELT, DATPOL1, DATPOL2, DEC, POL, DIO1 (DIO2) DIO1 (DIO2), IO = -1.0 mA DIO1 (DIO2), IO = +1.0 mA Refer to Table 1. Resistor Strings VDD2 = 10.0 V, Vx = 3.5 V, Vyo = 9.5 V(1) VDD2 = 10.0 V, Vx = 6.5 V, Vyo = 0.5 V(1) VSS2 + 0.1 V to VDD2 - 1.5 V VDD2 - 1.5 V to VDD2 - 0.1 V Input data: 00H to FFH Input data: 00H to FFH VDD1 = 3.0 V (3) VDD2 = 10 V
(4)
Min. 0.8 VDD1 0 -1 VDD1 - 0.5 Rn x 0.7 1.0 VSS2 + 0.1 -
Typ. -
Max. VDD1 0.2 VDD1 1 0.5 Rn x 1.3
Unit V A V mA mA
-2.0 2.0 7 10 3 4.0 10.0
-1.0 15 20 10 VDD2 - 0.1 7.0
mV
V
mA 15.0
NOTES: 1. Vyo is the output voltage of analog output pins Y1 to Y402. Vx is the voltage applied to analog output pins Y1 to Y402. 2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale. 3. CLK1 period is defined to be 15.6 s at fCLK2 = 54 MHz, DEC = L, data pattern = 10101010 (checkerboard pattern), Ta = 25 C. 4, Yout Load Condition
2k YOUT
4k
4k
20pF
40pF
20pF
VCOM = 0.5 VDD2
2k
4k
4k
Figure 5. Yout Load Condition
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KS0670
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
SINGLE EDGE AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75 C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = L) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time DATPOL-CLK2 setup time DATPOL-CLK2 hold time Start pulse delay time CLK1 setup time Driver output delay time1 Driver output delay time2 CLK1 pulse high period Data invalid period Last data timing CLK1-CLK2 time POL-CLK1 time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP4 tHOLD4 tPLH1 tSETUP3 tPHL1 tPHL2 PWCLK1 tINV tLDT tCLK1-CLK2 tPOL-CLK1 Condition CL = 20 pF PWCLK1 = 1 s, Refer Figure 5. Yout Load Condition CLK1 or CLK2 POL or CLK1 VDD1 = 2.5 to 3.0 V Min. 18 3 3 3 0 3 0 3 0 2 0.5 1 1 8 8 Max. 15 4 8 2 VDD1 = 3.0 to 3.6 V Min. 13 2 2 2 0 2 0 2 0 2 0.5 1 1 6 6 Max. 11 4 8 2 CLK2 period ns ns s CLK2 period ns Unit
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8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
KS0670
DOUBLE EDGE AC CHARACTERISTICS
Table 7. AC Characteristics (Ta = -20 to 75 C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = H) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time DATPOL-CLK2 setup time DATPOL-CLK2 hold time Start pulse delay time CLK1 setup time Driver output delay time1 Driver output delay time2 CLK1 pulse high period Data invalid period Last data timing CLK1-CLK2 time POL-CLK1 time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP4 tHOLD4 tPLH1 tSETUP3 tPHL1 tPHL2 PWCLK1 tINV tLDT tCLK1-CLK2 tPOL-CLK1 CLK1 or CLK2 POL or CLK1 Condition CL = 20 pF PWCLK1 = 1 s , Figure 5. Yout Load Condition VDD1 = 2.5 to 3.0 V Min. 25 4 4 4 0 4 0 4 0 1 0.5 0.5 1 8 8 Max. 15 4 8 2 VDD1 = 3.0 to 3.6 V Min. 18 3 3 3 0 3 0 3 0 1 0.5 0.5 1 6 6 Max. 15 4 8 2 CLK2 period ns ns s CLK2 period ns Unit
17
18
PWCLK tINV 1st tHOLD1 VIH VIL LAST-1 LAST PWCLK(L) PWCLK(H) INVALID DATA tSETUP4 tHOLD4 tSETUP1 1st DATA tSETUP2 tHOLD2 tPLH1 tSETUP3 PWCLK1 tPHL1 Target output voltage 90% Target output voltage tPHL2 HI-Z tLDT tCLK1-CLK2 0.5VDD1 LAST DATA tPOL-CLK1 INVALID DATA
KS0670
CLK2
DXX
DATPOL1 DATPOL2
DIO1 input (DIO2 input)
DIO2 output (DIO1 output)
CLK1
SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1)
Figure 6. Waveforms, DEC = L
Y(1:402)
CLK2
CLK1
DXX
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
POL
PWCLK PWCLK(L) LAST-2 LAST-1 LAST tINV 1st tHOLD1 2nd PWCLK(H) VIH VIL
CLK2
DXX
INVALID DATA tSETUP4 tHOLD4
tSETUP1 1st DATA
DATPOL1 DATPOL2
tSETUP2 tHOLD2
DIO1 input (DIO2 input)
tPLH1
DIO2 output (DIO1 output)
tSETUP3 PWCLK1 tPHL1 Target output voltage 90%
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
CLK1
Y(1:402) tPHL2 HI-Z
DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1)
Figure 7. Waveforms, DEC = H
tLDT tCLK1-CLK2 0.5VDD1 tSETUP1 LAST DATA tPOL-CLK1 tHOLD1
Target output voltage
CLK2
CLK1
DXX
INVALID DATA
POL
KS0670
19
20
0.5VDD1 1/2CLK2 (DEC = H ) 2CLK2(Min.) tLDT N-1th DATA INVALID DATA blanking time = Min. 4CLK2 Last data First data in the next line Nth DATA 1st DATA 2nd DATA HI-Z HI-Z HI-Z HI-Z VGMA1 - VGMA8 VGMA9 - VGMA16 VGMA1 - VGMA8 VGMA9 - VGMA16 Charge sharing period VGMA1- VGMA8 VGMA9 - VGMA16
KS0670
CLK2
DIO1 input (DIO2 input)
CLK1
DXX
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD
Figure 8. Waveforms
CLK1
POL
Y2N-1:odd number output
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Y2N:even number output

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