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MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY DESCRIPTION
The MITSUBISHI Mobile FLASH M5M29GB/T160BVP are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. The M5M29GB/T160BVP are fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in in 48pin TSOP(I) .
FEATURES
Organization
.................................1048,576 word x 16bit .................................2,097,152 word x 8 bit
Boot Block M5M29GB160BVP ........................ Bottom Boot M5M29GT160BVP ........................ Top Boot Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) and Bank(II) Package 48-Lead, 12mm x 20mm TSOP (type-I)
............................. VCC = 2.7~3.6V Supply voltage ................................
Access time
.............................. 80ns (Vcc=3.3V+/-0.3V)
90ns (Vcc=2.7~3.6V)
Power Dissipation ................................. 54 mW (Max. at 5MHz) Read (After Automatic Power saving) .......... 0.33mW (typ.) Program/Erase .................................126 mW (Max.) ................................. 0.33mW (typ.) Standby Deep power down mode ....................... 0.33mW (typ.) Auto program for Bank(I) ................................. 4ms (typ.) Program Time Program Unit .........................1word/1byte (Byte Program) (Page Program) ......................... 128word/256byte Auto program for Bank(II) ................................. 4ms (typ.) Program Time ................................. 128word/256byte Program Unit Auto Erase ................................. 40 ms (typ.) Erase time Erase Unit Bank(I) Boot Block ..................... 16Kword/32Kbyte x 1 .............. Parameter Block 16Kword/32Kbyte x 7 ...................... 32Kword/64Kbyte x 28 Bank(II) Main Block Program/Erase cycles
APPLICATION
Code Strage Digital Cellular Phone Telecommunication Mobile Computing Machine PDA (Personal Digital Assistance) Car Navigation System Video Game Machine
.........................................
100Kcycles
PIN CONFIGURATION (TOP VIEW)
160BVP A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RP# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38
160BVP A16 BYTE# GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 NC : NO CONNECTION
M5M29GB/T 160BVP
37 36 35 34 33 32 31 30 29 28 27 26 25
Outline 48pin TSOP type-I (12 X 20mm) VP(Normal bend)
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Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
ADDRESS INPUTS
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
CE# OE# WE# WP# RP# BYTE# RY/BY#
128 WORD PAGE BUFFER Main Block 32KW
VCC (3.3V)
28
Bank(II)
GND (0V)
Main Block
Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block
X-DECODER Bank(I)
32KW
16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW
Y-DECODER
Y-GATE / SENSE AMP.
STATUS / ID REGISTER
MULTIPLEXER
CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT BYTE ENABLE INPUT READY/BUSY OUTPUT
CUI
WSM INPUT/OUTPUT BUFFERS
DQ15/A-1DQ14DQ13DQ12
DQ3DQ2DQ1DQ0
DATA INPUTS/OUTPUTS
M5M29GB/T160BVP (8/16 bit version)
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Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY FUNCTION
The M5M29GB/T160BVP includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and byte/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption. Read The M5M29GB/T160BVP has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the M5M29GB/T160BVP automatically resets to read array mode. In the read array mode, low level input to CE# and OE#, high level input to WE# and RP#, and address signals to the address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode) output the data of the addressed location to the data input/output (D7-D0:Byte Mode, D15-D0:Word Mode). Write Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing WE# to low level, while CE# is at low level and OE# is at high level. Address and data are latched on the earlier rising edge of WE# and CE#. Standard micro-processor write timings are used. Alternating Background Operation (BGO) The M5M29GB/T160BVP allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Read array operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation. Output Disable When OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. Deep Power-Down When RP# is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, RP# low will abort either operation. Memory array data of the block being altered become invalid. Automatic Power-Saving (APS) The Automatic Power-Saving minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or CE# isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. While in this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed.
3
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep powerdown, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically. Read Device Identifier Command (90H) It can normally read device identifier codes when Read Device Identifier Code Command(90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 00000H and 00001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of OE# or CE#. So CE# or OE# must be toggled every status read. Clear Status Register Command (50H) The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. C)Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H) Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 256byte/128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programing the data on the page buffer is cleared automatically. This command is valid for only Bank(I) alike Word/Byte Program. Clear Page Buffer Command (55H) Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes.
DATA PROTECTION Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Program Commands A)Word/Byte Program (40H) Word/Byte program is executed by a two-command sequence. The Word/Byte Program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. The Word/Byte Program Command is Valid for only Bank(I). B)Page Program for Data Blocks (41H) Page Program for Bank(I) and Bank(II) allows fast programming of 128words/256bytes of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 257th cycle (Byte Mode)129th cycle (Word Mode), write data must be serially inputted. Address A6-A0,A-1 (Byte Mode) / A6-A0 (Word Mode) have to be incremented from 00H to 7FH/FFH. After completion of data loading, the WSM controls the program pulse application and verify operation. The M5M29GB/T160BVP provides selectable block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the M5M29GB/T160BVP has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set to "0", when WP# is low. When WP# is high, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for details. Power Supply Voltage When the power supply voltage (Vcc) is less than VLKO, Low VCC Lock-Out voltage, the device is set to the Read-only mode. Regarding DC electrical characteristics of VLKO, see P.10 A delay time of 2 us is required before any device operation is initiated. The delay time is measured from the time Vcc reaches Vccmin (2.7V). During power up, RP#=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device. MEMORY ORGANIZATION The M5M29GB/T160BVP has one 32Kbyte boot block, seven 32Kbyte parameter blocks, for Bank(I) and twenty-eight 64Kbyte main blocks for Bank(II). A block is erased independently of other blocks in the array.
4
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Mitsubishi 16M Flash Memory Type name
M 5 M 29G T 160B VP
Operating Voltage : 29G : 2.7 - 3.6V Standard / BGO Type 29W : 1.65 - 2.2V Standard / BGO Type Boot Block : T : Top Boot B : Bottom Boot Density/Write Protect/ Word Organizetion: 160B : 16M WP#, x8/x16 161B : 16M WP1# & WP2#, x16
Package : VP : 48pin TSOP(I) 12mm x 20mm (Nomal Pinout) WG: CSP Ball Pitch 0.75mm,6x8 array, 7mm x 8.5mm
5
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
MEMORY ORGANIZATION
x8 ( Bytemode) 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-1FFFFFH 100000H-10FFFFH F0000H-FFFFFH E0000H-EFFFFH D0000H-DFFFFH C0000H-CFFFFH B0000H-BFFFFH A0000H-AFFFFH 90000H-9FFFFH 80000H-8FFFFH 70000H-7FFFFH 60000H-6FFFFH 50000H-5FFFFH 40000H-4FFFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH A19-A-1 (Byte Mode) x16 ( Wordmode) F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 1C000H-1FFFFH 18000H-1BFFFH 14000H-17FFFH 10000H-13FFFH 0C000H-0FFFFH 08000H-0BFFFH 04000H-07FFFH 00000H-03FFFH A19-A0 (Word Mode) x8 ( Bytemode) x16 ( Wordmode) FC000H-FFFFFH
32Kword MAIN BLOCK 35 32Kword MAIN BLOCK 34 32Kword MAIN BLOCK 33 32Kword MAIN BLOCK 32 32Kword MAIN BLOCK 31 32Kword MAIN BLOCK 30 32Kword MAIN BLOCK 29 32Kword MAIN BLOCK 28 32Kword MAIN BLOCK 27 32Kword MAIN BLOCK 26 32Kword MAIN BLOCK 25 32Kword MAIN BLOCK 24 32Kword MAIN BLOCK 23 BANK(II) BANK(I) 32Kword MAIN BLOCK 22 32Kword MAIN BLOCK 21 32Kword MAIN BLOCK 20 32Kword MAIN BLOCK 19 32Kword MAIN BLOCK 18 32Kword MAIN BLOCK 17 32Kword MAIN BLOCK 16 32Kword MAIN BLOCK 15 32Kword MAIN BLOCK 14 32Kword MAIN BLOCK 13 32Kword MAIN BLOCK 12 32Kword MAIN BLOCK 11 32Kword MAIN BLOCK 10 32Kword MAIN BLOCK 9 32Kword MAIN BLOCK 8
16Kword PARAMETER BLOCK 7 16Kword PARAMETER BLOCK 6 16Kword PARAMETER BLOCK 5 16Kword PARAMETER BLOCK 4 16Kword PARAMETER BLOCK 3 16Kword PARAMETER BLOCK 2 16Kword PARAMETER BLOCK 1
1F8000H-1FFFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH F0000H-FFFFFH E0000H-EFFFFH D0000H-DFFFFH C0000H-CFFFFH B0000H-BFFFFH A0000H-AFFFFH 90000H-9FFFFH 80000H-8FFFFH 70000H-7FFFFH 60000H-6FFFFH 50000H-5FFFFH 40000H-4FFFFH 30000H-3FFFFH 20000H-2FFFFH 10000H-1FFFFH 00000H-0FFFFH A19-A-1 (Byte Mode)
16Kword BOOT BLOCK 35
F8000H-FBFFFH 16Kword PARAMETER BLOCK 34 F4000H-F7FFFH 16Kword PARAMETER BLOCK 33
BANK(I)
F0000H-F3FFFH 16Kword PARAMETER BLOCK 32 EC000H-EFFFFH 16Kword PARAMETER BLOCK 31 E8000H-EBFFFH 16Kword PARAMETER BLOCK 30 E4000H-E7FFFH 16Kword PARAMETER BLOCK 29 E0000H-E3FFFH 16Kword PARAMETER BLOCK 28 D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH A19-A0 (Word Mode)
32Kword MAIN BLOCK 27 32Kword MAIN BLOCK 26 32Kword MAIN BLOCK 25 32Kword MAIN BLOCK 24 32Kword MAIN BLOCK 23 32Kword MAIN BLOCK 22 32Kword MAIN BLOCK 21 32Kword MAIN BLOCK 20 32Kword MAIN BLOCK 19 32Kword MAIN BLOCK 18 32Kword MAIN BLOCK 17 32Kword MAIN BLOCK 16 BANK(II) 32Kword MAIN BLOCK 15 32Kword MAIN BLOCK 14 32Kword MAIN BLOCK 13 32Kword MAIN BLOCK 12 32Kword MAIN BLOCK 11 32Kword MAIN BLOCK 10 32Kword MAIN BLOCK 9 32Kword MAIN BLOCK 8 32Kword MAIN BLOCK 7 32Kword MAIN BLOCK 6 32Kword MAIN BLOCK 5 32Kword MAIN BLOCK 4 32Kword MAIN BLOCK 3 32Kword MAIN BLOCK 2 32Kword MAIN BLOCK 1 32Kword MAIN BLOCK 0
16Kword BOOT BLOCK 0
M5M29GB160BVP Memory Map
M5M29GT160BVP Memory Map
6
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY BUS OPERATIONS Bus Operations for Word-Wide Mode
Pins
Mode Read
CE# VIL VIL VIL VIL VIL VIH VIL VIL VIL X
OE# VIL VIL VIL VIL VIH X 2) VIH VIH VIH X
WE# VIH VIH VIH VIH VIH X VIL VIL VIL X
RP# VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL
DQ0-15 Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z
RY/BY# VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z)
Array Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down
Bus Operations for Byte-Wide Mode
Mode Pins CE# VIL VIL VIL VIL VIL VIH VIL VIL VIL X OE# VIL VIL VIL VIL VIH X 2) VIH VIH VIH X WE# VIH VIH VIH VIH VIH X VIL VIL VIL X RP# VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL DQ0-7 Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z RY/BY# VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z)
Array Read Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down
1) X at RY/BY# is VOL or VOH(Hi-Z). *The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition. 2) X can be VIH or VIL for control pins.
7
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITION Command List
1st bus cycle Command Mode Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Byte/Word Program 5) Page Program 7) Single Data Load to Page Buffer 5) Page Buffer to Flash 5) Block Erase / Confirm Suspend Resume Read Lock Bit Status Lock Bit Program / Confirm Erase All Unlocked Blocks Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address X X Bank3) X X Bank(I) 5) Bank Bank(I) 5) Bank(I) 5) Bank Bank Bank X Bank X Data
(DQ7-0) 1) (DQ15-0)
2nd bus cycle Data Mode Address IA 2) Bank X WA 6) WA0 7) WA WA 8) BA 9)
(DQ7-0) (DQ15-0)
3rd ~257th bus cycles (Byte Mode) 3rd ~129th bus cycles (Word Mode)
Data Mode Address
(DQ7-0) (DQ15-0)
FFH 90H 70H 50H 55H 40H 41H 74H 0EH 20H B0H D0H 71H 77H A7H
Read Read Write Write Write Write Write Write
ID 2) SRD4) D0H 1) WD 6) WD0 7) WD D0H 1) D0H 1)
Write
WAn 7)
WDn 7)
Read Write Write
BA BA X
DQ6 10) D0H 1) D0H 1)
1) In the word-wide version(Byte#=H), upper byte data (DQ8-DQ15) is ignored. 2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code 3) Bank = Bank Address (Bank(I) or Bank(II)) : A19-A17. 4) SRD = Status Register Data 5) Byte/Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I). 6) WA = Write Address,WD = Write Data 7) WA0,WAn=Write Address, WD0,WDn=Write Data. Byte Mode : Write Address and Write Data must be provided sequentially from 00H to FFH for A6-A0,A-1. Page size is 256Byte (256byte x 8bit), and also A19-A7(Block Address, Page Address) must be valid. Word Mode : Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit). and also A19-A7(Block Address, Page Address) must be valid. 8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid. 9) BA = Block Address : BA = Block Address : A19-A14(Bank1) A19-A15(Bank2) 10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
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Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK LOCKING
160B RP# VIL VIH WP# X VIL VIH Lock Bit (Internally) X 0 1 X Write Protection Provided BANK(I) BANK(II) Note Lock Bit Boot Parameter Data Locked Locked Locked Locked Deep Power Down Mode Locked Locked Locked Locked Locked Locked Unlocked Unlocked Unlocked Unlocked Unlocked Unlocked All Blocks Unlocked
1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H). WP# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0). 2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and 00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode to array read mode.
STATUS REGISTER
Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3) (DQ2) (DQ1) (DQ0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Definition "1" Ready Suspended Error Error Error "0" Busy Operation in Progress / Completed Successful Successful Successful -
*The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition. *DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
9
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY DEVICE IDENTIFIER CODE
Code Manufacturer Code Device Code (-T160BVP) Device Code (-B160BVP) Pins A0 VIL VIH VIH DQ7 0 1 1 DQ6 0 0 0 DQ5 0 1 1 DQ4 1 0 0 DQ3 1 0 0 DQ2 1 0 0 DQ1 0 0 0 DQ0 0 0 1 Hex. Data 1CH A0H A1H
In the word-wide mode, the upper data(D15-8) is "0".
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI1 Ta Tbs Tstg I OUT Parameter Vcc voltage All input or output voltage 1) Ambient temperature Temperature under bias Storage temperature Output short circuit current Conditions
With respect to Ground
Min -0.2 -0.6 -40 -50 -65
Max 4.6 4.6 85 95 125 100
Unit V V C C C mA
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.
CAPACITANCE
Symbol CIN COUT Parameter Input capacitance (Address, Control Pins) Output capacitance Test conditions Ta = 25C, f = 1MHz, Vin = Vout = 0V Min Limits Typ Max 8 12 Unit pF pF
DC ELECTRICAL CHARACTERISTICS (Ta = -40~ 85C, Vcc = 2.7V ~ 3.6V, unless otherwise noted)
Symbol ILI ILO ISB1 ISB2 ISB3 ISB4 ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH1 VOH2 VLKO Parameter Input leakage current Output leakage current VCC standby current Test conditions 0VVINVCC 0VVOUTVCC VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH VCC = 3.6V, VIN=GND or VCC, CE# = RP# = WP#= VCC0.3V VCC = 3.6V, VIN=VIL/VIH, RP# = VIL VCC = 3.6V, VIN=GND or VCC, RP# =GND0.3V VCC = 3.6V, VIN=VIL/VIH, CE# = VIL, 5MHz RP#=OE#=VIH, IOUT = 0mA 1MHz VCC = 3.6V,VIN=VIL/VIH, CE# =WE#= VIL, RP#=OE#=VIH VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH - 0.5 2.0 IOL = 4.0mA IOH = -2.0mA IOH = -100mA 0.85Vcc
Vcc-0.4
Min
Limits Typ1)
50 0.1 5 0.1 8 2
Max 1 10 200 5 15 5 15 4 15 35 35 200 0.8
Vcc+0.5
Unit mA mA mA mA mA mA mA mA mA mA mA V V V V V V
VCC deep powerdown current VCC read current for Word or Byte VCC Write current for Word or Byte VCC program current VCC erase current VCC suspend current Input low voltage Input high voltage Output low voltage Output high voltage Low VCC Lock-Out voltage 2)
0.45
1.5
2.2
All currents are in RMS unless otherwise noted. 1) Typical values at Vcc=3.3V, Ta=25C 2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO. If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
10
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85C) Read-Only Mode
Limits
Symbol
Parameter
Speed Item: -80 Vcc=3.3V+/-0.3V Min Typ Max 80 80 80 30 0 25 0 25 150 80 25 0 5 5 10 150 0 10 150 0 5 5 Vcc=2.7~3.6V Min Typ 90 Max 90 90 30 0 25 0 25 150 90 25
Unit
tRC ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ
tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ
Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low-Z Chip enable high to output in high Z Output enable to output in low-Z Output enable high to output in high Z RP# low to output high-Z
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ta(BYTE) tFL/HQV BYTE# access time tBHZ tFLQZ BYTE# low to output high-Z tOH tBCD tBAD tOEH tPS tOH Output hold from CE#, OE#, addresses tELFL/H F-CE# low to BYTE# high or low tAVFL/H Address to BYTE# high or low tWHGL tPHEL OE# hold from WE# high RP# recovery to CE# low
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85C) Write Mode (WE# control)
Symbol
Parameter Min 80 50 0 50 0 10 30 0 0 60 30 50 80 0 80 0 4 40 150
Limits Speed Item: -80 Vcc=3.3V+/-0.3V Typ Max Min 90 50 0 50 0 10 30 0 0 60 30 50 90 0 90 0 80 600 90 150 4 40 80 600 90 Vcc=2.7~3.6V Typ Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns
Write cycle time Address set-up time Address hold time Data set-up time Data hold time OE# hold from WE# high Latency between Read and Write FFH or 71H tRE tCS Chip enable set-up time tCH Chip enable hold time tWP Write pulse width tWPH Write pulse width high tBS Byte enable high or low set-up time tBH Byte enable high or low hold time tGHWL tGHWL OE# hold to WE# Low tBLS tPHHWH Block Lock set-up to write enable high tBLH tQVPH Block Lockhold from valid SRD tDAP tWHRH1 Duration of auto-program operation tDAE tWHRH2 Duration of auto-block erase operation tWHRL tWHRL Write enable high to F-RY/BY# low tPS tPHWL RP# high recovery to write enable low
tWC tAS tAH tDS tDH tOEH
tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH tWLWH tWHWL tFL/HWH tWHFL/H
Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25C
11
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85C) Write Mode (CE# control)
Symbol
Parameter
Limits Speed Item: -80 Vcc=3.3V+/-0.3V Min Typ Max 80 50 0 50 0 10 30 0 0 60 30 50 80 80 80 0 4 40 150 80 600 90 150 Vcc=2.7~3.6V Min Typ 90 50 0 50 0 10 30 0 0 60 30 50 90 90 90 0 4 40 80 600 90 Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns
tWC tAS tAH tDS tDH tOEH tRE tWS tWH tCEP
Write enable hold time CE# pulse width tCEPH tEHEL CE# pulse width high tBS tFL/HWH Byte enable high or low set-up time tBH tWHFL/H Byte enable high or low hold time tGHEL tGHEL OE# hold to CE# Low tBLS tPHHEH Block Lock set-up to write enable high tBLH tQVPH Block Lockhold from valid SRD tDAP tEHRH1 Duration of auto-program operation tDAE tEHRH2 Duration of auto-block erase operation tEHRL tEHRL F-CE# high to F-RY/BY# low tPS tPHWL RP# high recovery to write enable low
tAVAV tAVWH tEHAX tDVWH tEHDX tEHGL tWLEL tEHWH tELEH
Write cycle time Address set-up time Address hold time Data set-up time Data hold time OE# hold from CE# high Latency between Read and Write FFH or 71H Write enable set-up time
Read timing parameters during command write operation mode are the same as during read-only operation mode. Typical values at Vcc=3.3V, Ta=25C
Erase and Program Performance
Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Min Typ 40 1.0 4 Max 600 1.8 80 Unit ms sec ms
Program Suspend Latency / Erase Suspend Time
Parameter Program Suspend Latency Erase Suspend Time
Please see page 19.
Min
Typ
Max 15 15
Unit ms ms
Vcc Power Up / Down Timing
Symbol tVCS
Please see page 12. During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during power up/down. The delay time of min.2msec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down. By holding RP# VIL, the contents of memory is protected during Vcc power up/down. During power up, RP# must be held VIL for min.2ms from the time Vcc reaches Vccmin. During power down, RP# must be held VIL until Vcc reaches GND. RP# doesn't have latch mode ,therefore RP# must be held VIH during read operation or erase/program operation.
Parameter RP# =VIH set-up time from Vccmin
Min 2
Typ
Max
Unit ms
12
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit
VCC
3.3V GND tVCS VIH VIL
RP#
CE#
VIH VIL tPS tPS
WE#
VIH VIL
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
ADDRESSES
VIH VIL
ADDRESS VALID
TEST CONDITIONS FOR AC CHARACTERISTICS Input voltage : VIL = 0V, VIH = 3.0V Input rise and fall times : 5ns Reference voltage at timing measurement : 1.5V Output load : 1TTL gate + CL(30pF) or
tRC ta (AD) ta (CE) tDF(CE)
CE#
VIH VIL
OE#
VIH VIL tOEH ta (OE) tOLZ HIGH-Z tPS tCLZ tDF(OE) tOH HIGH-Z
1.3V 1N914 3.3kW DUT CL =30pF
WE#
VIH VIL
DATA
VOH VOL
OUTPUT VALID
RP#
VIH VIL
tPHZ
13
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
ADDRESSES
VIH VIL
ADDRESS VALID
tRC ta (AD) ta (CE) tRE ta (OE)
FFH or 71H
CE#
VIH VIL
tDF(CE)
OE#
VIH VIL tDF(OE) tOH
HIGH-Z
WE#
VIH VIL tOLZ tCLZ
OUTPUT VALID
DATA
VOH HIGH-Z VOL
Valid
tPS RP# VIH VIL
tPHZ
In the case of use CE# is Low fixed, it is allowed to define a timming specification of tRE from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE). (This is only for FFH,71H program and read)
BYTE AC WAVEFORMS FOR READ OPERATION
ADDRESSES VIH (A0 - A19,A-1*) VIL VIH VIL ta(CE) OE# VIH VIL ta(OE) ta(BYTE) tOLZ tCLZ tBCD HIGH-Z tBAD
OUTPUT VALID VALID VALID ADDRESS VALID ADDRESS VALID
ta(AD) CE#
tDF(CE)
tDF(OE) tBAD ta(BYTE)
BYTE#
VIH VIL
tOH
DATA (D0 - D7)
VIH VIL
tBHZ VIH HIGH-Z
VALID
ta(AD)
DATA (D8 - D14) VIL
D15 / A-1
VIH VIL
A-1
D15
A-1
When BYTE#=VIH, CE#=OE#=VIL , D15/A-1 is output status. At this time, input signal must not be applied.
14
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)
VIH A19~A7 VIL
BYTE#=VIL (A6~A-1) BYTE#=VIH (A6 ~A0) The other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID 00H 00H
VALID
ADDRESS VALID 01H~FEH FFH 7FH
BANK ADDRESS VALID
VIH VIL tWC VIH VIL tCS
VALID
01H~7EH
tAS tCH tWPH
tAH
ta(CE)
CE# OE#
ta(CE) ta(OE)
VIH VIL tOEH tGHWL ta(OE) tOEH tDAP
WE#
VIH VIL tWP
41H
DATA
VIH VIL
tDS
DIN
tDH
DOUT DIN DIN SRD FFH
tWHRL tBH
RY/BY# BYTE# RP#
VOH VOL VIH VIL tPS VIH VIL VIH VIL tBLS tBLH tBS
WP#
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (CE# control)
VIH A19~A7 VIL
BYTE#=VIL (A6~A-1) BYTE#=VIH (A6 ~A0) The other bank address
BANK ADDRESS VALID
PROGRAM
READ STATUS WRITE READ REGISTER ARRAY COMMAND
VALID 00H 00H
VALID
ADDRESS VALID 01H~FEH FFH 7FH
BANK ADDRESS VALID
VIH VIL tWC VIH VIL VIH VIL tCEP tWS tWH
VALID
01H~7EH
tAS tCEPH
tAH ta(CE) ta(OE) tOEH tGHEL tOEH tDAP tDH
DIN DOUT DIN DIN
CE# OE#
ta(CE) ta(OE)
WE#
VIH VIL tDS
41H
DATA
VIH VIL
SRD
FFH
tEHRL
RY/BY#
VOH VOL VIH tBS tBH
BYTE#
VIL VIH VIL VIH
tPS
RP#
tBLS
tBLH
WP#
VIL
15
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (WE# control) (to only BANK(I))
PROGRAM
BANK ADDRESS VALID
VIH
ADDRESSES
READ STATUS REGISTER
WRITE READ ARRAY COMMAND
VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL RY/BY# VIH VIL
ADDRESS VALID
BANK(I) ADDRESS VALID
tWC tCS
tAS
tAH
ta(CE) ta(OE) tOEH
tCH tWP tWPH
tDS
40H DIN SRD FFH
tDH tWHRL
tBS
VIH BYTE# VIL VIH RP# VIL VIH VIL
tPS tBLS
tBH
tDAP tBLH
WP#
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (CE# control)
PROGRAM
BANK ADDRESS VALID
(to only BANK(I))
WRITE READ ARRAY COMMAND
VIH
ADDRESSES
READ STATUS REGISTER
VIL VIH VIL
ADDRESS VALID
BANK(I) ADDRESS VALID
tWC
tAS
tAH
ta(CE) ta(OE)
CE#
OE#
VIH VIL
tCEP tWS tWH tDS
40H DIN
tOEH
WE#
VIH VIL VIH
DATA VIL VIH RY/BY# VIL VIH BYTE# VIL VIH RP# VIL VIH WP# VIL
SRD
FFH
tDH tEHRL tBS tPS tBLS tBH tDAP tBLH
16
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)
VIH
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
VIL VIH CE# VIL tCS VIH OE# VIL VIH WE# VIL
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
tWC
tAS
tAH
ta(CE)
tCH tOEH tDAE tDH
D0H
ta(OE)
tWPH
tWP VIH DATA
20H
tDS
SRD
FFH
VIL VOH VOL VIH tBS
tWHRL
RY/BY#
tBH
BYTE#
VIL tPS
RP#
VIH VIL tBLS tBLH
WP#
VIH VIL
AC WAVEFORMS FOR ERASE OPERATIONS (CE# control)
VIH
ADDRESSES
ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
VIL VIH CE# VIL
BANK ADDRESS VALID
ADDRESS VALID
BANK ADDRESS VALID
tWC
tAS
tAH
ta(CE)
tCEP VIH OE# VIL tWS VIH WE# VIL VIH DATA
20H
tCEPH tOEH
ta(OE)
tWH tDS
D0H
tDAE tDH
SRD FFH
VIL VOH VOL VIH tBS
tEHRL
RY/BY#
tBH
BYTE#
VIL tPS
RP#
VIH VIL VIH tBLS tBLH
WP#
VIL
17
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address PROGRAM DATA TO ONE BANK
A19~A7
VIH VIL
ARRAY READ FROM THE OTHER BANK WITH BGO
BANK ADDRESS VALID
ADDRESS VALID 00H 00H 01H~FEH 01H~7EH FFH 7FH
VALID
VALID
BYTE#=VIL (A6~A-1) VIH BYTE#=VIH (A6 ~A0) VIL
VALID
VALID
tWC tCS
tAS tCH tWP tWPH
CE#
VIH VIL
tAH
ta(CE) ta(OE) tOEH
OE#
VIH VIL
WE#
VIH VIL VIH
tDS
41H DIN DIN DIN SRD DOUT DOUT
DATA VIL VIH RY/BY# VIL
tDH
tWHRL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (CE# control)
Change Bank Address PROGRAM DATA TO ONE BANK
A19~A7
VIH VIL
ARRAY READ FROM THE OTHER BANK WITH BGO
BANK ADDRESS VALID
ADDRESS VALID 00H 00H 01H~FEH 01H~7EH FFH 7FH
VALID
VALID
BYTE#=VIL (A6~A-1) VIH BYTE#=VIH (A6 ~A0) VIL
VALID
VALID
tWC
tAS tCEPH
CE#
VIH VIL
tAH
ta(CE) ta(OE) tOEH
OE#
VIH VIL
tCEP tWS
WE#
VIH VIL VIH
tCH tDS
41H DIN DIN DIN SRD DOUT DOUT
DATA VIL VIH RY/BY# VIL
tDH
tEHRL
18
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address PROGRAM DATA TO BANK(I)
BANK ADDRESS VALID
VIH A19~A7 VIL
BYTE#=VIL VIH (A6~A-1) BYTE#=VIH VIL (A6 ~A0)
READ STATUS REGISTER
ARRAY READ FROM BANK(II) WITH BGO
ADDRESS VALID
VALID
VALID
VALID
VALID
VALID
tWC tCS
tAS tCH tWP tWPH
tAH
CE#
VIH VIL
ta(CE) ta(OE)
OE#
VIH VIL
tOEH
WE#
VIH VIL VIH
tDS
40H DIN SRD DOUT DOUT
DATA VIL VIH RY/BY# VIL
tDH tWHRL
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (CE# control)
PROGRAM DATA TO BANK(I)
BANK ADDRESS VALID
A19~A7
VIH VIL
READ STATUS REGISTER
Change Bank Address ARRAY READ FROM BANK(II) WITH BGO
ADDRESS VALID
VALID
VALID
BYTE#=VIL VIH (A6~A-1) BYTE#=VIH VIL (A6 ~A0)
VALID
VALID
VALID
tWC
tAS tCEPH
CE#
VIH VIL
ta(CE) ta(OE) tOEH
OE#
VIH VIL
tCEP tWS
WE#
VIH VIL
tCH tDS
40H DIN SRD DOUT DOUT
DATA
VIH VIL VIH
tDH tEHRL
RY/BY# VIL
19
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control)
Change Bank Address BLOCK ERASE IN ONE BANK
BANK ADDRESS VALID
VIH ADDRESSES VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH RY/BY# VIL
READ STATUS REGISTER
ARRAY READ FROM THE OTHER BANK WITH BGO
ADDRESS VALID
VALID
VALID
tWC tCS
tAS tCH tWP tWPH tOEH
tAH
ta(CE) ta(OE)
tDS
20H D0H SRD DOUT DOUT
tDH tWHRL
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (CE# control)
Change Bank Address BLOCK ERASE IN ONE BANK
BANK ADDRESS VALID
VIH ADDRESSES VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL VIH DATA VIL VIH RY/BY# VIL
READ STATUS REGISTER
READ DATA FROM THE OTHER BANK WITH BGO
ADDRESS VALID
VALID
VALID
tWC
tAS tCEPH
tAH
ta(CE) ta(OE)
tCEP tWS
tOEH tCH tDS
20H D0H SRD DOUT DOUT
tDH tEHRL
20
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR SUSPEND OPERATION (WE# control)
VIH
ADDRESSES
READ STATUS REGISTER
VIL VIH CE# VIL
BANK ADDRESS VALID
BANK ADDRESS VALID
tAS
tAH
ta(CE)
tCS VIH OE# VIL VIH WE# VIL tWP VIH DATA
B0H
tCH tOEH Program Suspend Latency
ta(OE)
S.R.6,7=1
VALID SRD
VIL VOH VOL VIH VIL VIH tBLS tBLH
RY/BY#
RP#
WP#
VIL
AC WAVEFORMS FOR SUSPEND OPERATION (CE# control)
VIH
ADDRESSES
READ STATUS REGISTER
VIL VIH CE# VIL VIH OE# VIL VIH WE# VIL VIH DATA
BANK ADDRESS VALID
BANK ADDRESS VALID
tAS tCEP
tAH
ta(CE)
ta(OE) tOEH Program Suspend Latency tWS tWH S.R.6,7=1
B0H VALID SRD
VIL VOH
RY/BY#
VOL VIH VIL VIH tBLS tBLH
RP#
WP#
VIL
21
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY FULL STATUS CHECK PROCEDURE
STATUS REGISTER READ
LOCK BIT PROGRAM FLOW CHART
START
SR.4 =1 and SR.5 =1 ? NO
WRITE 77H YES COMMAND SEQUENCE ERROR WRITE D0H BLOCK ADDRESS
SR.5 = 0 ? NO YES
BLOCK ERASE ERROR SR.7 = 1 ? NO YES
SR.4 = 0 ? NO YES
PROGRAM ERROR (PAGE, LOCK BIT) SR.4 = 0 ? NO YES
LOCK BIT PROGRAM FAILED
SR.3 = 0 ? NO YES SUCCESSFUL (BLOCK ERASE, PROGRAM)
PROGRAM ERROR (BLOCK)
LOCK BIT PROGRAM SUCCESSFUL
BYTE PROGRAM FLOW CHART
START
PAGE PROGRAM FLOW CHART
START
WRITE 40H WRITE 41H
WRITE ADDRESS , DATA
n=0
STATUS REGISTER READ
WRITE ADDRESS n, DATA n
n = n+1
SR.7 = 1 ?
NO
WRITE B0H ?
NO
n = FFH ? or n = 7FH ? YES
NO
YES
YES
STATUS REGISTER READ
FULL STATUS CHECK IF DESIRED
SUSPEND LOOP WRITE D0H
YES SR.7 = 1 ? NO WRITE B0H ? NO
PAGE PROGRAM COMPLETED
* Byte program is admitted to only BANK(I).
YES
YES
FULL STATUS CHECK IF DESIRED
SUSPEND LOOP WRITE D0H
YES
PAGE PROGRAM COMPLETED
22
Sep 1999. Rev2.0
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY CLEAR PAGE BUFFER
START
SUSPEND / RESUME FLOW CHART
START
WRITE B0H WRITE 55H STATUS REGISTER READ WRITE D0H SR.7 = 1? NO PAGE BUFFER CLEAR COMPLETED YES
SUSPEND
SR.6 =1?
SINGLE DATA LOAD TO PAGE BUFFER
YES START WRITE FFH
NO
PROGRAM / ERASE COMPLETED
WRITE 74H
READ ARRAY DATA
WRITE ADDRESS , DATA
DONE READING ? YES
NO
DONE LOADING?
NO
WRITE D0H
RESUME
YES SINGLE DATA LOAD TO PAGE BUFFER COMPLETED
OPERATION RESUMED
* The bank address is required when writing this command. Also, there is no need to suspend the erase or program operation when reading data from the other bank. Please use BGO function.
PAGE BUFFER TO FLASH
START
BLOCK ERASE FLOW CHART
START
WRITE 20H WRITE 0EH WRITE D0H BLOCK ADDRESS WRITE D0H PAGE ADDRESS STATUS REGISTER READ STATUS REGISTER READ
NO NO SR.7 = 1 ? WRITE B0H ? NO SR.7 = 1 ?
WRITE B0H ?
NO
YES FULL STATUS CHECK IF DESIRED
YES FULL STATUS CHECK IF DESIRED
YES
SUSPEND LOOP WRITE D0H
YES
SUSPEND LOOP WRITE D0H
PAGE BUFFER TO FLASH COMPLETED YES
BLOCK ERASE COMPLETED
23
Sep 1999. Rev2.0
OPERATION STATUS and EFFECTIVE COMMAND
24 Clear Status Register
50H
Read/Standby State Read Status Register
90H 70H 70H 90H 71H 71H FFH FFH 70H 71H
Read Device Identifier
90H FFH
Read Lock Status
Read Array
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
Setup State Clear Page Buffer Setup
D0H 55H 74H
WD 0EH 41H 40H 77H
20H
A7H
Single Data Load to Page Buffer Setup
Page Buffer to Flash Setup
Page Program Setup
Byte Program Setup
WD D0H
Lock Bit Program Setup
Block Erase Setup
D0H
Erase All Unlocked Blocks Setup
OTHER
OTHER
D0H
Internal State
WDi i=0-255
OTHER
OTHER D0H
M5M29GB/T160BVP-80
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Program & Verify
Ready
Erase & Verify Read Status Register
D0H B0H B0H D0H
Read Status Register
Suspend State
Change Bank Address
Read Status Register
Change Bank Address
FFH 70H
70H
MITSUBISHI LSIs
Read State with BGO Read Array
(From The Other Bank)
Sep 1999. Rev2.0
Read Array
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
PACKAGE DIMENSIONS
48P3E-C EIAJ Package Code TSOP I 48-P-1220-0.50
48P3E (48pin 12 x 20 mm TSOP(I))
Plastic 48pin 12x20mm TSOP(I) Weight(g) Lead Material Cu Alloy MD e
JEDEC Code
HD D 1 48 xM b2 l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD L L1 Lp A3 z Z1 x y q b2 l2 MD Dimension in Millimeters Min Nom Max 1.2 0.125 0.2 0.05 1.0 0.15 0.2 0.3 0.105 0.125 0.175 18.3 18.4 18.5 11.9 12.0 12.1 0.5 19.8 20.0 20.2 0.4 0.5 0.6 0.8 0.6 0.75 0.45 0.25 0.25 0.4 0.1 0.1 10 0.225 0.9 18.6 b E y G 25 e A L1 A2 A3 F z A1
q
24
Lp Detail F
Detail G
Z1
L
c
0
25
Sep 1999. Rev2.0

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