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FEATURES Extremely Low Distortion Second Harmonic -88 dBc @ 5 MHz -83 dBc @ 20 MHz (AD8007) -77 dBc @ 20 MHz (AD8008) Third Harmonic -101 dBc @ 5 MHz -92 dBc @ 20 MHz (AD8007) -98 dBc @ 20 MHz (AD8008) High Speed 650 MHz, -3 dB Bandwidth (G = +1) 1000 V/ s Slew Rate Low Noise 2.7 nV/Hz Input Voltage Noise 22.5 pA/ Hz Input Inverting Current Noise Low Power 9 mA/Amplifier Typ Supply Current Wide Supply Voltage Range 5 V to 12 V 0.5 mV Typical Input Offset Voltage Small Packaging SOIC-8, MSOP, and SC70 Packages Available APPLICATIONS Instrumentation IF and Baseband Amplifiers Filters A/D Drivers DAC Buffers GENERAL DESCRIPTION
NC 1 -IN 2 +IN 3 -VS 4
Ultralow Distortion High Speed Amplifiers AD8007/AD8008
CONNECTION DIAGRAMS SOIC (RN-8)
AD8007
(Top View)
8 7 6 5
SC70 (KS-5)
VOUT 1 -VS 2 +IN 3
4
AD8007
(Top View)
5
NC +VS VOUT NC
+VS
-IN
NC = NO CONNECT
SOIC (RN) and MSOP (RM)
AD8008
VOUT1 1 -IN1 2 +IN1 3 -VS 4 (Top View)
8 7 6 5
+VS VOUT2 -IN2 +IN2
DISTORTION - dBc
The AD8007 (single) and AD8008 (dual) are high performance current feedback amplifiers with ultralow distortion and noise. Unlike other high performance amplifiers, the low price and low quiescent current allow these amplifiers to be used in a wide range of applications. ADI's proprietary second generation eXtra-Fast Complementary Bipolar (XFCB) process enables such high performance amplifiers with low power consumption. The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/Hz voltage noise, -83 dB SFDR @ 20 MHz (AD8007), and -77 dBc SFDR @ 20 MHz (AD8008). With the wide supply voltage range (5 V to 12 V) and wide bandwidth, the AD8007/AD8008 are designed to work in a variety of applications. The AD8007/AD8008 amplifiers have a low power supply current of 9 mA/amplifier. The AD8007 is available in a tiny SC70 package as well as a standard 8-lead SOIC. The dual AD8008 is available in both REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
8-lead SOIC and 8-lead MSOP packages. These amplifiers are rated to work over the industrial temperature range of -40C to +85C.
-30 -40 -50 -60 -70 -80
2ND
G = +2 RL = 150 VS = 5V VOUT = 2V p-p
-90
3RD
-100 -110
1
10 FREQUENCY - MHz
100
Figure 1. AD8007 Second and Third Harmonic Distortion vs. Frequency
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD8007/AD8008-SPECIFICATIONS
VS = 5 V (@ T = 25 C, R = 200
A S
, RL = 150
, RF = 499
, Gain = +2, unless otherwise noted.)
Min 540 250 180 200 50 900 AD8007/AD8008 Typ Max 650 500 230 235 90 30 1000 18 35 -88 -83/-77 -101 -92/-98 -77 43.0/42.5 42.5 -68 2.7 22.5 2 0.015 0.010 0.5 3 4 0.4 16 9 1.5 0.8 4 8 6 Unit MHz MHz MHz MHz MHz ns V/s ns ns dBc dBc dBc dBc dBc dBm dBm dB nV/Hz pA/Hz pA/Hz % Degree mV V/C A A nA/C nA/C M M M pF V dB V mA mA pF V mA dB dB
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth
Conditions G = +1, VO = 0.2 V p-p, RL = 1 k G = +1, VO = 0.2 V p-p, RL = 150 G = +2, VO = 0.2 V p-p, RL = 150 G = +1, VO = 2 V p-p, RL = 1 k VO = 0.2 V p-p, G = +2, RL = 150 2.5 V Input Step, G = +2, RL = 1 k G = +1, VO = 2 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p fC = 20 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p fC = 20 MHz, VO = 2 V p-p fC = 19.5 MHz to 20.5 MHz, RL = 1 k, VO = 2 V p-p fC = 5 MHz, RL = 1 k fC = 20 MHz, RL = 1 k f = 5 MHz, G = +2 f = 100 kHz -Input, f = 100 kHz +Input, f = 100 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150
Bandwidth for 0.1 dB Flatness Overdrive Recovery Time Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD Third Order Intercept Crosstalk (AD8008) Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Saturation Voltage Short Circuit Current, Source Short Circuit Current, Sink Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio +PSRR -PSRR
+Input -Input +Input -Input VO = 2.5 V, RL = 1 k RL = 150 +Input +Input VCM = 2.5 V VCC - VOH, VOL - VEE, RL = 1 k 30% Overshoot
1.0 0.4
56
4 1 -3.9 to +3.9 59 1.1 130 90 8 1.2
5 9 59 59 64 65
12 10.2
-2-
REV. C
AD8007/AD8008 VS = +5 V (@ T = 25 C, R = 200
A S
, RL = 150
, RF = 499
, Gain = +2, unless otherwise noted.)
Min 520 350 190 270 72 665 AD8007/AD8008 Typ Max 580 490 260 320 120 30 740 18 35 -96/-95 -83/-80 -100 -85/-88 -89/-87 43.0 42.5/41.5 -68 2.7 22.5 2 0.5 3 4 0.7 15 8 1.3 0.6 4 1 1.1 to 3.9 56 1.05 70 50 8 5 8.1 59 59 62 63 1.15 4 8 6 Unit MHz MHz MHz MHz MHz ns V/s ns ns dBc dBc dBc dBc dBc dBm dBm dB nV/Hz pA/Hz pA/Hz mV V/C A A nA/C nA/C M M M pF V dB V mA mA pF V mA dB dB
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth
Conditions G = +1, VO = 0.2 V p-p, RL = 1 k G = +1, VO = 0.2 V p-p, RL = 150 G = +2, VO = 0.2 V p-p, RL = 150 G = +1, VO = 1 V p-p, RL = 1 k Vo = 0.2 V p-p, G = +2, RL = 150 2.5 V Input Step, G = +2, RL = 1 k G = +1, VO = 2 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 5 MHz, VO = 1 V p-p fC = 20 MHz, VO = 1 V p-p fC = 5 MHz, VO = 1 V p-p fC = 20 MHz, VO = 1 V p-p fC = 19.5 MHz to 20.5 MHz, RL = 1 k, VO = 1 V p-p fC = 5 MHz, RL = 1 k fC = 20 MHz, RL = 1 k Output to Output f = 5 MHz, G = +2 f = 100 kHz -Input, f = 100 kHz +Input, f = 100 kHz
Bandwidth for 0.1 dB Flatness Overdrive Recovery Time Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD Third Order Intercept Crosstalk (AD8008) Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Saturation Voltage Short Circuit Current, Source Short Circuit Current, Sink Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio +PSRR -PSRR
+Input -Input +Input -Input VO = 1.5 V to 3.5 V, RL = 1 k RL = 150 +Input +Input VCM = 1.75 V to 3.25 V VCC - VOH, VOL - VEE, RL = 1 k 30% Overshoot
0.5 0.4
54
12 9
REV. C
-3-
AD8007/AD8008
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2 Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 1.0 V Output Short Circuit Duration . . . . . . . . . . . . . . See Figure 2 Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Lead Temperature Range (soldering 10 sec) . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS/4 for RL to midsupply: VS 4 PD = (VS x IS ) + RL
2
In single-supply operation, with RL referenced to VS, worst case is: VOUT = VS 2
MAXIMUM POWER DISSIPATION
MAXIMUM POWER DISSIPATION - W
The maximum safe power dissipation in the AD8007/AD8008 packages is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die will locally reach the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8007/ AD8008. Exceeding a junction temperature of 175C for an extended period of time can result in changes in the silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as follows:
Airflow will increase heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the JA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the board layout section. Figure 2 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC-8 (125C/ W), MSOP (150C/W), and SC70 (210C/W) packages on a JEDEC standard 4-layer board. JA values are approximations.
2.0
1.5
MSOP-8 SOIC-8
1.0
TJ = TA + (PD x JA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL ) is referenced to midsupply, the total drive power is VS/2 IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = quiescent power + (total drive power - load power): V V V PD = (VS x IS ) + S x OUT - OUT RL RL 2
2
SC70-5 0.5
0 -60
-40
-20 0 20 40 60 AMBIENT TEMPERATURE - C
80
100
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for the AD8007/AD8008 will likely cause catastrophic failure.
RMS output voltages should be considered. If RL is referenced to VS, as in single-supply operation, then the total drive power is VS IOUT.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD80 07/ AD8008 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. C
AD8007/AD8008
ORDERING GUIDE
Model AD8007AR AD8007AR-REEL AD8007AR-REEL7 AD8007AKS-REEL AD8007AKS-REEL7 AD8008AR AD8008AR-REEL7 AD8008AR-REEL AD8008ARM-REEL AD8008ARM-REEL7
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 5-Lead SC70 5-Lead SC70 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP
Package Outline RN-8 RN-8 RN-8 KS-5 KS-5 RN-8 RN-8 RN-8 RM-8 RM-8
Branding Information
HTA HTA
H2B H2B
REV. C
-5-
AD8007/AD8008-Typical Performance Characteristics
(VS = 5 V, RL = 150
3 2 1 G = +1
, RS = 200
, RF = 499
, unless otherwise noted.)
6.4 6.3 6.2 6.1 G = +2 GAIN - dB 6.0 5.9 5.8 5.7 VS = 5V VS = +5V G = +2
NORMALIZED GAIN - dB
0 -1 -2 -3 -4 -5 -6 -7 1 10 100 FREQUENCY - MHz 1000 G = +10 G = -1
5.6 5.5 5.4 10 100 FREQUENCY - MHz 1000
TPC 1. Small Signal Frequency Response for Various Gains
3 G = +1 2 1 0 GAIN - dB GAIN - dB -1 -2 -3 -4 -5 -6 -7 10 100 FREQUENCY - MHz 1000 RL = 150 , VS = +5V RL = 150 , VS = 5V RL = 1k , VS = 5V
TPC 4. 0.1 dB Gain Flatness; VS = +5, 5 V
9 G = +2 8 7 RL = 1k , VS = +5V 6 5 4 3 2 1 0 -1 10 100 FREQUENCY - MHz 1000 RL = 150 , VS = 5V 5V RL = 150 VS = +5V
RL = 1k , VS =
TPC 2. Small Signal Frequency Response for VS and RLOAD
3 2 1 0 G = +1 RL = 1k RS = 200
TPC 5. Small Signal Frequency Response for VS and RLOAD
9 G = +2 8 7 6 GAIN - dB 5 4 3 2 1 0 RF = RG = 649 RF = RG = 499 RF = RG = 324 RF = RG = 249
GAIN - dB
-1 -2 -3 -4 -5 -6 -7 10 100 FREQUENCY - MHz 1000 RS = 301 RS = 249
-1 10
100 FREQUENCY - MHz
1000
TPC 3. Small Signal Frequency Response for Various R S Values
TPC 6. Small Signal Frequency Response for Various Feedback Resistors, R F = RG
-6-
REV. C
AD8007/AD8008
10 G = +2 9 8 7 GAIN - dB 6 5 4 499 3 2 49.9 1 0 1 10 100 FREQUENCY - MHz 1000 200 CLOAD
10 1 10k -270 -330 1G 2G 10M 90 30 TRANSIMPEDANCE 0 -30 PHASE 10k 1k -90 -150 -180 100 -210
20pF 20pF AND 20 SNUB
20pF AND 10 SNUB
1M 100k
TRANSIMPEDANCE -
499 RSNUB 0pF
100k
10M 1M FREQUENCY - Hz
100M
TPC 7. Small Signal Frequency Response for Capacitive Load and Snub Resistor
3 2 1 0 G = +1 VS = +5V, +85 C VS = 5V, +85 C
TPC 10. Transimpedance and Phase vs. Frequency
9 G = +2 8 7 6 GAIN - dB 5 4 3 2 1 0 -1 10 100 FREQUENCY - MHz 1000 VS = +5V, -40 C VS = 5V, -40 C VS = 5V, +85 C VS = +5V, +85 C
GAIN - dB
-1 -2 -3 -4 -5 -6 -7 10 100 FREQUENCY - MHz 1000 VS = +5V, -40 C
VS =
5V, -40 C
TPC 8. Small Signal Frequency Response over Temperature, VS = +5 V, 5 V
3 VOUT = 2V p-p 2 1 G = +1 G = +2
TPC 11. Small Signal Frequency Response over Temperature, VS = +5 V, 5 V
9 G = +2 8 7 6 GAIN - dB 5 4 3 2 1 0 -1 10 RL = 150 , VS = 5V, VO = 2V p-p 5V, VO = 2V p-p
NORMALIZED GAIN - dB
0 -1 -2 -3 -4 -5 -6 -7 1 10 100 FREQUENCY - MHz 1000 G = +10 G = -1
RL = 1k , VS =
RL = 150 , VS = +5V, VO = 1V p-p RL = 1k , VS = +5V, VO = 1V p-p
100 FREQUENCY - MHz
1000
TPC 9. Large Signal Frequency Response for Various Gains
TPC 12. Large Signal Frequency Response for VS and R LOAD
REV. C
-7-
PHASE - Degrees
AD8007/AD8008
(VS = 5 V, RL = 150
-40 G= 1 VS = 5V VO = 1V p-p HD2, RL = 150 HD3, RL = 150
-60 HD2, RL = 1k
DISTORTION - dBc
, RS = 200
, RF = 499
, unless otherwise noted.)
-40 -50 G= 2 VS = 5V VO = 1V p-p
-50 -60
DISTORTION - dBc
HD2, RL = 1k -70 HD3, RL = 1k -80
-70 -80
HD2, RL = 150
-90 -100
-90 -100 HD3, RL = 1k -110 HD3, RL = 150
-110
1
10 FREQUENCY - MHz
100
1
10 FREQUENCY - MHz
100
TPC 13. AD8007 Second and Third Harmonic Distortion vs. Frequency and R L
-40 -50 -60
DISTORTION - dBc
TPC 16. AD8007 Second and Third Harmonic Distortion vs. Frequency and R L
-40 G= 2 VS = 5V VO = 2V p-p
G= 1 VS = 5V VO = 2V p-p
-50 -60
DISTORTION - dBc
HD2, RL = 1k
-70 -80 HD2, RL = 1k
HD2, RL = 150
-70
HD2, RL = 150
HD3, RL = 150
-80
-90 -100 HD3, RL = 1k
-90 -100
HD3, RL = 150
HD3, RL = 1k
-110
1
10 FREQUENCY - MHz
100
-110
1
10 FREQUENCY - MHz
100
TPC 14. AD8007 Second and Third Harmonic Distortion vs. Frequency and R L
-30
TPC 17. AD8007 Second and Third Harmonic Distortion vs. Frequency and R L
-30 G = +2 VS = 5V RL = 150
HD3, VO = 4V p-p
-40 -50
DISTORTION - dBc
VS = 5V VO = 2V p-p RL = 150
HD2, G = 10
-40 -50
DISTORTION - dBc
-60
HD3, G = 10
-60 -70 -80 -90
HD2, VO = 4V p-p
-70 -80
HD3, G = 1
HD2, VO = 2V p-p
-90
HD2, G = 1
-100 -110 1 10 FREQUENCY - MHz 100
-100 -110 1
HD3, VO = 2V p-p
10 FREQUENCY - MHz
100
TPC 15. AD8007 Second and Third Harmonic Distortion vs. Frequency and Gain
TPC 18. AD8007 Second and Third Harmonic Distortion vs. Frequency and V OUT
-8-
REV. C
AD8007/AD8008
(VS = 5 V, RS = 200
-40 -50 G=1 VS = 5V VO = 1V p-p
, RF = 499
, RL = 150
, @25 C, unless otherwise noted.)
-40 -50 G=2 VS = 5V VO = 1V p-p
-60
-60
DISTORTION - dBc
DISTORTION - dBc
HD2, RL = 150 -70 HD2, RL = 1k -80
HD2, RL = 150 -70 HD2, RL = 1k -80 -90
-90 HD3, RL = 1k -100 HD3, RL = 150 -110 1 10 FREQUENCY - MHz 100
HD3, RL = 1k -100 HD3, RL = 150 -110 1 10 FREQUENCY - MHz 100
TPC 19. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
-40 -50 G=1 VS = 5V VO = 1V p-p
TPC 22. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
-40 -50 G=2 VS = 5V VO = 2V p-p HD2, RL = 1k
-60
DISTORTION - dBc
-60
-70 HD2, RL = 150 -80 HD2, RL = 1k -90
DISTORTION - dBc
-70 HD2, RL = 150 -80 -90 HD3, RL = 1k
-100 HD3, RL = 1k -110 1 HD3, RL = 150 10 FREQUENCY - MHz 100
-100 HD3, RL = 150 -110 1 10 FREQUENCY - MHz 100
TPC 20. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
-30 -40 -50 DISTORTION - dBc -60 -70 -80 HD2, G = 1 -90 -100 HD3, G = 10 -110 1 HD3, G = 1 100 VS = 5V VO = 2V p-p RL = 150 HD2, G = 10
TPC 23. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
-30 -40 -50
DISTORTION - dBc
G=2 RL = 150 VS = 5
-60 HD2, VO = 4V p-p -70 HD2, VO = 2V p-p -80 -90
-100 -110
HD3, VO = 4V p-p HD3, VO = 2V p-p 1 10 FREQUENCY - MHz 100
10 FREQUENCY - MHz
TPC 21. AD8008 Second and Third Harmonic Distortion vs. Frequency and Gain
TPC 24. AD8008 Second and Third Harmonic Distortion vs. Frequency and VOUT
REV. C
-9-
AD8007/AD8008
(VS = 5 V, RS = 200
-60 G= 2 VS = 5V FO = 20MHz HD2, RL = 1k
, RF = 499
, RL = 150
, @25 C unless otherwise noted.)
-65
HD3, RL = 1k
-70 -75
-65
G= 2 VS = 5V FO = 20MHz HD2, RL = 150
HD3, RL = 1k
DISTORTION - dBc
-70 HD3, RL = 150
DISTORTION - dBc
-80 -85 HD2, RL = 1k -90 -95 HD3, RL = 150
-75
-80 HD2, RL = 150
-100
-85
-105
-90
1
1.5 VOUT - V p-p
2
2.5
-110 1 2 3 4 VOUT - V p-p 5 6
TPC 25. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
44 43
THIRD ORDER INTERCEPT - dBm
TPC 28. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
44 G= 2 VS = 5V VO = 2V p-p RL = 1k
THIRD ORDER INTERCEPT - dBm
42 41 40 39 38 37 36 35 5 10 15 20 25 30 35 40 45 50 FREQUENCY - MHz 55
G = +2 VS = 5V VO = 2V p-p RL = 1k
43 42 41 40 39 38 37 36 35
60
65
70
5
10
15
20
25
30 35 40 45 50 FREQUENCY - MHz
55
60
65
70
TPC 26. AD8007 Third Order Intercept vs. Frequency
-65 G= 2 VS = 5V FO = 20MHz HD2, RL = 1k
TPC 29. AD8008 Third Order Intercept vs. Frequency
-65 HD2, RL = 1k HD2, RL = 150
HD2, RL = 150
-70 -75 -80
-70
-75 -85 HD3, RL = 1k -90 -80 HD3, RL = 150 HD3, RL = 1k -85 -100 -105 -90 -110 1 1.5 VOUT - V p-p 2 2.5 -95
HD3, RL = 150
G= 2 VS = 5V FO = 20MHz 1 2 3 4 VOUT - V p-p 5 6
TPC 27. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
TPC 30. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
-10-
REV. C
AD8007/AD8008
(VS = 5 V, RL = 150
100
, RS = 200
, RF = 499
, unless otherwise noted.)
1000
CURRENT NOISE - pA/ Hz
VOLTAGE NOISE - nV/ Hz
100
INVERTING CURRENT NOISE 22.5pA/ Hz
10
2.7nV/ Hz
10
1 10
100
1k 10k FREQUENCY - Hz
100k
1M
1 10
NONINVERTING CURRENT NOISE 2.0pA/ Hz 100 1k 10k 100k FREQUENCY - Hz 1M 10M
TPC 31. Input Voltage Noise vs. Frequency
1000 G= 2
TPC 34. Input Current Noise vs. Frequency
-20 -30 G= 2 R = 150 VS = 5V VM = 1V p-p SIDE B DRIVEN
100
-40
OUTPUT IMPEDANCE -
CROSSTALK - dB
10
-50 -60 -70 -80
1
SIDE A DRIVEN
0.1
-90
0.01 100k
-100
1M 10M FREQUENCY - Hz 100M 1G
100k
1M
10M FREQUENCY - Hz
100M
1G
TPC 32. Output Impedance vs. Frequency
0 VS = -10 5V, 5V
TPC 35. AD8008 Crosstalk vs. Frequency (Output to Output)
20 10 0
-20 CMRR - dB PSRR - dB
-10 -20 -30 -40 -50 -60 -PSRR +PSRR
-30 -40 -50
-60 -70 100k
-70 -80 10k
1M
10M FREQUENCY - Hz
100M
1G
100k
10M 1M FREQUENCY - Hz
100M
1G
TPC 33. CMRR vs. Frequency
TPC 36. PSRR vs. Frequency
REV. C
-11-
AD8007/AD8008
G= 1 RL = 150 , VS = 5V AND 5V
G = +2
RL = 150 , VS = +5V AND 5V
RL = 1k , VS =
5V AND
5V
RL = 1k , VS = +5V AND 5V
50mV/DIV
50mV/DIV
0
10
20 30 TIME - ns
40
50
0
10
20
30 TIME - ns
40
50
TPC 37. Small Signal Transient Response for RL = 150 , 1 k and VS = +5 V, 5 V
TPC 40. Small Signal Transient Response for RL = 150 , 1 k and VS = +5 V, 5 V
G = +1
RL = 150
G = -1
INPUT
RL = 1k
OUTPUT
1V/DIV
1V/DIV
0
10
20 30 TIME - ns
40
50
0
10
20 30 TIME - ns
40
50
TPC 38. Large Signal Transient Response for RL = 150 , 1 k
TPC 41. Large Signal Transient Response, G = -1, RL = 150
G=
2
CLOAD = 0pF CLOAD = 10pF CLOAD = 20pF
G=
2
CL = 0pF CL = 20pF CL = 20pF RSNUB = 10
499 499 200 49.9 - + RSNUB CLOAD
1V/DIV 0 10 20 30 TIME - ns 40 50 0
50mV/DIV 10 20 30 TIME - ns 40 50
TPC 39. Large Signal Transient Response for Capacitive Load = 0 pF, 10 pF, and 20 pF
TPC 42. Small Signal Transient Response: Effect of Series Snub Resistor when Driving Capacitive Load
-12-
REV. C
AD8007/AD8008
4
G= VS RL = 1k 2
3 2 1
VOUT - V
G = +10 VS = 5V VIN = 0.75V
RL = 150
0 -1 -2 -3
OUTPUT (2V/DIV) VS INPUT (1V/DIV)
0
100
200 300 TIME - ns
400
500
-4 0 200 400 RL - 600 800 1000
TPC 43. Output Overdrive Recovery, RL = 1 k, 150 , VIN = 2.5 V
TPC 45. VOUT Swing vs. RLOAD, VS = 5 V, G = +10, VIN = 0.75 V
0.5 G = +2 0.4 0.3
SETTLING TIME - %
0.2 0.1 0 0.1 18ns 0.2 0.3 0.4 0.5 0 5 10 15 20 25 TIME - ns 30 35 40 45
TPC 44. 0.1% Settling Time, 2 V Step
REV. C
-13-
AD8007/AD8008
THEORY OF OPERATION
The AD8007 (single) and AD8008 (dual) are current feedback amplifiers optimized for low distortion performance. A simplified conceptual diagram of the AD8007 is shown in Figure 3. It closely resembles a classic current feedback amplifier comprised of a complementary emitter-follower input stage, a pair of signal mirrors, and a diamond output stage. However, in the case of the AD8007/AD8008, several modifications have been made to greatly improve the distortion performance over that of a classic current feedback topology.
+VS M1 I1 - - I3
USING THE AD8007/AD8008 Supply Decoupling for Low Distortion
Decoupling for low distortion performance requires careful consideration. The commonly adopted practice of returning the high frequency supply decoupling capacitors to physically separate (and possibly distant) grounds can lead to degraded even-order harmonic performance. This situation is shown in Figure 4 using the AD8007 as an example. Note that for a sinusoidal input, each decoupling capacitor returns to its ground a quasi-rectified current carrying high even-order harmonics.
RF 499 GND 1
CJ1 Q1 D1 IN+ D2 Q2 -VS CJ2 I2 - M2 RF RG Q4 IDI IN- +VS HiZ Q3 IDO
Q5
0.1 F RG 499 +VS
10 F +
OUT
IN
Q6
RS 200
AD8007
OUT
-VS 0.1 F 10 F + GND 2
-VS
- I4
Figure 4. High Frequency Capacitors Returned to Physically Separate Grounds (Not Recommended)
Figure 3. Simplified Schematic of AD8007
The signal mirrors have been replaced with low distortion, high precision mirrors. They are shown as "M1" and "M2" in Figure 3. Their primary function from a distortion standpoint is to greatly reduce the effect of highly nonlinear distortion caused by capacitances CJ1 and CJ2. These capacitors represent the collector-to-base capacitances of the mirrors' output devices. A voltage imbalance arises across the output stage, as measured from the high impedance node "HiZ" to the output node "Out." This imbalance is a result of delivering high output currents and is the primary cause of output distortion. Circuitry is included to sense this output voltage imbalance and generate a compensating current "IDO." When injected into the circuit, IDO reduces the distortion that would be generated at the output stage. Similarly, the nonlinear voltage imbalance across the input stage (measured from the noninverting to the inverting input) is sensed, and a current "IDI" is injected to compensate for input-generated distortion. The design and layout are strictly top-to-bottom symmetric in order to minimize the presence of even-order harmonics.
The decoupling scheme shown in Figure 5 is preferable. Here, the two high frequency decoupling capacitors are first tied together at a common node, and are then returned to the ground plane through a single connection. By first adding the two currents flowing through each high frequency decoupling capacitor, one is ensuring that the current returned into the ground plane is only at the fundamental frequency.
RF 499
10 F + RG 499 +VS 0.1 F RS 200
AD8007
0.1 F
OUT
IN
-VS 10 F +
Figure 5. High Frequency Capacitors Returned to Ground at a Single Point (Recommended)
Whenever physical layout considerations prevent the decoupling scheme shown in Figure 5, the user can connect one of the high frequency decoupling capacitors directly across the supplies and connect the other high frequency decoupling capacitor to ground. This is shown in Figure 6.
-14-
REV. C
AD8007/AD8008
RF 499
Output Capacitance
+VS
C1 0.1 F
10 F +
To a lesser extent, parasitic capacitances on the output can cause peaking of the frequency response. There are two methods to effectively minimize its effect: 1. Put a small value resistor in series with the output to isolate the load capacitance from the amplifier's output stage. (See TPC 7.)
OUT
RG 499
RS 200
AD8007
C2 0.1 F
IN
2. Increase the phase margin by (a) increasing the amplifier's gain or (b) adding a pole by placing a capacitor in parallel with the feedback resistor.
Input-to-Output Coupling
-VS
10 F +
Figure 6. High Frequency Capacitors Connected across the Supplies (Recommended)
Layout Considerations
To minimize capacitive coupling, the input and output signal traces should not be parallel. This helps reduce unwanted positive feedback.
External Components and Stability
The standard noninverting configuration with recommended power supply bypassing is shown in Figure 6. This is also the bypassing scheme used on the evaluation board shown in Figure 7. The 0.1 F high frequency decoupling capacitors should be X7R or NPO chip components. Connect C2 from the +VS pin to the -VS pin. Connect C1 from the +VS pin to signal ground. The length of the high frequency bypass capacitor leads is critical. Parasitic inductance due to long leads will work against the low impedance created by the bypass capacitor. The ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical.
LAYOUT AND GROUNDING CONSIDERATIONS Grounding
The AD8007 and AD8008 are current feedback amplifiers and, to a first order, the feedback resistor determines the bandwidth and stability. The gain, load impedance, supply voltage, and input impedances also have an effect. TPC 6 shows the effect of changing RF on bandwidth and peaking for a gain of +2. Increasing RF will reduce peaking but also reduce the bandwidth. TPC 1 shows that for a given RF, increasing the gain will also reduce peaking and bandwidth. Table I shows the recommended RF and RG values that optimize bandwidth with minimal peaking.
Table I. Recommended Component Values
Gain -1 +1 +2 +5 +10
RF() 499 499 499 499 499
RG() 499 NA 499 124 54.9
RS 200 200 200 200 200
A ground plane layer is important in densely packed PC boards to minimize parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and thus the high frequency impedance of the path. High speed currents in an inductive ground return will create an unwanted voltage noise. Broad ground plane areas will reduce the parasitic inductance.
Input Capacitance
The load resistor will also affect bandwidth as shown in TPCs 2 and 5. A comparison between TPCs 2 and 5 also demonstrates the effect of gain and supply voltage. When driving loads with a capacitive component, stability is improved by using a series snub resistor "RSNUB" at the output. The frequency and pulse responses for various capacitive loads are illustrated in TPCs 7 and 42, respectively. For noninverting configurations, a resistor in series with the input, RS, is needed to optimize stability for Gain = +1, as illustrated in TPC 3. For larger noninverting gains, the effect of a series resistor is reduced.
Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. Even 1 pF or 2 pF of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifier's gain, causing peaking of the frequency response or even oscillations if severe enough. It is recommended that the external passive components that are connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a distance of at least 0.05 mm from the input pins on all layers of the board.
REV. C
-15-
AD8007/AD8008
RF +VS C4 10 F + C1 0.1 F RGN INPUT SMA RT RS AGND C3 10 F + -VS RGP 4 5 AGND 1 RBT OUTPUT SMA
EVALUATION BOARD
AD8007
AGND 3
The SC70 board schematic is shown in Figure 7. To use the SC70 board in an inverting configuration, RGN is used and RGP is left open. The position of RS can be shifted so that it connects Pin 3 to ground. When used as a noninverter, RGP is populated and RGN is left open. In both configurations, RT allows for a 50 termination resistor. Universal (inverting or noninverting) AD8007 SOIC, AD8008 SOIC, and AD8008 MSOP boards are also available. The SC70 and MSOP evaluation boards are shown in Figures 8-15.
C2 2 0.1 F
Figure 7. Schematic of AD8007 Evaluation Board for the SC70 Package
-16-
REV. C
AD8007/AD8008
Figure 8. SC70 Evaluation Board Silkscreen (Top)
Figure 10. SC70 Evaluation Board, Amplifier Side (Top)
Figure 9. SC70 Evaluation Board Silkscreen (Bottom)
Figure 11. SC70 Evaluation Board, Component Side (Bottom)
REV. C
-17-
AD8007/AD8008
Figure 12. MSOP Evaluation Board Silkscreen (Top)
Figure 14. MSOP Evaluation Board, Amplifier Side (Top)
Figure 13. MSOP Evaluation Board Silkscreen (Bottom)
Figure 15. MSOP Evaluation Board, Amplifier Side (Bottom)
-18-
REV. C
AD8007/AD8008
OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075)
0.50 (0.0196) 0.25 (0.0099)
45
0.51 (0.0201) 0.33 (0.0130)
1.27 (0.0500) 0.41 (0.0160)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead MSOP Package [MSOP] (RM-8)
Dimensions shown in millimeters
3.00 BSC
8
5
3.00 BSC
1 4
4.90 BSC
PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.40
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
5-Lead Pastic Surface Mount Package [SC70] (KS-5)
Dimensions shown in millimeters
2.00 BSC
5
4
1.25 BSC
1 2 3
2.10 BSC
PIN 1 1.00 0.90 0.70 0.10 0.00 0.65 BSC 1.10 MAX 0.22 0.08 0.30 0.15 SEATING PLANE 0.46 0.36 0.26
COMPLIANT TO JEDEC STANDARDS MO-203AA
REV. C
-19-
AD8007/AD8008 Revision History
Location 10/02--Data Sheet changed from REV. B to REV. C Page
CONNECTION DIAGRAMS captions updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 5 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9/02--Data Sheet changed from REV. A to REV. B.
C02866-0-10/02(C) PRINTED IN U.S.A.
ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8/02--Data Sheet changed from REV. 0 to REV. A.
Added AD8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Added SOIC-8 (RN) and MSOP-8 (RM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to MAXIMUM POWER DISSIPATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 New TPCs 19-24 and TPCs 27, 29, 30, and 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MSOP-8 (RM) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
-20-
REV. C

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