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| a FEATURES Complete RF Detector/Controller Function Typical Range -58 dBV to -13 dBV -45 dBm to 0 dBm re 50 Frequency Response from 100 MHz to 2.5 GHz Temperature-Stable Linear-in-dB Response Accurate to 2.5 GHz Rapid Response: 70 ns to a 10 dB Step Low Power: 12 mW at 2.7 V Power-Down to 20 A APPLICATIONS Cellular Handsets (TDMA, CDMA, GSM) RSSI and TSSI for Wireless Terminal Devices Transmitter Power Measurement and Control PRODUCT DESCRIPTION 100 MHz-2500 MHz 45 dB RF Detector/Controller AD8314 For convenience, the signal is internally ac-coupled, using a 5 pF capacitor to a load of 3 k in shunt with 2 pF. This high-pass coupling, with a corner at 16 MHz, determines the lowest operating frequency. Thus, the source may be dc-grounded. The AD8314 provides two voltage outputs. The first, called V_UP, increases from close to ground to about 1.2 V as the input signal level increases from 1.25 mV to 224 mV. This output is intended for use in measurement mode. Consult the Applications section of this data sheet for information on use in this mode. A capacitor may be connected between the V_UP and FLTR pins when it is desirable to increase the time interval over which averaging of the input waveform occurs. The second output, V_DN, is an inversion of V_UP, but with twice the slope and offset by a fixed amount. This output starts at about 2.25 V (provided the supply voltage is 3.3 V) for the minimum input and falls to a value close to ground at the maximum input. This output is intended for analog control loop applications. A setpoint voltage is applied to VSET and V_DN is then used to control a VGA or power amplifier. Here again, an external filter capacitor may be added to extend the averaging time. Consult the Applications section of this data sheet for information on use in this mode. The AD8314 is available in a micro_SOIC package and consumes 4.5 mA from a 2.7 V to 5.5 V supply. When powered down, the typical sleep current is 20 A. The AD8314 is a complete low-cost subsystem for the measurement and control of RF signals in the frequency range 0.1 GHz-2.5 GHz, with a typical dynamic range of 45 dB, intended for use in a wide variety of cellular handsets and other wireless devices. It provides a wider dynamic range and better accuracy than possible using discrete diode detectors. In particular, its temperature stability is excellent over the full operating range of -30C to +85C. Its high sensitivity allows control at low power levels, thus reducing the amount of power that needs to be coupled to the detector. It is essentially a voltage-responding device, with a typical signal range of 1.25 mV to 224 mV rms or -58 dBV to -13 dBV. This is equivalent to -45 dBm to 0 dBm re 50 . FUNCTIONAL BLOCK DIAGRAM FLTR V-I VSET I-V DET DET DET DET DET X2 10dB 10dB 10dB 10dB BAND-GAP REFERENCE VPOS ENBL V UP RFIN V DN OFFSET COMP'N COMM (PADDLE) AD8314 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD8314-SPECIFICATIONS (V = 3 V, T = +25 C, unless otherwise noted) S A Parameter OVERALL FUNCTION Frequency Range Input Voltage Range Equivalent Power Range Logarithmic Slope Logarithmic Intercept Equivalent dBm Level INPUT INTERFACE DC Resistance to COMM Inband Input Resistance Input Capacitance MAIN OUTPUT Voltage Range Minimum Output Voltage Maximum Output Voltage2 General Limit Available Output Current Response Time Residual RF (at 2f) INVERTED OUTPUT Gain Referred to V_UP Minimum Output Voltage Maximum Output Voltage Available Output Current Output-Referred Noise Response Time Full-Scale Settling Time SETPOINT INPUT Voltage Range Input Resistance Logarithmic Scale Factor ENABLE INTERFACE Logic Level to Enable Power Input Current when HI Logic Level to Disable Power POWER INTERFACE Supply Voltage Quiescent Current Over Temperature Total Supply Current when Disabled Over Temperature Condition To Meet All Specifications Internally AC-Coupled 52.3 External Termination Main Output, V_UP, 100 MHz1 Main Output, V_UP, 100 MHz 52.3 External Termination (Pin RFIN) f = 0.1 GHz f = 0.1 GHz (Pin V_UP) V_UP Connected to VSET No Signal at RFIN, RL 10 k RL 10 k 2.7 V VS 5.5 V Sourcing/Sinking 10%-90%, 10 dB Step f = 0.1 GHz (Worst Condition) (Pin V_DN) VDN = 2.25 V - 2 x VUP VS 3.3 V VS 3.3 V3 Sourcing/Sinking RF Input = 2 GHz, -33 dBV, fNOISE = 10 kHz 10%-90%, 10 dB Input Step -40 dBm to 0 dBm Input Step, to 95% (Pin VSET) Corresponding to Central 40 dB f = 0.900 GHz f = 1.900 GHz (Pin ENBL) HI Condition, -30C TA +85C 2.7 V at ENBL, -30C TA +85C LO Condition, -30C TA +85C (Pin VPOS) -30C TA +85C -30C TA +85C Min 0.1 1.25 -45 18.85 -68 -55 Typ Max 2.5 224 0 23.35 -56 -43 Unit GHz mV rms dBm mV/dB dBV dBm k k pF 21.3 -62 -49 100 3 2 0.01 0.01 1.9 VS - 1.1 1/0.5 0.02 2 VS - 1 2/1 70 100 -2 0.05 2.2 6/200 1.05 70 150 1.2 0.05 V V V V mA ns V 0.01 2.1 4/100 0.1 2.5 V V mA/A V/Hz ns ns V k mV/dB mV/dB V A V V mA mA A A 0.15 7 1.2 10 20.7 19.7 VPOS 300 0.8 5.5 5.7 6.6 95 1.6 20 -0.5 2.7 3.0 2.7 3.0 4.5 4.4 20 40 NOTES 1 Mean and Standard Deviation specifications are available in Table I. 2 Increased output possible when using an attenuator between V_UP and VSET to raise the slope. 3 Refer to Figure 19 for details. Specifications subject to change without notice. -2- REV. 0 AD8314 ABSOLUTE MAXIMUM RATINGS* Pin Function Descriptions Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V V_UP, V_DN, VSET, ENBL . . . . . . . . . . . . . . . . 0 V, VPOS Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 V rms Equivalent Power . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 dBm Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 200 mW JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C Operating Temperature Range . . . . . . . . . . . -30C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin 1 2 3 Name RFIN ENBL VSET Function RF Input. Connect pin to V S for normal operation. Connect pin to ground for disable mode. Setpoint input for operation in controller mode. To operate in detector mode connect VSET to V_UP Connection for an external capacitor to slow the response of the output. Capacitor is connected between FLTR and V_UP. Device Common (Ground). Logarithmic output. Output voltage increases with increasing input amplitude. Inversion of V_UP, governed by the following equation: V_DN = 2.25 V - 2 x VUP. Positive supply voltage (VS), 2.7 V to 5.5 V. 4 FLTR 5 6 7 COMM V_UP V_DN VPOS PIN CONFIGURATION 8 RFIN 1 ENBL VSET 2 3 8 VPOS V DN TOP VIEW 6 V UP (Not to Scale) 7 5 AD8314 FLTR 4 COMM ORDERING GUIDE Model AD8314ARM* AD8314ARM-REEL AD8314ARM-REEL7 AD8314-EVAL *Device branded as J5A. Temperature Range -30C to +85C Package Description Tube, 8-Lead micro_SOIC 13" Tape and Reel 7" Tape and Reel Evaluation Board Package Option RM-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8314 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -3- AD8314 -Typical Performance Characteristics 1.2 0.1GHz 4 3 1.0 2 0.9GHz 0.8 1.9GHz 0.6 2.5GHz ERROR - dB VUP - Volts 1 0 -1 -2 0.2 -3 -4 -70 1.9GHz 0.1GHz 2.5GHz 0.4 0.9GHz 0 -75 -65 (-52dBm) -55 -45 -35 -25 INPUT AMPLITUDE - dBV -15 (-2dBm) -5 -60 (-47dBm) -50 -40 -30 -20 INPUT AMPLITUDE - dBV -10 (+3dBm) 0 Figure 1. VUP vs. Input Amplitude Figure 4. Log Conformance vs. Input Amplitude 1.2 3 1.2 3 1.0 +25 C 2 1.0 +85 C 2 0.8 VUP - Volts -30 C 0.6 +25 C 0.4 +85 C -30 C 1 ERROR - dB VUP - Volts 0.8 +25 C 0.6 -30 C 0.4 1 ERROR - dB ERROR - dB 0 0 -1 -1 0.2 SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -30 C AND +85 C -60 (-47dBm) -50 -40 -30 -20 INPUT AMPLITUDE - dBV -10 (+3dBm) 0 -2 0.2 SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -30 C AND +85 C -60 (-47dBm) -50 -40 -30 -20 INPUT AMPLITUDE - dBV -10 (+3dBm) 0 -2 0 -70 -3 0 -70 -3 Figure 2. VUP and Log Conformance vs. Input Amplitude at 0.1 GHz; -30C, +25 C, and +85C Figure 5. V UP and Log Conformance vs. Input Amplitude at 1.9 GHz; -30 C, +25C, and +85C 1.2 3 1.2 3 1.0 +25 C 0.8 VUP - Volts +85 C 0.6 -30 C 0.4 2 1.0 +85 C +85 C +25 C 0.6 -30 C 0.4 2 1 ERROR - dB VUP - Volts 0.8 1 0 0 -1 -1 0.2 SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -30 C AND +85 C -60 (-47dBm) -50 -40 -30 -20 INPUT AMPLITUDE - dBV -10 (+3dBm) 0 -2 0.2 SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -30 C AND +85 C -60 (-47dBm) -50 -40 -30 -20 INPUT AMPLITUDE - dBV -10 (+3dBm) 0 -2 0 -70 -3 0 -70 -3 Figure 3. VUP and Log Conformance vs. Input Amplitude at 0.9 GHz; -30 C, +25C, and +85C Figure 6. V UP and Log Conformance vs. Input Amplitude at 2.5 GHz; -30 C, +25C, and +85C -4- REV. 0 AD8314 23 -55 22 -30 C VUP INTERCEPT - dBV -30 C -60 +25 C -65 +85 C SLOPE - mV/dB 21 +25 C 20 +85 C 19 -70 18 0 0.5 1.0 1.5 FREQUENCY - GHz 2.0 2.5 -75 0 0.5 1.0 1.5 FREQUENCY - GHz 2.0 2.5 Figure 7. Slope vs. Frequency; -30 C, +25 C, and +85C Figure 10. VUP Intercept vs. Frequency: -30C, +25 C, and +85C 22 -61 0.1GHz 0.1GHz VUP INTERCEPT - dBV -62 2.5GHz -63 0.9GHz -64 VUP SLOPE - mV/dB 21 0.9GHz 20 1.9GHz -65 -66 2.5GHz 19 2.5 -67 2.5 1.9GHz 5.0 5.5 3.0 3.5 4.0 VS - Volts 4.5 5.0 5.5 3.0 3.5 4.0 VS - Volts 4.5 Figure 8. VUP Slope vs. Supply Voltage Figure 11. VUP Intercept vs. Supply Voltage 3500 X 3000 2500 RESISTANCE - 2000 FREQUENCY (GHz) 0.1 0.9 1.9 2.5 R || - jX 3030 || - j748 760 || - j106 301 || - j80 90 || - j141 0 -200 SUPPLY CURRENT - mA 6 5 4 DECREASING VENBL INCREASING VENBL -400 REACTANCE - -600 3 2 1500 R 1000 R 500 0 0 0.5 1.0 1.5 FREQUENCY - GHz 2.0 X -800 -1000 -1200 -1400 2.5 1 0 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VENBL - Volts 2.2 2.4 2.6 Figure 9. Input Impedance Figure 12. Supply Current vs. ENBL Voltage, VS = 3 V REV. 0 -5- AD8314 AVERAGE: 128 SAMPLES VDN 500mV/VERT. DIV. AVERAGE: 128 SAMPLES VDN 1V/VERT. DIV. VDN GND 1 s PER HORIZONTAL DIVISION VUP 500mV/VERT. DIV. GND VUP GND VENBL GND VENBL 5V PER VERTICAL DIVISION GND VUP 500mV/ VERT. DIV. PULSED RF 0.1GHz, -13dBV RF INPUT 200mV PER VERTICAL DIVISION 100ns PER HORIZONTAL DIVISION Figure 13. ENBL Response Time Figure 16. VUP and VDN Response Time, -40 dBm to 0 dBm HP8648B SIGNAL GENERATOR -33dBV RF OUT 10MHz REF OUTPUT EXT TRIG HP8116A PULSE GENERATOR TRIG OUT PULSE OUT HP8648B SIGNAL GENERATOR PULSE MODULATION MODE 10MHz REF OUTPUT PULSE MODE IN EXT TRIG OUT PICOSECOND PULSE LABS PULSE GENERATOR TRIG OUT 3.0V 0.1 F 1 RFIN 52.3 2 ENBL 3 VSET NC 4 FLTR VPOS 8 V DN 7 V UP 6 COMM 5 TEK P6204 FET PROBE TEK P6204 FET PROBE TRIG TEK TDS784C SCOPE RF SPLITTER -3dB RF OUT -3dB TEK P6204 FET PROBE 3.0V 0.1 F 1 RFIN 52.3 3.0V 2 ENBL 3 VSET NC 4 FLTR VPOS 8 V DN 7 V UP 6 COMM 5 TEK P6204 FET PROBE TEK P6204 FET PROBE TRIG TEK TDS784C SCOPE AD8314 AD8314 NC = NO CONNECT NC = NO CONNECT Figure 14. Test Setup for ENBL Response Time Figure 17. Test Setup for Pulse Response 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 -5 10 100 1k 10k 100k FREQUENCY - Hz 1M 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10M 10.0 V/ Hz RF INPUT -70dBm -60dBm -50dBm -40dBm NOISE SPECTRAL DENSITY - PHASE - Degrees AMPLITUDE - dB 1.0 -20dBm -30dBm 0.1 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 15. AC Response from VSET to V_DN Figure 18. VDN Noise Spectral Density -6- REV. 0 AD8314 2.3 0mA 2.2 4mA 2mA 2.2 SHADING INDICATES 3 SIGMA 2.1 2.3 2.1 VDN - V VDN - V 2.0 6mA 1.9 2.0 1.9 1.8 1.8 1.7 2.7 2.8 2.9 3.0 3.1 VS - Volts 3.2 3.3 3.4 3.5 1.7 2.7 2.8 2.9 3.0 3.1 3.2 VS - Volts 3.3 3.4 3.5 Figure 19. Maximum V DN Voltage vs. VS by Load Current Figure 22. Maximum VDN Voltage vs. VS with 3 mA Load VUP AVERAGE: 128 SAMPLES AVERAGE: 128 SAMPLES 200mV PER VERTICAL DIVISION VDN VDN 500mV/VERT. DIV. VDN GND VUP 500mV/VERT. DIV. VUP GND 2V PER VERTICAL DIVISION VDN GND VPOS AND ENABLE 2V PER VERTICAL DIVISION 100ns PER HORIZONTAL DIVISION VPOS AND ENABLE GND 1 s PER HORIZONTAL DIVISION GND Figure 20. Power-On and -Off Response, Measurement Mode Figure 23. Power-On Response, VDN , Controller Mode with VSET Held Low HP8648B SIGNAL GENERATOR -33dBV RF OUT 10MHz REF OUTPUT EXT TRIG HP8116A PULSE GENERATOR PULSE OUT TRIG OUT HP8648B SIGNAL GENERATOR 10MHz REF OUTPUT EXT TRIG HP8112A PULSE GENERATOR PULSE OUT TRIG OUT RF OUT AD811 AD811 49.9 49.9 TRIG TEK TDS784C SCOPE 1 RFIN 52.3 2 ENBL 3 VSET NC 4 FLTR VPOS 8 V DN 7 V UP 6 COMM 5 732 TEK P6204 FET PROBE TEK P6204 FET PROBE TRIG 52.3 TEK TDS784C SCOPE +0.2 1 RFIN 2 ENBL VPOS 8 V DN 7 V UP 6 NC COMM 5 732 TEK P6204 FET PROBE AD8314 AD8314 3 VSET NC 4 FLTR NC = NO CONNECT NC = NO CONNECT Figure 21. Test Setup for Power-On and -Off Response Figure 24. Test Setup for Power-On Response at V_DN Output, Controller Mode with VSET Pin Held Low REV. 0 -7- AD8314 Table I. Typical Specifications at Selected Frequencies at 25 C (Mean and Sigma) Slope - mV/dB Frequency - GHz 0.1 0.9 1.9 2.5 *Refer to Figure 29. Intercept - dBV -62.2 -63.6 -66.3 -62.1 0.4 0.4 0.4 0.7 1 dB Dynamic Range* - dBV High Point Low Point -11.8 -13.8 -19 -16.4 0.3 0.3 0.7 1.7 -59 -61.4 -64 -61 0.5 0.4 0.6 1.3 21.3 20.7 19.7 19.2 0.4 0.4 0.4 0.4 GENERAL DESCRIPTION The AD8314 is a logarithmic amplifier (log amp) similar in design to the AD8313; further details about the structure and function may be found in the AD8313 data sheet and other log amps produced by Analog Devices. Figure 25 shows the main features of the AD8314 in block schematic form. The AD8314 combines two key functions needed for the measurement of signal level over a moderately wide dynamic range. First, it provides the amplification needed to respond to small signals, in a chain of four amplifier/limiter cells, each having a small-signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each of these amplifier stages is a full-wave rectifier, essentially a square-law detector cell, that converts the RF signal voltages to a fluctuating current having an average value that increases with signal level. A further passive detector stage is added ahead of the first stage. Thus, there are five detectors, each separated by 10 dB, spanning some 50 dB of dynamic range. The overall accuracy at the extremes of this total range, viewed as the deviation from an ideal logarithmic response, that is, the law-conformance error, can be judged by reference to Figure 4, which shows that errors across the central 40 dB are moderate. Other curves show how the conformance to an ideal logarithmic function varies with supply voltage, temperature and frequency. The output of these detector cells is in the form of a differential current, making their summation a simple matter. It can easily be shown that such summation closely approximates a logarithmic function. This result is then converted to a voltage, at pin V_UP, through a high-gain stage. In measurement modes, this output is connected back to a voltage-to-current (V-I) stage, in such a manner that V_UP is a logarithmic measure of the RF input voltage, with a slope and intercept controlled by the design. For a fixed termination resistance at the input of the AD8314, a given voltage corresponds to a certain power level. However, in using this part, it must be understood that log amps do not fundamentally respond to power. It is for this reason that we use dBV (decibels above 1 V rms) rather than the commonly used metric of dBm. While the dBV scaling is fixed, independent of termination impedance, the corresponding power level is not. For example, 224 mV rms is always -13 dBV (with one further condition of an assumed sinusoidal waveform; see the Applications section for more information about the effect of waveform on logarithmic intercept), and it corresponds to a power of 0 dBm when the net impedance at the input is 50 . When this impedance is altered to 200 , the same voltage clearly represents a power level that is four times smaller (P = V2/R), that is, -6 dBm. Note that dBV may be converted to dBm for the special case of a 50 system by simply adding 13 dB (0 dBV is equivalent to +13 dBm). Thus, the external termination added ahead of the AD8314 determines the effective power scaling. This will often take the form of a simple resistor (52.3 will provide a net 50 input) but more elaborate matching networks may be used. This impedance determines the logarithmic intercept, the input power for which the output would cross the baseline (V_UP = zero) if the function were continuous for all values of input. Since this is never the case for a practical log amp, the intercept refers to the value obtained by the minimum-error straight-line fit to the actual graph of V_UP versus PIN (more generally, VIN). Again, keep in mind that the quoted values assume a sinusoidal (CW) signal. Where there is complex modulation, as in CDMA, the calibration of the power response needs to be adjusted accordingly. Where a true power (waveform-independent) response is needed, the use of an rms-responding detector, such as the AD8361, should be considered. However, the logarithmic slope, the amount by which the output V_UP changes for each decibel of input change (voltage or power) is, in principle, independent of waveform or termination impedance. In practice, it usually falls off somewhat at higher FLTR V-I VSET I-V DET DET DET DET DET X2 10dB 10dB 10dB 10dB BAND-GAP REFERENCE VPOS ENBL V UP RFIN V DN OFFSET COMP'N COMM (PADDLE) AD8314 Figure 25. Block Schematic -8- REV. 0 AD8314 frequencies, due to the declining gain of the amplifier stages and other effects in the detector cells. For the AD8314, the slope at low frequencies is nominally 21.3 mV/dB, falling almost linearly with frequency to about 19.2 mV/dB at 2.5 GHz. These values are sensibly independent of temperature (see Figure 7) and almost totally unaffected by the supply voltage from 2.7 V to 5.5 V (Figure 8). Inverted Output APPLICATIONS Basic Connections The second provision is the inclusion of an inverting amplifier to the output, for use in controller applications. Most power amplifiers require a gain-control bias that must decrease from a large positive value toward ground level as the power output is required to decrease. This control voltage, which appears at the pin V_DN, is not only of the opposite polarity to V_UP, but also needs to have an offset added in order to determine its most positive value when the power level (assumed to be monitored through a directional coupler at the output of the PA) is minimal. The starting value of V_DN is nominally 2.25 V, and it falls on a slope of twice that of V_UP, in other words, -43 mV/dB. Figure 26 shows how this is achieved: the reference voltage that determines the maximum output is derived from the onchip voltage reference, and is substantially independent of the supply voltage or temperature. However, the full output cannot be attained for supply voltages under 3.3 V; Figure 19 shows this dependency. The relationship between V_UP and V_DN is shown in Figure 27. V_UP CURRENTS FROM DETECTORS I-V +2 V_DN Figure 28 shows connections for the basic measurement mode. A supply voltage of 2.7 V to 5.5 V is required. The supply to the VPOS pin should be decoupled with a low inductance 0.1 F surface mount ceramic capacitor. A series resistor of about 10 may be added; this resistor will slightly reduce the supply voltage to the AD8314 (maximum current into the VPOS pin is approximately 9 mA when V_DN is delivering 5 mA). Its use should be avoided in applications where the power supply voltage is very low (i.e., 2.7 V). A series inductor will provide similar power supply filtering with minimal drop in supply voltage. 52.3 0.1 F INPUT VS 1 RFIN 2 ENBL 3 VSET 4 FLTR CF OPTIONAL (SEE TEXT) VPOS 8 OPTIONAL (SEE TEXT) V DN 7 V UP 6 COMM 5 VS VDN VUP AD8314 Figure 28. Basic Connections for Operation in Measurement Mode V-I VSET AD8314 VDN = 2.25V - 2.0 V_UP The ENBL pin is here connected to VPOS. The AD8313 may be disabled by pulling this pin to ground when the chip current is reduced to about 20 A from its normal value of 4.5 mA. The logic threshold is around +VS/2 and the enable function occurs in about 1.5 s. Note, however, further settling time is generally needed at low input levels. The AD8314 has an internal input coupling capacitor. This eliminates the need for external ac-coupling. A broadband input match is achieved in this example by connecting a 52.3 resistor between RFIN and ground. This resistance combines with the internal input impedance of approximately 3 k to give an overall broadband input resistance of 50 . Several other coupling methods are possible; these are described in the Input Coupling section. The measurement mode is selected by connecting VSET to V_UP, which establishes a feedback path and sets the logarithmic slope to its nominal value. The peak voltage range of the measurement extends from -58 dBV to -13 dBV at 0.9 GHz, and only slightly less at higher frequencies up to 2.5 GHz. Thus, using the 50 termination, the equivalent power range is -45 dBm to 0 dBm. At a slope of 21.5 mV/dB, this would amount to an output span of 967 mV. Figure 29 shows the transfer function for V_UP at a supply voltage of 3 V, and input frequency of 0.9 GHz. V_DN, which will generally not be used when the AD8314 is used in the measurement mode, is essentially an inverted version of V_UP. The voltage on V_UP and V_DN are related by the equation. VDN = 2.25 V - 2 VUP FLTR BAND-GAP REFERENCE 1.125V Figure 26. Output Interfaces 2.5 OUTPUT FOR PA CONTROL V_DN 1.5 VOLTS 1.0 OUTPUT FOR MEASUREMENT V_UP 0.5 0 -60 2.0 -50 -40 -30 -20 INPUT AMPLITUDE - dBV -10 0 Figure 27. Showing V_UP and V_DN Relationship While V_DN can deliver up to 6 mA, the load resistance on V_UP should not be lower than 10 k in order that the full-scale output of 1 V can be generated with the limited available current of 200 A max. Figure 29 shows the logarithmic conformance under the same conditions. REV. 0 -9- AD8314 1.2 VS = 3V RT = 52.3 1.0 1dB DYNAMIC RANGE 0.8 VUP - Volts 1 ERROR - dB 2 3 Filter Capacitor 0.6 0 The video bandwidth of both V_UP and V_DN is approximately 3.5 MHz. In CW applications where the input frequency is much higher than this, no further filtering of the demodulated signal will be required. Where there is a low-frequency modulation of the carrier amplitude, however, the low-pass corner must be reduced by the addition of an external filter capacitor, CF (see Figure 28). The video bandwidth is related to CF by the equation Video Bandwidth = 1 2 x 4.4 k x (10 pF + C F ) 0.4 -1 0.2 -2 3dB DYNAMIC RANGE INTERCEPT -3 -10 (+3dBm) 0 Operating in Controller Mode 0 -70 -60 (-47dBm) -50 -40 -30 -20 INPUT AMPLITUDE - dBV Figure 29. V UP and Log Conformance Error vs. Input Level vs. Input Level at 900 MHz Transfer Function in Terms of Slope and Intercept The transfer function of the AD8314 is characterized in terms of its Slope and Intercept. The logarithmic slope is defined as the change in the RSSI output voltage for a 1 dB change at the input. For the AD8314, slope is nominally 21.5 mV/dB. So a 10 dB change at the input results in a change at the output of approximately 215 mV. The plot of Log-Conformance (Figure 29) shows the range over which the device maintains its constant slope. The dynamic range can be defined as the range over which the error remains within a certain band, usually 1 dB or 3 dB. In Figure 29, for example, the 1 dB dynamic range is approximately 50 dB (from -13 dBV to -63 dBV). The intercept is the point at which the extrapolated linear response would intersect the horizontal axis (Figure 29). Using the slope and intercept, the output voltage can be calculated for any input level within the specified input range using the equation: VUP = V SLOPE x (PIN - PO) Figure 30 shows the basic connections for operation in the controller mode and Figure 31 shows a block diagram of a typical controller mode application. The feedback from V_UP to VSET is broken and the desired setpoint voltage is applied to VSET from the controlling source (often this will be a DAC). VDN will rail high (2.2 V on a 3.3 V supply, 1.9 V on a 2.7 V supply) when the applied power is less than the value corresponding to the setpoint voltage. When the input power slightly exceeds this value, VDN would, in the absence of the loop via the power amplifier gain pin, decrease rapidly toward ground. In the closed loop, however, the reduction in VDN causes the power amplifier to reduce its output. This restores a balance between the actual power level sensed at the input of the AD8314 and the demanded value determined by the setpoint. This assumes that the gain control sense of the variable gain element is positive, that is, an increasing voltage from V_DN will tend to increase gain. The output swing and current sourcing capability of V_DN are shown in Figures 19 and 20. 52.3 0.1 F INPUT VS VSET 1 RFIN 2 ENBL 3 VSET 4 FLTR VPOS 8 V DN 7 V UP 6 COMM 5 VS VDN where VUP is the demodulated and filtered RSSI output, VSLOPE is the logarithmic slope, expressed in V/dB, PIN is the input signal, expressed in decibels relative to some reference level (either dBm or dBV in this case) and PO is the logarithmic intercept, expressed in decibels relative to the same reference level. For example, at an input level of -40 dBV (-27 dBm), the output voltage will be VOUT = 0.020 V/dB x (-40 dBV - (-63 dBV )) = 0.46 V dBV vs. dBm AD8314 CF Figure 30. Basic Connections for Operation in Controller Mode POWER AMPLIFIER RF INPUT DIRECTIONAL COUPLER CF GAIN CONTROL VOLTAGE V UP FLTR V DN VSET DAC The most widely used convention in RF systems is to specify power in dBm, that is, decibels above 1 mW in 50 . Specification of log amp input levels in terms of power is strictly a concession to popular convention; they do not respond to power (tacitly "power absorbed at the input"), but to the input voltage. The use of dBV, defined as decibels with respect to a 1 V rms sine wave, is more precise, although this is still not unambiguous because waveform is also involved in the response of a log amp, which, for a complex input (such as a CDMA signal), will not follow the rms value exactly. Since most users specify RF signals in terms of power-- more specifically, in dBm/50 --we use both dBV and dBm in specifying the performance of the AD8314, showing equivalent dBm levels for the special case of a 50 environment. Values in dBV are converted to dBm re 50 by adding 13. AD8314 RFIN 52.3 Figure 31. Typical Controller Mode Application -10- REV. 0 AD8314 The relationship between the input level and the setpoint voltage follows from the nominal transfer function of the device (VUP vs. Input Amplitude, see Figure 1). For example, a voltage of 1 V on VSET is demanding a power level of 0 dBm at RFIN. The corresponding power level at the output of the power amplifier will be greater than this amount due to the attenuation through the directional coupler. When connected in a PA control loop, as shown in Figure 31, the voltage VUP is not explicitly used, but is implicated in again setting up the required averaging time, by choice of CF. However, now the effective loop response time is a much more complicated function of the PA's gain-control characteristics, which are very nonlinear. A complete solution requires specific knowledge of the power amplifier. The transient response of this control loop is determined by the filter capacitor, CF. When this is large, the loop will be unconditionally stable (by virtue of the "dominant pole" generated by this capacitor), but the response will be sluggish. The minimum value ensuring stability should be used, requiring full attention to the particulars of the power amplifier control function. Because this is invariably nonlinear, the choice must be made for the worst-case condition, which usually corresponds to the smallest output from the PA, where the gain function is steepest. In practice, an improvement in loop dynamics can often be achieved by adding a response zero, formed by a resistor in series with CF. Power-On and Enable Glitch the large input resistance. For low frequencies, Option a or Option c (see below) are recommended. In Figure 32b, the matching components are drawn as general reactances. Depending on the frequency, the input impedance at that frequency and the availability of standard value components, either a capacitor or an inductor will be used. As in the previous case, the input impedance at a particular frequency is plotted on a Smith Chart and matching components are chosen (shunt or series L, shunt or series C) to move the impedance to the center of the chart. Table II gives standard component values for some popular frequencies. Matching components for other frequencies can be calculated using the input resistance and reactance data over frequency which is given in Figure 9. Note that the reactance is plotted as though it appears in parallel with the input impedance (which it does because the reactance is primarily due to input capacitance). The impedance matching characteristics of a reactive matching network provide voltage gain ahead of the AD8314; this increases the device sensitivity (see Table II). The voltage gain is calculated using the equation: Voltage GaindB = 20 log10 R2 R1 As already mentioned, the AD8314 can be put into a low power mode by pulling the ENBL pin to ground. This reduces the quiescent current from 4.5 mA to 20 A. Alternatively, the supply can be turned off completely to eliminate the quiescent current. Figures 13 and 23 show the behavior of the V_DN output under these two conditions (in Figure 23, ENBL is tied to VPOS). The glitch that results in both cases can be reduced by loading the V_DN output. Input Coupling Options where R2 is the input impedance of the AD8314 and R1 is the source impedance to which the AD8314 is being matched. Note that this gain will only be achieved for a perfect match. Component tolerances and the use of standard values will tend to reduce the gain. 50 SOURCE 50 RSHUNT 52.3 RFIN CC AD8314 CIN VBIAS RIN The internal 5 pF coupling capacitor of the AD8314, along with the low frequency input impedance of 2 k give a high-pass input corner frequency of approximately 16 MHz. This sets the minimum operating frequency. Figure 32 shows three options for input coupling. A broadband resistive match can be implemented by connecting a shunt resistor to ground at RFIN (Figure 32a). This 52.3 resistor (other values can also be used to select different overall input impedances) resistor combines with the input impedance of the AD8314 (3 k 2 pF) to give a broadband input impedance of 50 . While the input resistance and capacitance (CIN and RIN) will vary by approximately 20% from device to device, the dominance of the external shunt resistor means that the variation in the overall input impedance will be close to the tolerance of the external resistor. At frequencies above 2 GHz, the input impedance drops below 250 (see Figure 9), so it is appropriate to use a larger value of shunt resistor. This value is calculated by plotting the input impedance (resistance and capacitance) on a Smith Chart and choosing the best value of shunt resistor to bring the input impedance closest to the center of the chart. At 2.5 GHz, a shunt resistor of 165 is recommended. A reactive match can also be implemented as shown in Figure 32b. This is not recommended at low frequencies as device tolerances will dramatically vary the quality of the match because of REV. 0 a. Broadband Resistive 50 SOURCE 50 X1 AD8314 RFIN X2 CC CIN VBIAS RIN b. Narrowband Reactive AD8314 CC CIN VBIAS RIN RFIN STRIPLINE RATTN c. Series Attenuation Figure 32. Input Coupling Options Figure 32c shows a third method for coupling the input signal into the AD8314, applicable in applications where the input signal is larger than the input range of the log amp. A series resistor, connected to the RF source, combines with the input impedance -11- AD8314 of the AD8314 to resistively divide the input signal being applied to the input. This has the advantage of very little power being "tapped off" in RF power transmission applications. Table II. Recommended Components for X1 and X2 in Figure 32b Table III. Shift in AD8314 Output for Signals with Differing Crest Factors Signal Type Sine Wave Square Wave GSM Channel (All Time Slots On) CDMA Channel (Forward Link, 9 Channels On) CDMA Channel (Reverse Link) PDC Channel (All Time Slots On) Correction Factor (Add to Measured Input Level) 0 dB -3.01 dB 0.55 dB 3.55 dB 0.5 dB 0.58 dB Frequency (GHz) 0.1 0.9 1.9 2.5 X1 Short 33 nH 10 nH 1.5 pF X2 52.3 39 nH 15 nH 3.9 nH Voltage Gain (dB) 11.8 7.8 2.55 Increasing the Logarithmic Slope in Measurement Mode Mobile Handset Power Control Examples The nominal logarithmic slope of 21.5 mV/dB (see Figure 7 for the variation of slope with frequency) can be increased to an arbitrarily high value by attenuating the signal between V_UP and VSET as shown in Figure 33. The ratio R1/R2 is set using the equation R1/R2 = (New Slope/Original Slope) - 1 In the example shown, two 5 k resistors combine to change the slope at 1900 MHz from 20 mV/dB to 40 mV/dB. The slope can be increased to higher levels. This will, however, reduce the usable dynamic range of the device. V_UP R1 5k VSET R2 5k 40mV/dB @ 1900MHz Figure 34 shows a complete power amplifier control circuit for a dual mode handset. This circuit is applicable to any dual mode handset using TDMA or CDMA technologies. The PF08107B (Hitachi) is driven by a nominal power level of +3 dBm. Some of the output power from the PA is coupled off using an LDC15D190A0007A (Murata) directional coupler. This has a coupling factor of approximately 19 dB for its lower frequency band (897.5 17.5 MHz) and 14 dB for its upper band (1747.5 37.5 MHz) and an insertion loss of 0.38 dB and 0.45 dB respectively. Because the PF08107B transmits a maximum power level of +35 dBm, additional attenuation of 15 dB is required before the coupled signal is applied to the AD8314. 3.5V 4.7 F 1000pF BAND SELECT 0V/2V POUT BAND 1 TO LDC15D190A0007A +35dBm MAX VCTL ANTENNA 7 1 8 4 PF081807B 5 3 (HITACHI) 49.9 2 ATTN 15dB 6 POUT BAND 2 +32dBm MAX VAPC PIN BAND 1 +3dBm PIN BAND 2 +3dBm AD8314 Figure 33. Increasing the Output Slope Effect of Waveform Type on Intercept Although specified for input levels in dBm (dB relative to 1 mW), the AD8314 fundamentally responds to voltage and not to power. A direct consequence of this characteristic is that input signals of equal rms power but differing crest factors will produce different results at the log amp's output. The effect of differing signal waveforms is to shift the effective value of the intercept upwards or downwards. Graphically, this looks like a vertical shift in the log amp's transfer function. The logarithmic slope, however, is not affected. For example, consider the case of the AD8314 being alternately fed by an unmodulated sine wave and by a single CDMA channel of the same rms power. The AD8314's output voltage will differ by the equivalent of 3.55 dB (70 mV) over the complete dynamic range of the device (the output for a CDMA input being lower). Table III shows the correction factors that should be applied to measure the rms signal strength of a various signal types. A sine wave input is used as a reference. To measure the rms power of a square wave, for example, the mV equivalent of the dB value given in the table (20 mV/dB times 3.01 dB) should be subtracted from the output voltage of the AD8314. 52.3 0.1 F 0dBm MAX 1 RFIN 2 ENBL 3 VSET 4 FLTR VPOS 8 V DN 7 V UP 6 COMM 5 +VS 2.7V +VS VSET 0V-1.1V AD8314 CF 220pF Figure 34. A Dual Mode Power Amplifier Control Circuit -12- REV. 0 AD8314 The setpoint voltage, in the range 0 V to 1.1 V, is applied to the VSET pin of the AD8314. This will typically be supplied by a Digital-to-Analog Converter (DAC). This voltage is compared to the input level to the AD8314. Any imbalance is between VSET and the RF input level is corrected by V_DN, which drives the VAPC (gain control) of the power amplifier. V_DN reaches a maximum value of approximately 1.9 V on a 2.7 V supply (this will be higher for higher supply voltages) while delivering approximately 3 mA to the VAPC input. A filter capacitor (CF ) must be used to stabilize the loop. The choice of CF will depend to a large degree on the gain control dynamics of the power amplifier, something that is frequently poorly characterized, so some trial and error may be necessary. In this example, a 220 pF capacitor gives the loop sufficient speed to follow the GSM and DCS1800 time slot ramping profiles, while still having a stable, critically-damped response. Figure 35 shows the relationship between the setpoint voltage, VSET and output power, at 0.9 GHz. The overall gain control function is linear in dB for a dynamic range of over 40 dB. Figure 36 shows a similar circuit for a single band handset power amplifier. The BGY241 (Phillips) is driven by a nominal power level of 0 dBm. A 20 dB directional coupler, DC09-73 (Alpha) is used to couple the signal in this case. Figure 37 shows the relationship between the control voltage and the output power at 0.9 GHz. In both of these examples, noise on the V_DN pin can be reduced by placing a simple RC low-pass filter between VDN and the gain control pin of the power amplifier. However, the value of the resistor should be kept low to minimize the voltage drop across it due to the dc current flowing into the gain control input. 40 10 30 POUT - dBm 0 -10 -20 10 -30 0 -10 -40 -50 0 -20 -30 0.2 0.4 0.6 VSET - Volts 0.8 1.0 VSET 0V-1.1V 3.5V 47 F 2.2 F 680pF TO ANTENNA DC09-73 6 4 3 +15dBm 1 5 2 +35dBm MAX BGY241 RF INPUT PIN 0dBm ATTN 15dB 52.3 0.1 F 0dBm MAX RFIN ENBL VSET FLTR VPOS V DN V UP COMM VS 2.7V VS AD8314 CF 220pF Figure 36. A Single Mode Power Amplifier Control Circuit 40 30 20 20 POUT - dBm 0 0.2 0.4 0.6 0.8 VSET - Volts 1.0 1.2 Figure 37. POUT vs. VSET at 0.9 GHz for Single Mode Handset Figure 35. POUT vs. VSET at 0.9 GHz for Dual Mode Handset Power Amplifier Application REV. 0 -13- AD8314 EVALUATION BOARD Figure 38 shows the schematic of the AD8314 evaluation board. The layout and silkscreen of the component side are shown in Figures 39 and 40. The board is powered by a single supply in the range, 2.7 V to 5.5 V. The power supply is decoupled R2 52.3 R1 0 INPUT VPOS 2 ENBL SW1 VSET 3 VSET 4 FLTR C4 (OPEN) R7 0 1 RFIN by a single 0.1 F capacitor. Additional decoupling, in the form of a series resistor or inductor in R9, can also be added. Table IV details the various configuration options of the evaluation board. C1 0.1 F R9 0 VPOS 8 R3 0 V DN 7 V UP 6 COMM 5 R5 0 R6 (OPEN) C3 (OPEN) VPOS V DN R4 (OPEN) C2 (OPEN) AD8314 LK1 V UP R8 (OPEN) Figure 38. Evaluation Board Schematic Figure 39. Layout of Component Side Figure 40. Silkscreen of Component Side -14- REV. 0 AD8314 Table IV. Evaluation Boards Configuration Options Component TP1, TP2 SW1 Function Supply and Ground Vector Pins Device Enable: When in position A, the ENBL pin is connected to +VS and the AD8314 is in operating mode. In Position B, the ENBL pin is grounded, putting the device in power-down mode. Input Interface: The 52.3 resistor in position R2 combines with the AD8314's internal input impedance to give a broadband input impedance of around 50 . A reactive match can be implemented by replacing R2 with an inductor and R1 (0 ) with a capacitor. Note that the AD8314's RF input is internally ac-coupled. Output Interface: R4, C2, R6, and C3 can be used to check the response of V_UP and V_DN to capacitive and resistive loading. R3/R4 and R5/R6 can be used to reduce the slope of V_UP and V_DN. Power Supply Decoupling: The nominal supply decoupling consists of a 0.1 F capacitor (C1). A series inductor or small resistor can be placed in R9 for additional decoupling. Filter Capacitor: The response time of V_UP and V_DN can be modified by placing a capacitor between FLTR (pin 4) and V_UP. Slope Adjust: By installing resistors in R7 and R8, the nominal slope of 20 mV/dB can be increased. See Slope Adjust discussion for more details. Measurement/Controller Mode: LK1 shorts V_UP to VSET, placing the AD8314 in measurement mode. Removing LK1 places the AD8314 in controller mode. Default Condition Not Applicable SW1 = A R1, R2 R2 = 52.3 (Size 0603) R1 = 0 (Size 0402) R3, R4, C2, R5, R6, C3 R4 = C2 = R6 = C3 = Open (Size 0603) R3 = R5 = 0 (Size 0603) C1, R9 C1 = 0.1 F (Size 0603) R9 = 0 (Size 0603) C4 C4 = Open (Size 0603) R7 = 0 (Size 0603) R8 = Open (Size 0603) LK1 = Installed R7, R8 LK1 REV. 0 -15- AD8314 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead micro_SOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27 0.028 (0.71) 0.016 (0.41) -16- REV. 0 PRINTED IN U.S.A. C2726-4.5-10/99 |
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