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ICS180-51
Low EMI Clock Generator
Description
The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses ICS' proprietary mix of analog and digital Phase-Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The ICS180-51 offers center spread selection of +/-0.625% and +/-1.875%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. ICS offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.
Features
* * * *
Pin and function compatible to Cypress W180-51 Packaged in 8-pin SOIC Provides a spread spectrum output clock Accepts a clock input and provides same frequency dithered output
* Input frequency of 8 to 28 MHz * Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
* Spread percentage selection for +/-0.625% and
+/-1.875%
* Operating voltage of 3.3 V and 5 V * Advanced, low-power CMOS process
Block Diagram
VDD
FS2:1 SS% PLL Clock Synthesis and Spread Spectrum Circuitry
CLK
X1/CLKIN X2
Clock Buffer/ Crystal Oscillator
GND
MDS 180-51 A
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ICS180-51 LOW EMI CLOCK GENERATOR
Pin Assignment
X1/CLKIN X2 GND SS% 1 2 3 4 8 7 6 5 FS2 FS1 VDD CLKOUT
Spread Spectrum Select Table
SS% (Pin 4) 0 1 Spread Direction Center Center Spread Percentage (%) +/-0.625% +/1.875%
8 pin (150 mil) SOIC
0 = connect to GND 1 = connect directly to VDD Note: SS% pin has an internal pull-up resistor
Frequency Range Selection Table
FS2 FS1 (Pin 8) (Pin 7) Frequency Range Selection (MHz) 8-10 10-15 15-18 18-28
0 0 1 1
0 1 0 1
Pin Descriptions
Pin Number Pin Name Pin Type Pin Description
1 2 3 4 5 6 7 8
X1/CLKIN X2 GND SS% CLKOUT VDD FS1 FS2
Input Output Power Input Output Power Input Input
Crystal or Clock Input. Crystal output. Float for a clock input. Connect to ground. Select pin for spread amount. See table above. Internal pull-up resistor. Spread spectrum clock output per table above. Connect to 3.3 V or 5 V. Select pin for input frequency. See table above. Internal pull-up resistor. Select pin for input frequency. See table above. Internal pull-up resistor.
MDS 180-51 A
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ICS180-51 LOW EMI CLOCK GENERATOR
External Components
The ICS180-51 requires a minimum number of external components for proper operation.
value of these capacitors is given by the following equation:
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS180-51. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected between VDD and GND on pins 6 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS180-51. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.135
Typ.
Max.
+70 +5.5
Units
C V
MDS 180-51 A
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I n t e gra t e d C i r cu i t S y s t e m sl 52 5 Race Stre et, San Jose, CA 95 126
ICS180-51 LOW EMI CLOCK GENERATOR
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Supply Current Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Capacitance Output Impedance Input Pull-up Resistor Power-up Time
Symbol
VDD IDD VIH VIL VOH VOH VOL CIN Rout
Conditions
No load
Min.
3.135
Typ.
18
Max.
3.465 32 0.8
Units
V mA V V V V
2.4 IOH = -4 mA IOH = -15 mA IOL = 15 mA 5 25 500 First locked clock cycle after steady power 5 VDD-0.4 2.4 0.4 7
V pF ohms K ms
Unless stated otherwise, VDD = 5 V, 10%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Supply Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Capacitance Input Pull-up Resistor Power-up Time
Symbol
VDD IDD VIH VIL VOH VOL Rout CIN
Conditions
No load
Min.
4.5 0.7VDD
Typ.
5 30
Max.
5.5 50 0.15VDD
Units
V mA V V V V ohms pF K ms
IOH = -24 mA IOL = 24 mA
2.4 0.4 20 5 500 7 5
First locked clock cycle after steady power
MDS 180-51 A
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Revision 110404 te l (4 08) 297 -1 201l w w w. i c s t . c o m
I n t e gra t e d C i r cu i t S y s t e m sl 52 5 Race Stre et, San Jose, CA 95 126
ICS180-51 LOW EMI CLOCK GENERATOR
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V5% or 5 V10%, Ambient Temperature 0 to +70 C, CL=15 pf
Parameter
Input/Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle Output Rise Time Output Fall Time Jitter Note 1: Measured with 15 pF load
Symbol
Conditions
Time above VDD/2 Note 1
Min.
8 40 40
Typ.
Max. Units
28 60 MHz % % ns ns ps
50 2 2 250
60 5 5 300
tOR tOF
0.8 to 2.4 V, note 1 2.4 to 0.8 V, note 1 Cycle-to-cycle
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
150 140 120 40
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram
Notes:
8 5
1. ###### is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. "LF" denotes Pb (lead) free package. 4. Bottom marking: country of origin.
180M-51 ###### YYWW
1 4
Marking Diagram (Pb free)
8 5
180M51LF ###### YYWW
1 4
MDS 180-51 A
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Revision 110404 te l (4 08) 297 -1 201l w w w. i c s t . c o m
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ICS180-51 LOW EMI CLOCK GENERATOR
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters Symbol Min Max
Inches Min Max
E INDEX AREA
H
12 D
A A1 B C D E e H h L
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
h x 45 C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS180M-51 ICS180M-51T ICS180M-51LF ICS180M-51LFT
Marking
Shipping packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
see page 5
"LF" denotes Pb free packaging. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 180-51 A
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Revision 110404 te l (4 08) 297 -1 201l w w w. i c s t . c o m
I n t e gra t e d C i r cu i t S y s t e m sl 52 5 Race Stre et, San Jose, CA 95 126

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