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| P . on. icati ange pecif ct to ch nal s je t a fi are sub no his is ic limits tr ce: T Noti parame e Som RY INA IM REL MITSUBISHI M66272FP LCD CONTROLLER with VRAM * Displayable LCD * Binary display Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2 VGA) * 4 gray scale display Monochrome STN-LCD of up to 76800 dots(equivalent to 1/4 VGA) Reflective color STN-LCD of up to 76800 dots (equivalent to 1/4 VGA) * Interface with MPU * Capability of switching the interface with two-way 8/16-bit MPU * Provides WAIT output pin(WAIT output when access from MPU to VRAM is gained) * Capability of controlling BHE or LWR/HWR at the interface with a 16-bit MPU * Interface with LCD * LCD display data bus is a 4-bit or 8-bit parallel output. * 4 kinds of control signals: CP, LP, FLM and M * Display functions * Graphic display only * Binary or 4 gray scale display(gray scale palette is used to set pseudo medium 2 gray scale.) * Reflective color(ECB) uses a gray scale function. * Vertical scrolling is allowed within memory range. * Additional function for LCD module built-in system * Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU byte access is not allowed.) * Access from MPU to VRAM is gained via the I/O register. * 5V or 3V single power supply DESCRIPTION The M66272FP is a graphic display-only controller for dot matrix type STN-LCD which is used widely for OA equipment, PDA, amusement equipment, etc. It is capable of displaying six types of LCD by combining the panel configuration(single or dual scan), LCD display function(binary or gray scale), LCD display data bus width(4 or 8 bit). Panel configuration Single scan Binary/ gray scale LCD display data 4bit Binary 8bit 4bit Gray scale 8bit Binary 4bit Gray scale 4bit Displayable LCD size Equivalent to 640 x 240 Equivalent to 320 x 240 Equivalent to 320 x 240 x 2 screens Equivalent to 320 x 120 x 2 screens Dual scan The M66272FP can support the reflective color type LCD (ECB : Electrically Controlled Birefringence). The IC has a built-in 19200-byte VRAM as a display data memory. All of the VRAM addresses are externally opened. Direct addressing of display data can be performed from MPU, thus display data processing such as drawing can be efficiently carried out. The built-in arbiter circuit(cycle steal system) which gives priority to display access allows timing-free access from MPU to VRAM, preventing display screen distortion. The IC provides has a function for LCD module built-in system by lessening connect pins between the MPU and the IC. FEATURES * Display memory * Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 320 x 240 dots x 2 screens) * All addresses of built-in VRAM are externally opened. APPLICATION * PPC/FAX operation panel, display/operation panel of other OA equipment, multifunction/public telephone * PDA/electronic notebook/information terminal, portable terminal * Game, Amusements, kid's computer etc. PIN CONFIGURATION (TOP VIEW) 61 64 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 VSS DISPLAY DATA TRANSFER CLOCK CP DISPLAY DATA LATCH PULSE LP FIRST LINE MARKER SIGNAL FLM VD<0> VD<1> VD<2> VD<3> LCD DISPLAY DATA BUS VD<4> VD<5> VD<6> VD<7> VDD N.C N.C VSS 41 VSS VDD LCD ALTERNATING M SIGNAL LCDENB LCD CONTROL D<15> SIGNAL D<14> D<13> D<12> MPU DATA BUS D<11> D<10> D<9> D<8> VDD VSS D<7> D<6> D<5> D<4> MPU DATA BUS D<3> D<2> D<1> D<0> VDD VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 20 21 22 23 10 11 12 13 14 15 16 17 18 19 24 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 M66272FP 33 32 31 30 29 28 27 26 25 VSS N.C N.C N.C CSE CYCLE STEAL ENABLE VSS VDD SWAP BUS SWAP A<14> A<13> A<12> MPU ADDRESS A<11> BUS A<10> A<9> A<8> VSS MPU CLOCK MPUCLK VSS RESET RESET 8/16MPU SELECT MPUSEL VSS BUS HIGH ENABLE BHE A<0> A<1> A<2> A<3> MPU ADDRESS BUS A<4> A<5> A<6> A<7> VDD IOCS HWR LWR RD MCS WAIT VDD VSS Outline 80P6N-A CONTROL REGISTER CHIP SELECT HIGH WRITE STROBE LOW WRITE STROBE READ STROBE VRAM CHIP SELECT WAIT VSS N.C : No Connection 1 P . on. icati ange pecif ct to ch nal s je t a fi are sub no his is ic limits tr ce: T Noti parame e Som RY INA IM REL MITSUBISHI M66272FP LCD CONTROLLER with VRAM BLOCK DIAGRAM 1 15 VDD 8 23 34 42 52 63 77 - 22 26 MPU ADDRESS BUS A<14:0> - ADDRESS BUFFER 61 32 CONTROL REGISTER LCD DISPLAY TIMING CONTROL CIRCUIT GRAY SCALE PATTERN TABLE 66 67 68 62 LCDENB SIGNAL DISPLAY DATA CP TRANSFER CLOCK LP LCD CONTROL 43 DISPLAY DATA LATCH PULSE FLM FIRST LINE MARKER SIGNAL M LCD ALTERNATING SIGNAL - MPU DATA BUS D<15:0> 50 53 - DATA BUFFER 60 VRAM CONTROL REGISTER IOCS CHIP SELECT VRAM CHIP SELECT MCS 2 6 3 4 5 12 11 14 33 9 7 36 - 19200byte HWR LOW W RITE STROBE LWR READ STROBE RD 8/16MPU SELECT MPUSEL RESET RESET BUS HIGH ENABLE BHE BUS SWAP SWAP MPU CLOCK MPUCLK WAIT WAIT CYCLE STEAL ENABLE CSE HIGH WRITE STROBE LCD DISPLAY DATA CONTROL CIRCUIT 69 VD<7:0> LCD DISPLAY DATA BUS 76 MPU I/F CONTROL CIRCUIT BUS ARBITER TIMIG CONTROL CLOCK CONTROL (BASIC TIMING CONTROL) (CYCLE STEAL CONTROL) 1 10 13 24 25 35 40 41 51 64 65 80 37 38 39 78 79 VSS N.C BLOCK DIAGRAM 2 (When interfacing with the LCD module built-in system and having the maximum number of pins connected with MPU) INPUT FIXED PIN 3 6 11 12 14 15 26 32 33 OPEN PIN 7 VDD 8 23 34 42 52 63 77 - MPU ADDRESS BUS 16 A<7:1> 22 MPU DATA BUS D<15:0> 50 53 60 DATA BUFFER - VRAM ADDRESS INDEX REGISTER CONTROL REGISTER IOCS CHIP SELECT 2 DATA PORT REGISTER VRAM 19200byte GRAY SCALE PATTERN TABLE 43 - - LOW WRITE STROBE READ STROBE LWR RD 4 5 MPU CLOCK MPUCLK 9 2 - ADDRESS BUFFER CONTROL REGISTER LCD DISPLAY TIMING CONTROL CIRCUIT 61 LCDENB SIGNAL LCD CONTROL 66 67 68 62 DISPLAY DATA CP TRANSFER CLOCK LP DISPLAY DATA LATCH PULSE FLM FIRST LINE MARKER SIGNAL LCD ALTERNATING M SIGNAL LCD DISPLAY DATA CONTROL CIRCUIT 69 VD<7:0> LCD DISPLAY DATA BUS 76 MPU I/F CONTROL CIRCUIT BUS ARBITER TIMIG CONTROL CLOCK CONTROL (BASIC TIMING CONTROL) 1 10 13 24 25 35 40 41 51 64 65 80 36 37 38 39 78 79 VSS N.C P tion. ange. ifica h spec t to c final bjec u not a s are s it is is h m tric li ce: T Noti parame e Som RY INA IM REL MITSUBISHI M66272FP LCD CONTROLLER with VRAM PIN DESCRIPTIONS Item Pin name Output D<15:0> Input/ Output Input/ Function MPU data bus When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to VDD or VSS. MPU address bus When selecting 8-bit MPU, use A<14:0>. When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to internal VRAM can be gained. When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address is restricted. Use A<7:0> for selecting address of control register. Number of pins 16 A<14:0> Input 15 IOCS MCS HWR Input Input Chip select input of control register When this pin is "L", select the internal control register. Assign to I/O space of MPU. Chip select input of VRAM When this pin is "L", select the internal VRAM. Assign to memory space of MPU. High-Write strobe input When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU controlled byte access by LWR and HWR. Low-Write strobe input When this pin is "L", write data to the internal control register or VRAM. Read strobe input When this pin is "L", read data from the internal control register or VRAM. 8/16-bit MPU select input According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU. Reset input Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and counters. MPU clock Input system clock output from MPU. Bus-High-Enable input This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE. Connect to "VDD" to select 8-bit MPU. Bus swap input When selecting 16-bit MPU, connect SWAP to "VSS" to transfer VD 1 1 Input Input Input Input 1 1 1 1 LWR RD MPU interface MPUSEL RESET MPUCLK Input 1 1 1 Input Input BHE SWAP Input 1 WAIT Output 1 CSE VD<7:0> Output Output Cycle Steal Enable output State output of internal cycle steal access. Display data bus for LCD Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in parallel. The VD 1 8 1 CP Output LP LCD interface FLM M Output 1 Output Output 1 LCD alternating signal output Signal for driving LCD by alternating current. LCD (ON/OFF) control signal output Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be used for controlling the LCD power supply, because LCDENB is set to "L" by RESET. Power supply pin Ground 1 LCDENB Output VDD Others VSS N.C 1 7 12 5 3 No connection P . ation nge. ecific t to cha c al sp a fin re subje not a his is ic limits tr ce: T Noti parame e Som RY INA IM REL MITSUBISHI M66272FP LCD CONTROLLER with VRAM OUTLINE M66272FP is a graphic display only controller for displaying a dot matrix type STN-LCD. * LCD display mode It is capable of displaying six types of LCD by combining the panel configuration, binary/gray scale, LCD display data bus width. Display mode 1 Panel Binary/ LCD display configuration gray scale data 4bit Binary Single scan Gray scale 8bit 4bit 8bit Dual scan Binary Gray scale 4bit 4bit Displayable LCD size Equivalent to 640 x 240 Equivalent to 320 x 240 Equivalent to 320 x 240 x 2 screens Equivalent to 320 x 240 x 2 screens * Cycle steal system Cycle steal system is interact method of transforming display data for LCD from VRAM and accessing VRAM from MPU on the basic cycle (MAINCLK) of internal operation. Basic timing is two clocks of MAINCLK, and assign first clock to the access from MPU to VRAM and second clock to the transfer of display data from VRAM to LCD. In accessing VRAM from MPU, output WAIT. Change WAIT to "L" at the timing of the falling edge of overlapping with MCS and RD or LWR / HWR, and return to "H" at synchronizing with rising edge of MPUCLK after internal processing. For the cycle steal system, this IC provides a cycle steal control function to improve data transfer efficiency in a line. This function gains access with the cycle steal system by taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On the other side, it does not output WAIT for keeping throughput of MPU during horizontal synchronous term (idle running term) with no necessity for the display data transfer from VRAM to LCD side. * Output to LCD side LCD display data VD<7:0> is output in parallel per 4 bits or 8 bits in synchronization with the rising edge of CP. Pin VD 3 2 3 4 5 6 * Control register When accessing the control register from MPU, use pins IOCS, LWR, RD, A<7:0> and D<7:0>. (However, use D<15:0> only when 16-bit MPU controls the LCD module built-in support function.) The IC contains the following registers as control registers. Operation control Gray scale pattern table R1 to R11 R17 to R80 Supporting LCD module built-in type R12 to 14 or R15 to 16 * VRAM This IC has a built-in 19200-byte VRAM which is equivalent to two screens of 320 x 240 dots LCD. When accessing VRAM from MPU, use pins MCS, HWR, LWR, RD, BHE, A<14:0> and D<15:0>. Use of MPUSEL input can support both 8-bit MPU and 16-bit MPU. The VRAM address settable range is restricted depending on the panel configuration, as follows. VRAM address settable range When single scan mode * A<14:0>=0000 to 4AFFH --- 19200 byte 0000H VRAM 4AFFH When dual scan mode * For the 1st screen --- A<14:0>=0000 to 257FH --- 9600 byte * For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte 0000H VRAM for the 1st screen 257FH 2580H VRAM for the 2nd screen 4AFFH VD<7:0> 2 4 VD<3:0> 5 6 When display data for a line has been sent, LP outputs data in synchronization with the falling edge of MAINCLK. The IC enables adjustment to an optimum value of the frame frequency as requested from the LCD PANEL side by adjusting pulse width of LP with the LPW register value. FLM is output when the display data for the first line has been sent. M output is an LCD alternating signal for driving LCD with alternating current. M output cycles can be set in lines with the M output cycle variable register and is available to prevent LCD from deterioration. * Gray scale display function Gray scale display can assign 2-bit VRAM data to a picture element of LCD display to show the display density at four levels. Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16 patterns x 2 medium gray scale), consisting of SRAM of 64 bytes in total, can set any gray scale display pattern. * Application to reflective color type LCD The above gradation display function is available to control about four display colors on the reflective color type LCD with ECB (Electrically Controlled Birefringence). 4 |
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