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UC1825 UC2825 UC3825
High Speed PWM Controller
FEATURES
* * * * * * * * * * Compatible with Voltage or Current Mode Topologies
DESCRIPTION
The UC1825 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators Practical Operation Switching Frequencies and logic circuitry while maximizing bandwidth and slew rate of the to 1MHz error amplifier. This controller is designed for use in either cur50ns Propagation Delay to Output rent-mode or voltage mode systems with the capability for input voltage feed-forward. High Current Dual Totem Pole Outputs (1.5A Peak) Protection circuitry includes a current limit comparator with a 1V threshold, a TTL compatible shutdown port, and a soft start pin Wide Bandwidth Error Amplifier which will double as a maximum duty cycle clamp. The logic is fully Fully Latched Logic with Double Pulse latched to provide jitter free operation and prohibit multiple pulses at Suppression an output. An under-voltage lockout section with 800mV of hysteresis assures low start up current. During under-voltage lockout, the outPulse-by-Pulse Current Limiting puts are high impedance. Soft Start / Max. Duty Cycle Control These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a Under-Voltage Lockout with Hysteresis power MOSFET. The on state is designed as a high level. Low Start Up Current (1.1mA)
BLOCK DIAGRAM
UDG-92030-2
SLUS235A - MARCH 1997 - REVISED MARCH 2004
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Pins 13, 15) . . . . . . . . . . . . . . . . . . . . . . . . 30V Output Current, Source or Sink (Pins 11, 14) DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5m s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Analog Inputs (Pins 1, 2, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V (Pin 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300C
CONNECTION DIAGRAMS
DIL-16 (Top View) J or N Package
UC1825 UC2825 UC3825
SOIC-16 (Top View) DW Package
PLCC-20 & LCC-20 (Top View) Q & L Packages
PACKAGE PIN FUNCTION FUNCTION PIN
N/C INV NI E/A Out Clock N/C RT CT Ramp Soft Start N/C ILIM/SD Gnd Out A Pwr Gnd N/C VC Out B VCC VREF 5.1V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
THERMAL RATINGS TABLE
Package DIL-16J DIL-16N PLCC-20 LCC-20 SOIC-16 Q QJA 80-120 90(1) 43-75(1) 70-80 50-120(1) QJC 28(2) 45 34 20(2) 35
Q
2
UC1825 UC2825 UC3825 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC = 15V, -55CUC1825 UC2825 MIN TOP MAX 5.05 5.10 2 5 0.2 50 5 -50 400 0.2 5 5.15 20 20 0.4 5.20 25 -100 440 2 460 4.5 2.3 2.8 1.0 1.8 UC3825 MIN 5.00 TOP 5.10 2 5 0.2 50 5 -50 400 0.2 5 MAX UNITS 5.20 20 20 0.4 5.25 25 -100 440 2 460 4.5 2.3 2.8 1.0 1.8 V mV mV mV/C V V mV mA kHz % % kHz V V V V V mV A A dB dB dB mA mA V V MHz V/s
PARAMETERS Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability* Total Output Variation* Output Noise Voltage* Long Term Stability* Short Circuit Current Oscillator Section Initial Accuracy* Voltage Stability* Temperature Stability* Total Variation* Oscillator Section (cont.) Clock Out High Clock Out Low Ramp Peak* Ramp Valley* Ramp Valley to Peak* Error Amplifier Section Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain CMRR PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth* Slew Rate*
TEST CONDITIONS
TO = 25C, IO = 1mA 10V < VCC < 30V 1mA < IO < 10mA TMIN < TA < TMAX Line, Load, Temperature 10Hz < f < 10kHz TJ = 125C, 1000hrs. VREF = 0V TJ = 2C 10V < VCC < 30V TMIN < TA < TMAX Line, Temperature
5.00
4.95
-15 360
-15 360
340 3.9 2.6 0.7 1.6
340 3.9
2.9 3.0 1.25 2.0 10 3 1
2.6 0.7 1.6
2.9 3.0 1.25 2.0 15 3 1
1V < VO < 4V 1.5V < VCM < 5.5V 10V < VCC < 30V VPIN 3 = 1V VPIN 3 = 4V IPIN 3 = -0.5mA IPIN 3 = 1mA
60 75 85 1 -0.5 4.0 0 3 6
0.6 0.1 95 95 110 2.5 -1.3 4.7 0 .5 5.5 12
5.0 1.0
60 75 85 1 -0.5 4.0 0 3 6
0.6 0.1 95 95 110 2.5 -1.3 4.7 0.5 5.5 12
5.0 1.0
3
UC1825 UC2825 UC3825 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC
= 15V, -55CPARAMETERS
TEST CONDITIONS
UC3825 MIN TOP -1 0 1.1 1.25 50 9 MAX UNITS -5 85 80 20 A % V ns A mA A V V ns V V V V A ns V V mA mA
PWM Comparator Section Pin 7 Bias Current VPIN 7 = 0V Duty Cycle Range Pin 3 Zero DC Threshold VPIN 7 = 0V Delay to Output* Soft-Start Section Charge Current VPIN 8 = 0.5V Discharge Current VPIN 8 = 1V Current Limit / Shutdown Section Pin 9 Bias Current 0 < VPIN 9 < 4V Current Limit Threshold Shutdown Threshold Delay to Output Output Section Output Low Level IOUT = 20mA IOUT = 200mA Output High Level IOUT = -20mA IOUT = -200mA Collector Leakage VC = 30V Rise/Fall Time* CL = 1nF Under-Voltage Lockout Section Start Threshold UVLO Hysteresis Supply Current Section Start Up Current VCC = 8V ICC VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V
3 1
0.9 1.25
1.0 1.40 50 0.25 1.2 13.5 13.0 100 30 9.2 0.8 1.1 22
15 1.1 1.55 80 0.40 2.2
0.9 1.25
1.0 1.40 50 0.25 1.2 13.5 13.0 10 30 9.2 0.8 1.1 22
10 1.1 1.55 80 0.40 2.2
13.0 12.0
13.0 12.0 500 60 9.6 1.2 2.5 33 8.8 0.4
500 60 9.6 1.2 2.5 33
8.8 0.4
4
Printed Circuit Board Layout Considerations
High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1825 follow these rules: 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1 Amp Schottky diode at the output pin will serve
UC1825 UC2825 UC3825
this purpose. 3) Bypass VCC, VC, and VREF. Use 0.1F monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, CT, like a bypass capacitor.
Error Amplifier Circuit
Simplified Schematic
Open Loop Frequency Response
Unity Gain Slew Rate
PWM Applications
Conventional (Voltage Mode) Current-Mode
5
Oscillator Circuit
Deadtime vs CT (3k RT 100k)
UC1825 UC2825 UC3825
Timing Resistance vs Frequency
160 140
Deadtime vs Frequency
1.0nF
TD (ns)
120 100 470pF 80 10k 100k 1M
FREQ (Hz)
Synchronized Operation
Two Units in Close Proximity
Generalized Synchronization
6
Forward Technique for Off-Line Voltage Mode Application
UC1825 UC2825 UC3825
Constant Volt-Second Clamp Circuit
The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime.
Output Section
Simplified Schematic Rise/Fall Time (CL=1nF)
Rise/Fall Time (CL=10nF)
Saturation Curves
7
Open Loop Laboratory Test Fixture
UC1825 UC2825 UC3825
UDG-92032-2
This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and byUC1825's functions and measuring their specifications. pass procedures should be followed. The use of a ground plane is highly recommended.
Design Example: 50W, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency
UDG-92033-3
8
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2005
PACKAGING INFORMATION
Orderable Device 5962-87681012A 5962-8768101EA 5962-8768101QFA 5962-8768101V2A 5962-8768101VEA UC1825J UC1825J883B UC1825JQMLV UC1825L UC1825L883B UC1825LQMLV UC1825W883B UC2825DW UC2825DW/1 UC2825DWTR UC2825DWTRG4 UC2825J UC2825N UC2825NG4 UC2825Q UC2825QTR UC3825DW UC3825DWG4 UC3825DWTR UC3825DWTRG4 UC3825J UC3825N UC3825NG4 UC3825Q UC3825QTR Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PREVIEW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type LCCC CDIP CFP LCCC CDIP CDIP CDIP CDIP LCCC LCCC LCCC CFP SOIC SOIC SOIC SOIC CDIP PDIP PDIP PLCC PLCC SOIC SOIC SOIC SOIC CDIP PDIP PDIP PLCC PLCC Package Drawing FK J W FK J J J J FK FK FK W DW DW DW DW J N N FN FN DW DW DW DW J N N FN FN Pins Package Eco Plan (2) Qty 20 16 16 20 16 16 16 16 20 20 20 16 16 16 16 16 16 16 16 20 20 16 16 16 16 16 16 16 20 20 1 40 1 1 1 1 1 1 1 1 1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 25 25 46 TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3)
POST-PLATE Level-NC-NC-NC A42 SNPB A42 SNPB Call TI Call TI A42 SNPB A42 SNPB Call TI Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Call TI
POST-PLATE Level-NC-NC-NC POST-PLATE Level-NC-NC-NC Call TI A42 SNPB CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 SNPB CU NIPDAU CU NIPDAU CU SN CU SN CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 SNPB CU NIPDAU CU NIPDAU CU SN CU SN Call TI Level-NC-NC-NC Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-NC-NC-NC Level-NC-NC-NC Level-NA-NA-NA Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR Level-2-260C-1 YEAR
1000 Green (RoHS & no Sb/Br) 40 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 25 25 46 TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
1000 Green (RoHS & no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2005
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B - OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
1
2
3
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A - OCTOBER 1994
FN (S-PQCC-J**)
20 PIN SHOWN
PLASTIC J-LEADED CHIP CARRIER
Seating Plane 0.004 (0,10) D D1 3 1 19 0.032 (0,81) 0.026 (0,66) 4 18 D2 / E2 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) 0.020 (0,51) MIN
E
E1 D2 / E2 8 14
0.050 (1,27) 9 13 0.008 (0,20) NOM
0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M
NO. OF PINS ** 20 28 44 52 68 84
D/E MIN 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 0.785 (19,94) 0.985 (25,02) 1.185 (30,10) MAX 0.395 (10,03) 0.495 (12,57) 0.695 (17,65) 0.795 (20,19) 0.995 (25,27) 1.195 (30,35) MIN
D1 / E1 MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.756 (19,20) 0.958 (24,33) 1.158 (29,41) MIN
D2 / E2 MAX 0.169 (4,29) 0.219 (5,56) 0.319 (8,10) 0.369 (9,37) 0.469 (11,91) 0.569 (14,45) 4040005 / B 03/95
0.350 (8,89) 0.450 (11,43) 0.650 (16,51) 0.750 (19,05) 0.950 (24,13) 1.150 (29,21)
0.141 (3,58) 0.191 (4,85) 0.291 (7,39) 0.341 (8,66) 0.441 (11,20) 0.541 (13,74)
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
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