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(R)
HI2559, CXD2559
DED ME N M FO R DES NEW S IG N
October 1997
1-Bit D/A Converter For Audio Application
Description
The HI2559, CXD2559 is a 1-bit stereo D/A converter featuring a 2nd-order system noise shaper. This good cost performance LSI has functions such as digital attenuator and digital de-emphasis and others.
Features
NO
CO T RE
* Two-Channel D/A Converter and Oversampling Digital Filter Into a Single Chip * Distortion . . . . . . . . . . . . . . . . . . . . . . . . 0.012% or Less * S/N Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . .96dB or More * Master Clock . . . . . . . . . . . . . . . . . . . . . 384FS or 256FS
Ordering Information
PART NUMBER HI2559JCQ CXD2559Q TEMP. RANGE ( oC) -20 to 75 -20 to 75 PACKAGE 32 Ld MPQF 32 Ld MPQF PKG. NO. Q32.7x7-S Q32.7x7-S
Applications
* CD Player and CD-ROM Player, etc.
Functions
* Data Can Be Input at Rate of 1 x FS with a Built-In Digital Filter * The 24-/32-Slot Serial Data Interface Enables Independent Selection of Data Frontward Truncation/Rearward Truncation and MSB First/LSB First * Two Channels Can Be Attenuated Independently in 255 Steps * The Output From Two Channels (L/R/L + R/Mute) Can Be Selected Independently * Digital Emphasis
Pinout
HI2559, CXD2559 (MQFP) TOP VIEW
AOUT2+ AVSS3 XVSS XTLI XTLO XVDD AVSS2 AOUT1+ AVDD0 AOUT2AVSS0 DVDD0 TEST CLR MASL DVSS0 3231 30 29 28 27 26 25 1 24 2 23 3 22 4 21 5 20 6 19 18 7 17 8 9 10 11 12 13 14 15 16
AVDD1 AOUT1AVSS1 DVSS1 XCLK DASL0 DASL1 DVDD1
LRCK BCK SIN MLSL ATT SHIFT LATCH WO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 4-1
File Number
4120.1
HI2559, CXD2559 Block Diagram
XTLI XTLO XCLK
CLOCK GENERATOR TIMING CIRCUIT
AOUT1 (+) DAC1 LRCK BCK SIN MASL MLSL S P DAC2 AOUT2 (-) DIGITAL FILTER (OVER SAMPLING) AOUT1 (-) AOUT2 (+)
ATT SHIFT LATCH
HOST COMPUTER I/F
ROM
ATT1
ATT2
RAM
Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 SYMBOL AVDD0 AOUT2(-) ADV SS0 DVDD0 TEST CLR MASL I/O O I I I DESCRIPTION Analog power supply for Channel 2 output. Analog reversed phase output for Channel 2. Analog GND for Channel 2 output. Digital power supply. IC measurement. Fixed to Low. System clear input. Cleared when low. Equipped with a pull-up resistor. Selects whether 16-bit serial data is placed in the first 16-bit or the second 16-bit slot of the serial IN 32-bit slots. Frontward truncation when High; rearward truncation when low. Equipped with a pulldown resistor. Digital GND. Serial IN sampling frequency clock. Transfers Channel-1 data when High; Channel-2 data when low. Serial bit transfer clock 48 FS or 64 FS in serial IN. The serial input data is retrieved at the rising edge. Two channels per sampling serial data input. Data format is represented by 2's complements, and consists of 24-bit or 32-bit slots. Selects whether 16-bit serial data SIN (Pin 15) of serial IN at LSB first or MSB first. MSBfirst when High; LSB-first when Low. Equipped with a pull-up resistor.
8 9 10 11 12
DV SS0 LRCK BCK SIN MLSL
I I I I
4-2
HI2559, CXD2559 Pin Descriptions
PIN NO. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ATT SHIFT LATCH WO DVDD1 DASL1 DASL0 XCLK DV SS1 AV SS1 AOUT1 (-) AVDD1 AOUT1 (+) AV SS2 XVDD XTLO XTLI XVSS AV SS3 AOUT2 (+) (Continued) I/O I I I I I I O O I O O I O DESCRIPTION Data input of the microcomputer interface. Attenuation data, output selection setting value, and de-emphasis on/off data re-input in serial mode. Shift clock input of the microcomputer interface. Latch input of the microcomputer interface. Latched at the rising edge. Synchronization window control. Window open when Low (forced synchronization). Digital power supply. IC measurement. Fixed to Low. IC measurement. Fixed High. Inversion output of the clock input from XTLI (Pin 1). Digital GND. Analog GND for Channel 1 output. Analog reversed phase output for Channel 1. Analog power supply for Channel 1 output. Analog positive phase output for Channel 1. Analog GND for Channel 1 output. Digital power supply for the master clock. Crystal oscillator output. Connects the master clock 256 FS or 384 FS crystal oscillator, which is identified automatically. Crystal oscillator input. Connects the master clock 256 FS or 384 FS crystal oscillator, which is identified automatically. External clock pulse is input at this pin. Digital GND for master clock Analog GND for Channel 2 output. Analog positive phase output for Channel 2.
SYMBOL
4-3
HI2559, CXD2559
Absolute Maximum Ratings TA = 25oC, VSS = 0V
Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . VSS -0.5V to 7.0V Input Voltage (V 1). . . . . . . . . . . . . . . . . . . . VSS -0.5V to V DD +0.5V Output Voltage (V 0) . . . . . . . . . . . . . . . . . . VSS- 0.5V to VDD +0.5V Operating Temperature (TOPR). . . . . . . . . . . . . . . . . -20oC to 75oC Storage Temperature (TSTG) . . . . . . . . . . . . . . . . . . -55oC to 150oC
Operating Conditions
Supply Voltage (V DD) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . 20oC to 75oC Sampling Frequency (FS) . . . . . . . . . . . . . . . . . . . . . 7kHz to 50kHz
Input/Output Capacitance
Input Pin (CIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9pF (Max.) Output Pin (COUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11pF (Max.) Measurement conditions: V DD = VI = 0V, f = 1MHz
Electrical Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS APPLICABLE PIN
DC Electrical Specifications
Input Voltage VIH VIL VIH V IL Output Voltage V OH VOL VOH VOL V OH VOL Input Leakage Current 1 Input Leakage Current 2 Input Leakage Current 3 Input Leakage Current 4 Feedback Resistance NOTES: 1. Input pins except for *2t 2. ATT, SHIFT, LATCH 3. XCLK 4. XLO 5. AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-) 6. ATT, SHIFT, LATCH, LRCK, BCK, SINt 7. WO 8. CLR, MLSLt 9. MASL 10. XTLI AC Electrical Specifications PARAMETER Oscillation Frequency 256 FS 384 FS External Clock Pulse Input High Level Width 258 FS 384 FS tCWH VDD = 5.0 10%, TOPR = -20oC to 75oC SYMBOL fx 2 2 38 25 13 20 250 250 ns ns MHz IIL1 IIL2 IIL IIH RFB IOH = -2mA IOL = 4mA IOH = -1mA IOL = 1mA IOH = -4mA IOL = 4mA VIN = VSS or VDD VIN = VSS or VDD VIL = VSS VIH = VDD VIN = VSS or VDD VDD -0.8 VDD /2 VDD -0.8 0 -10 -40 -40 40 250k -100 100 1M 0.4 0.4 VDD /2 10 40 -240 240 2.5M A A A A Note 6 Note 7 Note 8 Note 9 Note 12 V Note 5 V Note 4 V Note 3 0.7 VDD 2.2 0.3 VDD V Note 2 V Note 1
4-4
HI2559, CXD2559
AC Electrical Specifications PARAMETER External Clock Pulse Input Low Level Width External Clock Pulse Input Pulse Cycle (Note 2) Input BCK Frequency Input BCK Pulse Width Input Data Setup Time Input Data Hold Time Input LRCK Setup Time Input LRCK Hold Time Program Input Basic Time Latch Input Pulse Width ATT Setup Time ATT Hold Time ATT Interval NOTE: 11. Always input an external clock after turning the power on. ANALOG CHARACTERISTICS MEASUREMENT CONDITIONS S/N THD + N Dynamic Range Channel Separation Output Level Gain Difference Between Channels NOTES: 12. A-weighting filter used. 13. -60dB, 1kHz input. TA = 25oC, VDD = 5.0V, FS = 44kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, Master Clock 384FS. (EIAJ) *1 (EIAJ) (EIAJ) *1, *2 (EIAJ) 96 91 100 0.010 93 90 2.58 0.012 0.1 dB % dB dB V (ms) dB 256 FS 384 FS 256 FS 384 FS fBCK tWIB tIDS tIDH tILRS tILRH tPR tWLT tSET tHOLD tINT tCYC VDD = 5.0 10%, TOPR = -20oC to 75oC SYMBOL tCWL 38 25 76 50 100 10 15 10 15 100 200 5 100 300 250 250 500 500 3.1 ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns
4-5
HI2559, CXD2559
The analog characteristics are measured with the following circuit:
Test Circuits
820P CXD2559Q 3.9K 130K AOUT1 (-) 3.9K 3.9K 130K AOUT1 (+) 3.9K 4.7K 0.015 4.7K
+
47P
4.7K 4.7K 4.7K
+
4.7K 1800P
4.7K
+
22
100 OUTPUT
+
12K
82P
820P
+
47P
FIGURE 1. ANALOG CHARACTERISTICS
384FS
LRCK TEST DISC DATA CXD2500Q BCK DATA CXD2559Q
AOUT1 AOUT2 ANALOG CIRCUIT
ANALOG AUDIO ANALYZER (SHIBASOKU AM51A)
FIGURE 2.
Timing Diagrams
tCYC EXTERNAL CLOCK INPUT XTLI tWIB AUDIO INPUT BCK tIDS SIN tILRH LRCK PROGRAM INPUT ATT tSET tHOLD MSB tILAS tIDH 50% tWIB tCWH tCWL
SHIFT LATCH
tPR tPR tPR tWLT tINT
FIGURE 3. TIMING CHART
4-6
(32-BIT SLOT)
BCK CH-2 CH-1
Timing Diagrams
LRCK
MLSL = "H", MASL = "L" MSB INVALID
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSB INVALID
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Continued)
SIN
15
MLSL = "H", MASL = "H" MSB
0
LSB
0
SIN INVALID
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
INVALID
15
MLSL = "L", MASL = "L" INVALID
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LSB INVALID
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIN
15
HI2559, CXD2559
FIGURE 4. SERIAL DATA INTERFACE
4-7
LSB
7 8 9 10 11 12 13 14 15
MLSL = "L", MASL = "H" INVALID
0 1 2 3 4 6
MSB
7 8 9 10 11 12 13 14 15
SIN
0
1
2
3
4
6
INVALID
(24-BIT SLOT)
BCK CH-2 CH-1
LRCK
MLSL = "H" 15 14 13 12 11 10 9 8 7 6 5
MSB 4 3 2 1
LSB 0 INVALID 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIN
0
INVALID
MLSL = "L" LSB 0 1 2 3 4 5 6
MSB 7 8 9 10 11 12 13 14 15 INVALID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIN
0
INVALID
HI2559, CXD2559 Timing Diagrams
(Continued)
BYTE 0 LSB ATT MSB LSB
BYTE 1 MSB
BYTE 2 E A X X
L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 P0 P1 P2 P3
SHIFT 1 LATCH 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FIGURE 5.
Description of Functions
A. Crystal Oscillator Frequency Selection [Related pins] XTLI, XTLO, XCLK, BCK, SIN Although the 384 FS or 256 VS crystal oscillator can be connected to XTLI and XTLO, the selection is determined depending on whether the input serial data is 24-bit or 32-bit slot. The frequency of the crystal oscillator is output from XCLK as it is.
SERIAL DATA INPUT BIT RATE 24-Bit Slot (48FS) 32-Bit Slot (64FS) CRYSTAL OSCILLATOR FREQUENCY 384FS 256FS XCLK OUTPUT 384FS 256FS
B. Serial Data Interface [Related pins] LRCK, BCK, SIN, MASL, MLSL The serial data format consists of two channels per sampling serial data represented by 2's complement. In each channel, the data is processed as a 24-bit slot when the crystal oscillator frequency is 384 FS, and as a 32-bit slot when the crystal oscillator frequency is 256 FS . 16 of these bits are used as data. MSL is used to select whether the serial data is arranged at LSB first or MSB first. Also, MASL is used to select whether the 16-bits of valid data is placed in the first or the second half of the 32-bit slot.
MSL H MSB First LSB First 24-BIT SLOT Rearward Truncation 32-BIT SLOT Frontward Truncation Rearward Truncation
CXD2500BQ DA16 DA15 LRCK XTAI 24-SLOT 48FS IFS 384FS
CXD2559Q SIN BCK LRCK XCLK XTLO XTLI 384FS
L MASL H L
C. Control Mode
CXD2507Q PCMD BCK LRCK XTAI 24-SLOT 48FS IFS 384FS CXD2559Q SIN BCK LRCK XCLK XTLO XTLI 384FS
[Related pins] ATT, SHIFT, LATCH The serial ports of ATT, SHIFT and LATCH are used to control functions such as the digital attenuator, output selection and digital de-emphasis. Data consists of 24-bits (3 bytes), which have the following meanings:
FIGURE 6. CONNECTION EXAMPLE FOR THE CD DSP
4-8
HI2559, CXD2559
CONTROL BIT L7 TO L0 R7 to R0 P3 to P0 E
CONTROL The L channel attenuation data. The R channel attenuation data. Output selection.
WHEN SYSTEM IS CLEARED FF (H) FF (H) 9 (H) Stereo
De-emphasis (High = on, Low = off) OFF However, the time constant of the emphasis is 1 = 50s and 2 = 15s when FS = 44.1kHz. The de-emphasis function cannot be used when FS is not 44.1kHz. Attenuate (Low = independent, High = common). However, the L channel Independent attenuation value is used when the L and R channels are commonly attenuated. Don't care.
A
X
NOTE: When the data is more than three bytes are transferred to the ATT pin, only the three bytes transferred finally are effective.
D. Digital Attenuator [Related pins] ATT, SHIFT, LATCH The output data can be attenuated independently in the L and R channels, using the transfer data from the external microcomputer. The ATT data of the L and R channels consist of eight bits each, and the L and R channels can be attenuated commonly using the ATT control bit. (The L channel attenuation value is used when the L and R channels are commonly attenuated). (1) Command and Audio Output The attenuation data of the L and R channels consist of eight bits, it can be set 255 ways. The following table shows the relationship between the commands and the outputs.
ATTENUATION DATA L7 TO L0/R7 TO R0 FF (H) FE (H) 01 (H) 00 (H) AUDIO OUTPUT 0dB -0.034dB -48.131dB -
(FS = 44kHz for CD).
0dB A ATT1 B ATT3
C ATT2
FIGURE 7. METHOD OF OBTAINING AN ATTENUATION VALUE
F. Output Selection [Related pins] ATT, SHIFT, LATCH The L and R channel outputs can be set in four combinations [L/RL + R/Mute] (16 ways in total) using the transfer data from the external microcomputer. The following table shows the relationship between the commands and the outputs.
The attenuation values for 01 (H) to FE (H) can be obtained with the following equation:
ATT = 20log [Input data/255] dB Ex. for attenuating data FA (H) ATT = 20log [250/255] db = 0.172dB
E. Digital Attenuator Suppose that there are attenuation data ATT1, ATT2 and ATT3, and their relationship is ATT1>ATT3>ATT2. When ATT2 is transferred before the level reaches the value of ATT1 (point A in the figure), the level keeps approaching to the value of ATT2. Next, when ATT3 is transferred before the level reaches the value of ATT2 (point B or C in the figure), the level starts approaching to the value of ATT3 from its level at that time (point B or C in the figure). The transition (0 dB to -) between the attenuation data is 1024/FS
4-9
HI2559, CXD2559
P0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 P2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 L CHANNEL OUTPUT Mute Mute Mute Mute R R R R L L L L L+R L+R L+R L+R R CHANNEL OUTPUT Mute R L L+R Mute R L L+R Mute R L L+R Mute R L L+R Mono Stereo Reverse REMARKS Mute
NOTE: For L + R, the output data is (L + R)/2 to avoid overflow.
G. I/O Sync Circuit [Related pins] LRCK and WO (1) Operation (When the WO Pin is "H") The synchronization circuit has the window of eight clocks of the master clock and it monitors whether the rising edge of LRCK is in the window. If the rising edge of LRCK is out of the window, resynchronization is automatically performed. (2) Forced Synchronization by WO Pin Even if the rising edge of LRCK is within the window, it may not synchronize owing to the mixing of the external noises, etc. when the rising edge of LRCK is positioned near at both edges of the window.
When the power is turned on, it is necessary to set the rising edge of LRCK in the center of the window by performing the forced synchronization. After the system is cleared, the forced synchronization is performed by setting WO pin to Low at 2/F S or more. The forced synchronization is performed at the second rising edge of LRCK after the WO pin is turned to "Low."
NOTE: WO pin must be "H" except the forced synchronization.
H. System Clear When the Power is Turned ON. [Related Pins] CLR When the power is turned ON and the master clock more than 4 clocks is input to the XTLI pin, set the CLR pin from "L" to "H."
4-10
A C 0.01 3.9K 130K 3 3.9K 0.01 0.01 3.9K 8765 5 3.9K 47P 47P 820P 5 VSS VSS MASL CLR TEST VDD AOUT 2 (-) VDD 1800P 4 32 1 130K 6 7 4.7K 7 6 4.7K 820P 47K 0.01 0.01 2 D 47K +12V
+5V POWER SUPPLY FOR THE XTAL OSCILLATOR CIRCUIT
B
+5V POWER SUPPLY FOR AOUT1
C
+5V POWER SUPPLY FOR AOUT2
D
+5V DIGITAL POWER SUPPLY
ANALOG GND
DIGITAL GND
Application Circuit
4558 IS USED FOR OPERATIONAL AMPLIFIER 4
+
81
+
+
4.7K
4.7K 4.7K
2 3
+
82P
8 4
1 0.01
22
100 12K CH2 OUT
CXD2500Q LRCK LRCK DA15 8CK XTAI DA16 SIN 9 32 31 30 29 28 27 26 VDD 25 20p 20p A 384FS OR 256FS 10 11
VDD
DASL1 DASL0
XCLK VSS VSS
AOUT 1 (-)
4-11
12 13 14 15 16 17 18 19 20 21 22 23 24 0.01 3.9K 6 130K 7 4.7K 5
ATT
SHIFT
LATCH CLR
LRCK BCK SIN MLSL ATT SHIFT LATCH WO
AOUT2 (+) VSS VSS XTLI CXD2559Q XTLO VDD VSS AOUT 1 (+)
NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
MICROCOMPUTER ATT SHIFT LATCH CLR WO
WO
0.01
0.01 3.9K
+
5 47P
4.7K 820P 0.01 4.7K
6
+
4.7K
7
4.7K
4.7K 1800P
0.015 4.7K 2 3
+
82P
8
1 4
22
100
CH1 OUT 12K 0.01 820P
MASL MLSL
3.9K 3.9K B
130K 3
2
+
47P
81 4 0.01 -12V

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