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256K x 32 CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7MP4045 IDT7MP4145
FEATURES:
* High density 1 megabyte static RAM module (IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120) * Low profile 64 pin ZIP (Zig-zag In-line vertical Package) or 64 pin SIMM (Single In-line Memory Module) for IDT7MP4045 and 72 pin SIMM (Single In-line Memory Module) for IDT7MP4145 * Very fast access time: 15ns (max.) * Surface mounted plastic components on an epoxy laminate (FR-4) substrate * Single 5V (10%) power supply * Multiple GND pins and decoupling capacitors for maximum noise immunity * Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7MP4045/4145 is a 256K x 32 static RAM module constructed on an epoxy laminate (FR-4) substrate using 8 256K x 4 static RAMs in plastic SOJ packages. Availability of four chip select lines (one for each group of two RAMs) provides byte access. The IDT7MP4045 is available with access time as fast as 10ns with minimal power consumption. The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zigzag In-line vertical Package)or a 64 pin SIMM (Single In-line Memory Module) where as the 7MP4145 is packaged in a 72 pin SIMM (Single In-line Memory Module). The 4045 ZIP configuration allows 64 pins to be placed on a package 3.65 inches long and 0.365 inches wide. The 7MP4045 ZIP is only 0.585 inches high, this low profile package is ideal for systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the module. All inputs and outputs of the IDT7MP4045/4145 are TTLcompatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use. Identification pins are provided for applications in which different density versions of the module are used. In this way, the target system can read the respective levels of PD pins to determine a 256K depth. The contact pins are plated with 100 micro-inches of nickel covered by 30 micro-inches minimum of selective gold.
PIN CONFIGURATION - 7MP4045(1)
1
PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 ZIP, 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
WE
CS1 CS3
A14
GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15
PD0 - GND PD1 - GND
FUNCTIONAL BLOCK DIAGRAM
CS1 CS2 CS3 CS4
ADDRESS
18 2
SIMM TOP VIEW 33
35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
CS2 CS4
A17
PD
A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND
OE
WE OE
8
256K x 32 RAM
I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31
2703 drw 01
8
8
8
2703 drw 02
I/O0-31
PIN NAMES
I/O0-31 A0-17 Data Inputs/Outputs Addresses Chip Selects Write Enable Output Enable Depth Identification Power Ground No Connect
2703 tbl 01
CS1-4 WE OE
PD0-1 VCC GND NC
NOTE: 1. Pins 2 and 3 (PD0 and PD1) are read by the user to determine the density of the module. If PD0 reads GND and PD1 reads GND, then the module has a 256K depth.
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
SEPTEMBER 1996
DSC-2703/7
15.2
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IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN(C) CIN(A) CI/O Parameter(1) Input Capacitance (CS) Input Capacitance (Address & Control) I/O Capacitance Conditions V(IN) = 0V V(IN) = 0V V(OUT) = 0V Max. 20 70 12 Unit pF pF pF
2703 tbl 02
PIN CONFIGURATION - 7MP4145(1)
NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 WE 32 A14 34 CS1 36
CS3
NOTE: 1. This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. 5.5 0 6.0 0.8
Unit V V V V
2703 tbl 03
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
SIMM TOP VIEW
NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15
CS2 CS4
PD0 - GND PD1 - GND PD2 - OPEN PD3 - OPEN
NOTE: 1. VIL (min) = -1.5V for pulse width less than 10ns.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Ambient Temperature 0C to +70C GND 0V VCC 5.0V 10%
2703 tbl 04
TRUTH TABLE
Mode Standby Read Write Read
CS OE WE
Output High-Z DATAOUT DATAIN High-Z
Power Standby Active Active Active
2703 tbl 05
A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND NC NC
38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
A17
OE
I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 NC NC
2703 drw 15
H L L L
X L X H
X H L H
NOTE: 1. Pins 3,4,6,and 7 (PD0-3) are read by the user to determine the density of the module. If PD0, PD1 read GND and PD2, PD3 read OPEN, then the module has a 256K depth.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Value -0.5 to +7.0 0 to +70 -10 to +85 -55 to +125 50 Unit V C C C mA
NOTE: 2703 tbl 06 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
15.2
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IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = 0C to +70C)
Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage (Address and Control) Input Leakage (Data) Output Leakage Output LOW Output HIGH Test Conditions VCC = Max.; VIN = GND to VCC VCC = Max.; VIN = GND to VCC VCC = Max.; CS = VIH, VOUT = GND to VCC VCC = Min., IOL = 8mA VCC = Min., IOH = -4mA Min. -- -- -- -- 2.4 Max. 80 10 10 0.4 -- Unit A A A V V
2703 tbl 07
Symbol ICC ISB ISB1
Parameter Dynamic Operating Current Standby Supply Current Full Standby Supply Current
Test Conditions f = fMAX; CS = VIL VCC = Max.; Output Open
CS VIH, VCC = Max. Outputs Open, f = fMAX CS VCC - 0.2V; f = 0 VIN > VCC - 0.2V or < 0.2V
Max. 1360 480 120
Unit mA mA mA
2703 tbl
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1-4
2703 tbl 09
+5 V
+5 V
480 DATAOUT
480 DATAOUT
255
30 pF*
255
5 pF*
*Includes scope and jig. Figure 1. Output Load
2703 drw 03
2703 drw 04
Figure 2. Output Load (for tOLZ,tOHZ, tCHZ, tCLZ, tWHZ, tOW)
15.2
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IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = 0C to +70C)
'4045SxxZ, '4045/4145SxxM -15 Symbol tRC tAA tACS tCLZ(1) tOE tOLZ(1) tCHZ(1) tOHZ tOH tPU tPD
(1) (1) (1)
-20 Max. -- 15 15 -- 8 -- 8 8 -- -- 15 -- -- -- -- -- -- 8 -- -- -- Min. 20 -- -- 5 -- 0 -- -- 3 0 -- 20 15 15 0 15 0 -- 12 0 0 Max. -- 20 20 -- 10 -- 10 10 -- -- 20 -- -- -- -- -- -- 13 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2703 tbl 11
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Output Enable to Output Valid Output Enable to Output in Low-Z Chip Deselect to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time
Min. 15 -- -- 3 -- 0 -- -- 3 0 -- 15 12 12 0 12 0 -- 10 0 0
Read Cycle
Write Cycle tWC tCW tAW tAS tWP tWR tWHZ tDW tDH tOW(1)
(1)
Write Enable to Output in High-Z Data to Write Time Overlap Data Hold from Write Time Output Active from End-of-Write
NOTE: 1. This parameter is guaranteed by design but not tested.
15.2
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IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
tOE
CS
tOH
tOLZ tACS tCLZ (5)
(5)
tOHZ tCHZ
(5)
(5)
DATA OUT
2703 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID t OH DATA VALID
2703 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
tACS tCLZ DATAOUT
(5)
tCHZ
(5)
2703 drw 06
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected. CS = VIL. 3. Address valid prior to or coincident with CS transition LOW. 4. OE = VIL. 5. Transition is measured 200mV from steady state. This parameter is guaranteed by design, but not tested.
15.2
5
IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (1, 2, 3, 7) WE
tWC ADDRESS
OE
tAW
CS
tAS
WE
tWP (7)
tWR
tWHZ tOHZ DATA OUT
(4) (6)
(6)
tOHZ tOW(6)
(4)
(6)
tDW DATA IN DATA VALID
tDH
2703 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED) (1, 2, 3, 5) CS
tWC ADDRESS tAW
CS
tAS
WE
tCW
tWR
tDW DATAIN DATA VALID
tDH
2703 drw 11
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
15.2
6
IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS 7MP4045 ZIP VERSION
3.640 3.660 0.585 MAX. COMPONENT AREA 0.100 TYP. 0.100 TYP. FRONT VIEW 0.050 TYP. 0.125 0.190 SIDE VIEW 0.365 MAX.
PIN 1
0.015 0.025
0.250 TYP.
COMPONENT AREA
BACK VIEW
PIN 1
2703 drw 12
7MP4045 SIMM VERSION
3.840 3.860 3.580 3.588
0.365 MAX.
0.630 MAX.
COMPONENT AREA
0.390 0.410 0.050 TYP. 0.045 0.055 SIDE VIEW
0.240 0.260
0.250 TYP. PIN 1 FRONT VIEW
COMPONENT AREA
BACK VIEW
PIN 1
2703 drw 13
15.2
7
IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
7MP4145 SIMM VERSION
4.240 4.260 3.974 3.994 0.350 MAX.
0.640 0.660 0.240 0.260 0.250 TYP. FRONT VIEW 0.050 TYP.
0.390 0.410 0.045 0.055 SIDE VIEW
PIN 1 0.070 0.090
BACK VIEW
PIN 1
2703 drw 16
ORDERING INFORMATION
IDT XXXXX Device Type X Power X Speed X Package X Process/ Temperature Range Blank Z M Commercial (0C to +70C)
FR-4 ZIP (Zig-Zag In-line vertical Package, 7MP4045 only) FR-4 SIMM (Single In-line Memory Module)
15 20
Speed in Nanoseconds
S
Standard Power 256K x 32 Static RAM Module 256K x 32 Static RAM Module
2703 drw 14
7MP4045 7MP4145
15.2
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