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TC835
Personal Computer Data Acquisition A/D Converter
Features
* * * * * * * * Upgrade of Pin-Compatible TC7135, ICL7135 200kHz Operation Single 5V Operation With TC7660 Multiplexed BCD Data Output UART and Microprocessor Interface Control Outputs for Auto-Ranging Input Sensitivity: 100V No Sample and Hold Required
General Description
The TC835 is a low power, 4-1/2 digit (0.005% resolution), BCD analog to digital converter (ADC) that has been characterized for 200kHz clock rate operation. The five conversions per second rate is nearly twice as fast as the ICL7135 or TC7135. The TC835, like the TC7135, does not use the external diode resistor rollover error compensation circuits required by the ICL7135. The multiplexed BCD data output is perfect for interfacing to personal computers. The low cost, greater than 14-bit high-resolution and 100V sensitivity makes the TC835 exceptionally cost-effective. Microprocessor-based data acquisition systems are supported by the BUSY and STROBE outputs, along with the RUN/HOLD input of the TC835. The OVERRANGE, UNDERRANGE, BUSY and RUN/ HOLD control functions, plus multiplexed BCD data outputs, make the TC835 the ideal converter for Pbased scales, measurement systems and intelligent panel meters. The TC835 interfaces with full function LCD and LED display decoder/drivers. The UNDERRANGE and OVERRANGE outputs may be used to implement an auto-ranging scheme or special display functions.
Applications
* Personal Computer Data Acquisition * Scales, Panel Meters, Process Controls * HP-IL Bus Instrumentation
Device Selection Table
Part Number TC835CBU TC835CKW TC835CPI Note: Package 64-PinPQFP 44-PinPQFP 28-Pin PDIP Temperature Range 0C to +70C 0C to +70C 0C to +70C
Tape and Reel available for 44-Pin PQFP package.
2002 Microchip Technology Inc.
DS21478B-page 1
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TC835
Package Type
28-Pin PDIP
V- 1 REF IN 2 ANALOG 3 COM INT OUT 4 AZ IN 5 BUFF OUT 6 C REF- 7 CREF+ 8 -INPUT
9 28 UNDERRANGE
44-Pin PQFP
NC ANALOG COMMON REF IN STROBE
OR
NC
NC
UR
NC
26 STROBE 25 RUN/HOLD 24 DIGTAL GND 23 POLARITY
44 43 42 41 40 39 38 37 36 35 34
NC 1 INT OUT 2 AZ IN 3 BUFF OUT 4 REF CAP- 5 REF CAP+ 6 -INPUT 7 +INPUT 8 V+ 9 NC 10 NC 11
12 13 14 15 16 17 18 19 20 21 22
NC
33 NC 32 NC 31 RUN/HOLD 30 DGND 29 POLARITY 28 CLK IN 27 BUSY 26 D1 (LSD) 25 D2 24 NC 23 NC
TC835CPI
22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2 18 D3 17 D4 16 B8 (MSD) 15 B4
+INPUT 10 V+ 11 (MSD) D5 12 (LSB) B1 13 B2 14
TC835CKW
NC
NC
B2
B4
V-
27 OVERRANGE
D4
D3
NC
(MSD) D5
(LSB) B1
64-Pin PQFP
RUN/HOLD STROBE CLK IN DGND
BUSY
SUB
POL
NC NC
NC
NC
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 OVERRANGE 7 UNDERRANGE 8 SUB 9 V- 10 REF IN 11 ANALOG COM 12 NC 13 NC 14 NC 15 NC 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC
D1
D2
48 NC 47 NC 46 NC 45 D3 44 D4 43 B3 42 B4 41 B2 40 SUB 39 B1 38 D5 37 NC 36 NC 35 NC 34 NC 33 NC
TC835CBU
BUFFOUT
INT OUT NC
AZ IN
NC
NC
BUF CAP- NC
BUF CAP+
NOTES: 1. NC = No internal connection. 2. Pins 9, 25, 40 and 56 are connected to the die substrate. The potential at these pins is approximately V+. No external connections should be made.
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DS21478B-page 2
+INPUT
SUB
NC
-INPUT NC
NC
V+
(MSB) B8
2002 Microchip Technology Inc.
NC
TC835
Typical Application
Address Bus Control Data Bus +5V
V+ REF CAP PA0 PA1 PA2 HCTS157 1Y 1B 2B 2Y 3Y 3B S 1A 2A 3A BUF AZ POL OR INT UR D5 B8 INPUT+ B4 B2 TC835 B1 D1 VR D2 Input D3 D4 Analog STB Common R/H FIN DGND FIN - 5V REF Voltage +15V -15V
DG529 DA DB WR
Channel 1 Channel 2 Channel 3
R 6522 P PA3 PA4 PA5 PA6 PA7 CA1 CA2
Channel 4 A1 A0 EN Differential Multiplexer
PB0 PB1 PB2 PB3
Channel Selection
2002 Microchip Technology Inc.
DS21478B-page 3
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TC835
1.0 ELECTRICAL CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings*
Positive Supply Voltage......................................... +6V Negative Supply Voltage ........................................ -9V Analog Input Voltage (Pin 9 or 10) ... V+ to V- (Note 2) Reference Input Voltage (Pin 2) ..................... V+ to V- Clock Input Voltage ........................................ 0V to V+ Operating Temperature Range................0C to +70C Storage Temperature Range ............. -65C to +150C Package Power Dissipation (TA 70C) 28-Pin Plastic DIP ............................ 1.14 44-Pin PQFP .................................... 1.00 64-Pin PQFP .................................... 1.14
TC835 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: TA = +25C, FCLOCK = 200kHz, V+ = +5V, V- = -5V, unless otherwise specified. Symbol Analog Display Reading with Zero Volt Input TCZ TCFS NL DNL FSE IIN eN Digital IIL IIH VOL VOH Input Low Current Input High Current Output Low Voltage Output High Voltage; B1, B2, B4, B8, D 1 -D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency -- -- -- 2.4 4.9 0 10 0.08 0.2 4.4 4.99 200 100 10 0.4 5 5 1200 A A V V V kHz VIN = 0V VIN = +5V IOL = 1.6mA IOH = 1mA IOH = 10A Note 10 Zero Reading Temperature Coefficient Full-Scale Temperature Coefficient Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation Full Scale Symmetry Error (Rollover Error) Input Leakage Current Noise -0.0000 -- -- -- -- -- -- -- 0.0000 +0.0000 Display Reading Note 3, Note 4 0.5 -- 0.5 0.01 0.5 1 15 2 5 1 -- 1 10 -- V/C ppm/C Count LSB Count pA VP-P VIN = 0V, (Note 5) VIN = 2V; (Note 5, Note 6 Note 7 Note 7 -VIN = +VIN , (Note 8) Note 4 Peak to Peak Value not Exceeded 95% of Time Parameter Min Typ Max Unit Test Conditions
+0.9996 +0.9998 +1.0000 Display Reading VIN = VREF, (Note 3)
fCLK
Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10:
Functional operation is not implied. Limit input current to under 100 A if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 0C TA +70C. External reference temperature coefficient less than 0.01ppm/C. -2V VIN +2V. Error of reading from best fit straight line. |VIN| = 1.9959. Test circuit shown in Figure 1-1. Specification related to clock frequency range over which the TC835 correctly performs its various functions. Increased errors result at higher operating frequencies.
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DS21478B-page 4
2002 Microchip Technology Inc.
TC835
TC835 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: TA = +25C, FCLOCK = 200kHz, V+ = +5V, V- = -5V, unless otherwise specified. Symbol Power Supply V+ V- I+ I- PD Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation 4 -3 -- -- -- 5 -5 1 0.7 8.5 6 -8 3 3 30 V V mA mA m fCLK = 0Hz fCLK = 0Hz fCLK = 0Hz Parameter Min Typ Max Unit Test Conditions
Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10:
Functional operation is not implied. Limit input current to under 100 A if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 0C TA +70C. External reference temperature coefficient less than 0.01ppm/C. -2V VIN +2V. Error of reading from best fit straight line. |VIN| = 1.9959. Test circuit shown in Figure 1-1. Specification related to clock frequency range over which the TC835 correctly performs its various functions. Increased errors result at higher operating frequencies.
2002 Microchip Technology Inc.
DS21478B-page 5
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TC835
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number 28-Pin PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
PIN FUNCTION TABLE
Symbol VREF IN ANALOG COMMON INT OUT AZ IN BUFF OUT CREFCREF+ -INPUT +INPUT V+ D5 B1 B2 B4 B8 D4 D3 D2 D1 BUSY CLOCK IN POLARITY Negative power supply input. External reference input. Reference point for REF IN. Integrator output. Integrator capacitor connection. Auto zero input. Auto zero capacitor connection. Analog input buffer output. Integrator resistor connection. Reference capacitor input. Reference capacitor negative connection. Reference capacitor input. Reference capacitor positive connection. Analog input. Analog input negative connection. Analog input. Analog input positive connection. Positive power supply input. Digit drive output. Most Significant Digit (MSD) Binary Coded Decimal (BCD) output. Least Significant Bit (LSB) BCD output. BCD output. BCD output. Most Significant Bit (MSB) Digit drive output. Digit drive output. Digit drive output. Digit drive output. Least Significant Digit (LSD) Busy output. At the beginning of the signal-integration phase, BUSY goes High and remains High until the first clock pulse after the integrator zero crossing. Clock input. Conversion clock connection. Polarity output. A positive input is indicated by a logic High output. The polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. Digital logic reference input. Run / Hold input. When at a logic High, conversions are performed continuously. A logic Low holds the current data as long as the Low condition exists. Strobe output. The STROBE output pulses low in the center of the digit drive outputs. Over range output. A logic High indicates that the analog input exceeds the full scale input range. Under range output. A logic High indicates that the analog input is less than 9% of the full scale input range. Description
24 25 26 27 28
DGND RUN/HOLD STROBE OVERRANGE UNDERRANGE
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TC835
3.0
3.1
DETAILED DESCRIPTION
Dual Slope Conversion Principles
FIGURE 3-1:
(All Pin Designations Refer to 28-Pin DIP)
Analog Input Signal
BASIC DUAL SLOPE CONVERTER
Integrator Comparator + Clock Control Logic Counter VIN VREF VIN 1/2 VREF Variable Reference Integrate Time Switch Drive
The conventional dual slope converter measurement cycle has two distinct phases: 1. 2. Input signal integration Reference voltage integration (de-integration)
REF Voltage
Phase Control Polarity Control
The input signal being converted is integrated for a fixed time period, with time being measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual slope converter, a complete conversion requires the integrator output to "ramp-up" and "ramp-down." A simple mathematical equation relates the input signal, reference voltage and integration time:
Display
Integrator Output
Fixed Signal Integrate Time
3.2
TC835 Operational Theory
EQUATION 3-1:
TINT VREF T DEINT 1 VIN(T)DT = R C RINTC INT 0 INT INT where: VREF TINT = Reference voltage = Signal integration time (fixed)
The TC835 incorporates a system zero phase and integrator output voltage zero phase to the normal two phase dual slope measurement cycle. Reduced system errors, fewer calibration steps and a shorter overrange recovery time result. The TC835 measurement cycle contains four phases: 1. 2. 3. 4. System zero Analog input signal integration Reference voltage integration Integrator output zero
TDEINT = Reference voltage integration time (variable). For a constant VIN:
Internal analog gate status for each phase is shown in Table 3-1.
3.2.1
SYSTEM ZERO
EQUATION 3-2:
VIN = VREF TDEINT tINT
During this phase, errors due to buffer, integrator and comparator offset voltages are compensated for by charging CAZ (auto zero capacitor) with a compensating error voltage. With a zero input voltage the integrator output will remain at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to ANALOG COMMON. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages (see Figure 3-2).
The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high noise environments (see Figure 3-1).
2002 Microchip Technology Inc.
+
The TC835 is a dual slope, integrating analog to digital converter. An understanding of the dual slope conversion technique will aid in following the detailed TC835 operational theory.
DS21478B-page 7
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TC835
FIGURE 3-2:
SWI +IN SWRI- SWRI+
SYSTEM ZERO PHASE
Analog Input Buffer
+ CSZ SWIZ SWZ RINT CINT
FIGURE 3-4:
REFERENCE VOLTAGE INTEGRATION CYCLE
Analog Input Buffer
+ RINT CINT
SWI +IN SWRI- SWRI+
CSZ
SWRI+ SWRI-
Analog Common
SWI - IN SW1
SWZ SWRI+ SWRI-
SWZ
Integrator
Analog Common
Switch Open Switch Closed
- IN
SWI
SW1
Switch Open Switch Closed
3.2.2
ANALOG INPUT SIGNAL INTEGRATION
3.2.4
INTEGRATOR OUTPUT ZERO
The TC835 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within the device Common mode range (-1V from either supply rail, typically). The input signal polarity is determined at the end of this phase (see Figure 3-3).
This phase guarantees the integrator output is at 0V when the system zero phase is entered and that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5).
FIGURE 3-3:
INPUT SIGNAL INTEGRATION PHASE
Analog Input Buffer
+ RINT CINT
FIGURE 3-5:
INTEGRATOR OUTPUT ZERO PHASE
Analog Input Buffer
+ RINT CINT CSZ SWIZ SWZ
SWI +IN SWRI- SWRI+
CSZ SWIZ SWZ
SWI + IN SWRI- SWRI+
Analog Common
SWI - IN
SWRI+ SWRI-
SWZ SWRI+ SWRI-
SWZ
Integrator
SW1
Switch Open Switch Closed
Analog Common
SWI - IN SW1
Switch Open Switch Closed
3.2.3
REFERENCE VOLTAGE INTEGRATION
The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is: [Differential Input] VREF
Reading = 10,000
TABLE 3-1:
INTERNAL ANALOG GATE STATUS
SWI Closed Closed* Closed Closed Closed SWRI+ SWRISWZ Closed SWR Closed SW1 Closed SWIZ Reference Figures Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5
Conversion Cycle Phase System Zero Input Signal Integration Reference Voltage Integration Integrator Output Zero *Note:
Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
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-
+
SWZ
SWZ
Integrator
REF IN
+
To Digital Section
-
-
+
REF IN
+
SWR
-
CREF
Comparator
SWR CREF
-
SWZ
SWZ
+
Integrator
To Digital Section
+
REF IN
-
-
+
REF IN
+
-
SWR
CREF
Comparator
SWR CREF
SWIZ
SWZ
Comparator To Digital Section
Comparator To Digital Section
TC835
4.0 ANALOG SECTION FUNCTIONAL DESCRIPTION
Differential Inputs (+INPUT (Pin 10) and -INPUT (Pin 9)) 4.3 Reference Voltage Input (REF IN (Pin 2))
(In Reference to the 28-Pin Plastic Package)
4.1
The REF IN input must be a positive voltage with respect to ANALOG COMMON. A reference voltage circuit is shown in Figure 4-1.
FIGURE 4-1:
USING AN EXTERNAL REFERENCE
V+
The TC835 operates with differential voltages within the input amplifier Common mode range. The input amplifier Common mode range extends from 0.5V below the positive supply to 1V above the negative supply. Within this Common mode voltage range, an 86dB Common mode rejection ratio is typical. The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. An example of a worst case condition would be when a large positive Common mode voltage with a near full scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full scale swing, with the effect of reduced accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity.
V+
TC835
REF IN ANALOG COMMON
10k
MCP1525 2.5 VREF 1F
10k
Analog Ground
4.2
Analog Common Input (Pin 3)
ANALOG COMMON is used as the -INPUT return during auto zero and de-integrate. If -INPUT is different from ANALOG COMMON, a Common mode voltage exists in the system. This signal is rejected by the excellent CMRR of the converter. In most applications, -INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the common-mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON.
2002 Microchip Technology Inc.
DS21478B-page 9
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TC835
5.0 DIGITAL SECTION FUNCTIONAL DESCRIPTION
The major digital subsystems within the TC835 are illustrated in Figure 5-1, with timing relationships shown in Figure 5-2. The multiplexed BCD output data can be displayed on LCD or LED. The digital section is best described through a discussion of the control signals and data outputs.
FIGURE 5-1:
DIGITAL SECTION FUNCTIONAL DIAGRAM
Polarity D5 MSB D4 Digit D3 Drive Multiplexer From Analog Section Polarity FF Zero Cross Detect Latch Latch Latch Latch D2 Signal D1 LSB 13 B1 14 B2 Data Output 15 B4 16 B8
Latch
Counters
Control Logic 24 DGND 22 Clock In 25 RUN/ HOLD 27 28 26 STROBE 21 Busy
Overrange Underrange
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DS21478B-page 10
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TC835
FIGURE 5-2: TIMING DIAGRAMS FOR OUTPUTS
5.2
STROBE Output (Pin 26)
Integrator Output
Signal System Integrate Reference 10,000 Zero Integrate 10,001 Counts 20,001 Counts (Fixed) Counts (Max) Full Measurement Cycle 40,002 Counts
During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D1, D2, D3, D5) (see Figure 5-3). D5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one-half clock pulse. After the D5 digit strobe, D4 goes high for 200 clock pulses. The STROBE goes low 100 clock pulses after D4 goes high. This continues through the D1 digit drive pulse. The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. The active low STROBE pulses aid BCD data transfer to UARTs, processors and external latches.
Busy Overrange when Applicable Underrange when Applicable Expanded Scale Below Digit Scan
D5 D4 D3 D2 D1 * First D5 of System Zero and Reference Integrate One Count Longer Signal Integrate * D4 D3 Reference Integrate
100 Counts STROBE Auto Zero Digit Scan for Overrange * D5
FIGURE 5-3:
STROBE SIGNAL LOW FIVE TIMES PER CONVERSION
TC835 Outputs Busy
*
End of Conversion
D2 D1
B1-B8
D5 (MSD) Data
D4 Data
D3 Data
D2 Data
D1 (LSD) Data
D5 Data
STROBE 200 Counts
Note Absence of STROBE 200 Counts
5.1
RUN/HOLD Input (Pin 25)
D5 201 Counts 200 Counts 200 Counts 200 Counts 200 Counts D4
When left open, this pin assumes a logic "1" level. With a RUN/HOLD = 1, the TC835 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When RUN/HOLD changes to a logic "0," the measurement cycle in progress will be completed, and data held and displayed as long as the logic "0" condition exists. A positive pulse (>300nsec) at RUN/HOLD initiates a new measurement cycle. The measurement cycle in progress when RUN/HOLD initially assumed the logic "0" state must be completed before the positive pulse can be recognized as a single conversion run command. The new measurement cycle begins with a 10,001count auto zero phase. At the end of this phase, the busy signal goes high.
D3
D2
D1
*Delay between Busy going Low and First STROBE pulse is dependent on Analog Input.
5.3
BUSY Output
At the beginning of the signal integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic "0" state after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto zero cycle.
2002 Microchip Technology Inc.
DS21478B-page 11
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TC835
5.4 OVERRANGE Output
6.0
6.1
TYPICAL APPLICATIONS
Component Value Selection
If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic "1." The overrange output register is set when BUSY goes low, and is reset at the beginning of the next reference integration phase.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800 counts), the underrange register bit is set at the end of BUSY. The bit is set low at the next signal integration phase.
The integrating resistor is determined by the full-scale input voltage and the output current of the buffer used to charge the integrator capacitor. Both the buffer amplifier and the integrator have a class A output stage, with 100A of quiescent current. A 20A drive current gives negligible linearity errors. Values of 5A to 40A give good results. The exact value of an integrating resistor for a 20A current is easily calculated.
EQUATION 6-1:
RINT = Full scale voltage 20A
5.6
POLARITY Output
A positive input is registered by a logic "1" polarity signal. The POLARITY bit is valid at the beginning of Reference Integrate and remains valid until determined during the next conversion. The POLARITY bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications.
6.1.1
INTEGRATING CAPACITOR
5.7
Digit Drive Outputs
Digit drive signals are positive going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, except D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication.
The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the integrator swing (approximately 0.3V from either supply). For 5V supplies and ANALOG COMMON tied to supply ground, a 3.5V to 4V full-scale integrator swing is adequate. A 0.10F to 0.47F is recommended. In general, the value of CINT is given by:
EQUATION 6-2:
CINT = [10,000 x clock period] x IINT Integrator output voltage swing (10,000) (clock period) (20A) Integrator output voltage swing A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption would be to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications.
=
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B8, B4, B2, B1 are positive-true logic signals. The data bits become active simultaneously with the digit drive signals. In an overrange condition, all data bits are at a logic "0" state.
6.1.2
AUTO ZERO AND REFERENCE CAPACITORS
The size of the auto zero capacitor has some influence on the noise of the system. A large capacitor reduces the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. The dielectric absorption of the reference capacitor and auto zero capacitor are only important at power-on or when the circuit is recovering from an overload.
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TC835
Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. The conversion rate is easily calculated:
EQUATION 6-3:
Reading 1/sec = Clock Frequency (Hz) 4000
6.1.3
REFERENCE VOLTAGE
The analog input required to generate a full scale output is VIN = 2VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made.
6.3
6.3.1
Power Supplies and Grounds
POWER SUPPLIES
The TC835 is designed to work from 5V supplies. For single +5V operation, a TC7660 can provide a -5V supply.
6.2
6.2.1
Conversion Timing
LINE FREQUENCY REJECTION
6.3.2
GROUNDING
A signal integration period at a multiple of the 60Hz line frequency will maximize 60Hz "line noise" rejection. A 200kHz clock frequency will reject 60Hz and 400Hz noise. This corresponds to five readings per second (see Table 6-1 and Table 6-2).
Systems should use separate digital and analog ground systems to avoid loss of accuracy.
6.4
High-Speed Operation
TABLE 6-1:
CONVERSION RATE VS. CLOCK FREQUENCY
Conversion Rate (Conv./Sec.) 2.5 3 5 7.5 10 20 30
Oscillator Frequency (kHz) 100 120 200 300 400 800 1200
The maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3sec delay, and at a clock frequency of 200kHz (5sec period), half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50V input, 1 to 2 with 150V, 2 to 3 at 250V, etc. This transition at midpoint is considered desirable by most users, however, if the clock frequency is increased appreciably above 200kHz, the instrument will flash "1" on noise peaks even when the input is shorted. For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1MHz may be used. For a fixed clock frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted out digitally.
TABLE 6-2:
LINE FREQUENCY VS. CLOCK FREQUENCY
Line Frequency Rejection 60Hz * -- * -- -- * -- -- -- * 50Hz * -- -- -- * * * -- -- -- 400Hz * * * * * * * * * *
Oscillator Frequency (kHz) 50.000 53.333 66.667 80.000 83.333 100.000 125.000 133.333 166.667 200.000 250.000
The clock frequency may be extended above 200kHz without this error, however, by using a low-value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage onto the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error.
2002 Microchip Technology Inc.
DS21478B-page 13
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TC835
The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in Section 6.0, Typical Applications. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. course, the flip flop delays the true zero crossing by up to one count in every instance. If a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. This one-count delay compensates for the delay of the zero crossing flip flop and allows the correct number to be latched into the display. Similarly, a one-count delay at the beginning of auto zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate, so that true ratiometric readings result.
6.5
Zero Crossing Flip-Flop
The flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half-clock pulse have died down. False zero crossings caused by clock pulses are not recognized. Of
FIGURE 6-1:
4-1/2 DIGIT ADC MULTIPLEXED COMMON ANODE LED DISPLAY
+5V
20 19 18 17 12 D1 D2 D3 D4 D5 4 INT OUT 0.33F 1F 5 AZ IN POL 23 4.7k b 1F c 7 7 X7 5 RBI DM7447A 16 +5V 9-15 7 7
100k 200kHz 100k + Analog Input -
6 BUFF OUT 22 F IN 10
TC835
CREF- 7 CREF+ 8 16 B8 15 B4 14 B2 B1 13 V+ 11 V+ MCP1525
Blank MSD On Zero 6 D 2 C 1 B 7 A
+INPUT -INPUT
1F
9
3 ANALOG COMMON REF V - IN 12 -5V 100k
1F
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DS21478B-page 14
2002 Microchip Technology Inc.
TC835
FIGURE 6-2:
R2 C FO
16k 56k 1k
RC OSCILLATOR CIRCUIT
R1
FIGURE 6-3:
COMPARATOR CLOCK CIRCUITS
+5V
Gates are 74C04
0.22F
1. fO =
2C(0.41R P + 0.7R1)
, RP =
R1 R2 R 1 + R2
16k
a. If R 1 = R2 = R1, F 0.55/RC b. If R2 >> R1, f 0.45/R1C c. If R 2 << R1, f 0.72/R1C 2. Examples: a. f = 120kHz, C = 420pF R 1 = R 2 10.9k b. f = 120kHz, C = 420pF, R2 = 50k R1 = 8.93k c. f = 120kHz, C = 220pF, R2 = 5k R1 = 27.3k
R2 100k +5V R4 2k
R2 100k C1 0.1F
FIGURE 6-4:
+5V
4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON CATHODE LED DISPLAY
+5V SET VREF = 1V -5V 1 V-
MCP1525 1F
100 k
2
27 OR REF IN 26 3 ANALOG STROBE GND 25
TC835
UR
28 150 47 k 10 150 11 12 9 8 7
Analog GND 0.33F
100 k + SIG IN -
4 INT RUN/HOLD OUT 24 5 DGND AZ IN 23 6 BUFF POLARITY OUT 100 k 7 22 CREF+ CLK IN 1F 21 8C REFBUSY 20 9 -INPUT (LSD) D1 0.1 10 19 +INPUT D2 F 11 18 D3 +5V V+ 12 17 D4 D5 (MSD) 1F 13 16 B1 (LSB) (MSB) B8 14 B4 15 B2
FOSC = 200kHz
2002 Microchip Technology Inc.
-
3
+
2
LM311 4 1
13 MC14513 6 14 15 16 17 18 5 4 3 2 1 +5V
-
1
3
+ 4 6
2
8 7 1
VOUT
LM311
30k 390pF
C2 10pF 7 R3 50k VOUT
DS21478B-page 15
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TC835
FIGURE 6-5:
SET VREF = 1V VREF IN -5V 1 2 V-
TEST CIRCUIT
TC835
28 UNDERRANGE REF IN 27 OVERRANGE 3 ANALOG 26 STROBE COMMON ANALOG GND 4 25 RUN/HOLD INT OUT 0.47 1F 24 5 F DIGTAL GND AZ IN 23 6 BUFF OUT POLARITY 22 100 k 7 CLOCK IN CREF100 Signal 21 1F 8 k BUSY Input CREF+ 9 20 -INPUT (LSD) D1 19 0.1F 10 D2 +INPUT 18 11 D3 +5V V+ 12 17 D5 (MSD) D4 13 16 (MSB) B8 B1 (LSB) 14 15 B4 B2 100k
Clock Input 120kHz
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DS21478B-page 16
2002 Microchip Technology Inc.
TC835
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time.
7.2
Taping Forms
Component Taping Orientation for 64-Pin PQFP Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
64-Pin PQFP
32 mm
24 mm
250
13 in
NOTE: Drawing does not represent total number of pins.
Component Taping Orientation for 44-Pin PQFP Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PQFP
24 mm
16 mm
500
13 in
NOTE: Drawing does not represent total number of pins.
2002 Microchip Technology Inc.
DS21478B-page 17
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TC835
7.3 Package Dimensions
28-Pin PDIP (Wide)
PIN 1
.555 (14.10) .530 (13.46)
1.465 (37.21) 1.435 (36.45)
.610 (15.49) .590 (14.99)
.200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92)
.040 (1.02) .020 (0.51)
.015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50)
3MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
.022 (0.56) .015 (0.38) Dimensions: inches (mm)
44-Pin PQFP
.009 (0.23) .005 (0.13)
7 MAX.
PIN 1 .018 (0.45) .012 (0.30)
.041 (1.03) .026 (0.65)
.398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65)
.031 (0.80) TYP.
.398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65)
.010 (0.25) TYP. .083 (2.10) .075 (1.90) .096 (2.45) MAX.
Dimensions: inches (mm)
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DS21478B-page 18
2002 Microchip Technology Inc.
TC835
7.3 Package Dimensions (Continued)
64-Pin PQFP
PIN 1 .018 (0.45) .012 (0.30) .009 (0.23) .005 (0.13)
7 MAX.
.041 (1.03) .031 (0.78)
.555 (14.10) .547 (13.90) .687 (17.45) .667 (16.95)
.031 (0.80) TYP.
.555 (14.10) .547 (13.90) .687 (17.45) .667 (16.95)
.010 (0.25) TYP. .120 (3.05) .100 (2.55) .130 (3.30) MAX.
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21478B-page 19
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TC835
NOTES:
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DS21478B-page 20
2002 Microchip Technology Inc.
TC835
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21478B-page 21
TC835
NOTES:
DS21478B-page 22
2002 Microchip Technology Inc.
TC835
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21478B-page 23
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WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
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China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
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Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
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EUROPE
Denmark
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India
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United Kingdom
Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
04/20/02
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DS21478B-page 24
2002 Microchip Technology Inc.
*B87412SD*

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