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Wireless Components
ASK/FSK Transmitter 915 MHz TDA 5102 Version 1.1
Specification October 2001
Revision History Current Version: 1.1 as of October 2001 Previous Version: 1.0, March 2001 Page (in previous Version) 2-2, 5-3, 5-6 3-3 ... 3-6 3-10, 5-3 4-8 ... 4-10 5-2 5-2 5-3, 5-6 5-4, 5-7 5-5, 5-8 5-2 5-2 5-3, 5-6 5-4, 5-7 5-5, 5-8 Page (in current Version) 2-2, 5-3, 5-6 3-3 ... 3-6 3-10, 5-3 Subjects (major changes since last revision)
Frequency range increased ESD-structures added to interface schematics Typical value for Power-Down-Mode current added Description of Application board deleted Supply voltage range added to Absolute Maximum Ratings ESD integrity specified in detail Loop filter voltages adapted Saturation voltage of Clock Driver Output reduced Output Power Tolerances reduced
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Edition 15.02.2001 Published by Infineon Technologies AG, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG 2001. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
1
2.1 2.2 2.3 2.4
Table of Contents
1-i
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 2-2 2-2 2-2 2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 3-2 3-3 3-7 3-8
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 4-2 4-3 4-4 4-5
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 5.2 5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1 5-2 5-2 5-3
TDA 5102
Product Info
Product Info
General Description The TDA 5102 is a single chip ASK/ Package FSK transmitter for the frequency band 905-925 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additionally features like a power down mode, a low power detect, a selectable crystal oscillator frequency and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation.
I I I I I I I
Features
fully integrated frequency synthesizer VCO without external components high efficiency power amplifier frequency range 905-925 MHz ASK/FSK modulation low supply current (typically 7mA) voltage supply range 2.1 - 4 V Keyless entry systems Remote control systems
I I I I I
power down mode low voltage sensor selectable crystal oscillator 7.15 MHz/14.3 MHz programmable divided clock output for C low external component count
Applications
I I
I I
Alarm systems Communication systems
Ordering Information
Type TDA 5102 available on tape and reel Ordering Code Package P-TSSOP-16
Q67036-A1175
Wireless Components
Product Info
Specification, October 2001
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5102
Product Description
2.1 Overview
The TDA 5102 is a single chip ASK/FSK transmitter for the frequency band 905925 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features like a power down mode, a low power detect, a selectable crystal oscillator frequency and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation.
2.2 Applications
I I I I
Keyless entry systems Remote control systems Alarm systems Communication systems
2.3 Features
I I I I I I I I I I I I
fully integrated frequency synthesizer VCO without external components high efficiency power amplifier frequency range 905-925 MHz ASK/FSK modulation low supply current (typically 7 mA) voltage supply range 2.1 - 4 V power down mode low voltage sensor selectable crystal oscillator 7.15 MHz/14.3 MHz programmable divided clock output for C low external component count
Wireless Components
2-2
Specification, October 2001
TDA 5102
Product Description
2.4 Package Outlines
Figure 2-1
P-TSSOP-16
Wireless Components
2-3
Specification, October 2001
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.5.1 3.4.5.2 3.4.5.3 3.4.5.4 3.4.6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Power mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Recommended timing diagrams for ASK- and FSK-Modulation . . 3-12
TDA 5102
Functional Description
3.1 Pin Configuration
PDWN
1
16
CSEL
LPD
2
15
FSEL
VS
3
14
PAOUT
LF
4
13
PAGND
TDA 5102
GND 5 12 FSKGND
ASKDTA
6
11
FSKOUT
FSKDTA
7
10
COSC
CLKOUT
8
9
CLKDIV
Pin_config.wmf
Figure 3-1 Table 3-1
IC Pin Configuration
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol PDWN LPD VS LF GND ASKDTA FSKDTA CLKOUT CLKDIV COSC FSKOUT FSKGND PAGND PAOUT FSEL CSEL
Function Power Down Mode Control Low Power Detect Output Voltage Supply Loop Filter Ground Amplitude Shift Keying Data Input Frequency Shift Keying Data Input Clock Driver Output Clock Divider Control Crystal Oscillator Input Frequency Shift Keying Switch Output Frequency Shift Keying Ground Power Amplifier Ground Power Amplifier Output Frequency Range Selection: Has to be left open for 915 MHz operation Crystal Frequency Selection (7.15 or 14.3 MHz)
Wireless Components
3-2
Specification, October 2001
TDA 5102
Functional Description
3.2 Pin Definitions and Functions
Table 3-2
Pin No. 1
Symbol PDWN
Interface Schematic
Function Disable pin for the complete transmitter circuit.
VS 40 A (ASKDTA+FSKDTA)
A logic low (PDWN < 0.7 V) turns off all transmitter functions. A logic high (PDWN > 1.5 V) gives access to all transmitter functions.
5 k 1 "ON" 150 k
PDWN input will be pulled up by 40 A internally by either setting FSKDTA or ASKDTA to a logic high-state.
250 k
2
LPD
VS 40 A 2 300
This pin provides an output indicating the low-voltage state of the supply voltage VS. VS < 2.15 V will set LPD to the low-state. An internal pull-up current of 40 A gives the output a high-state at supply voltages above 2.15 V.
3
VS
This pin is the positive supply of the transmitter electronics. An RF bypass capacitor should be connected directly to this pin and returned to GND (pin 5) as short as possible.
Wireless Components
3-3
Specification, October 2001
TDA 5102
Functional Description
4
LF
VS
140 pF 15 pF 35 k 10 k 4 VS
Output of the charge pump and input of the VCO control voltage. The loop bandwidth of the PLL is 150 kHz when only the internal loop filter is used. The loop bandwidth may be reduced by applying an external RC network referencing to the positive supply VS (pin 3).
5 6
GND ASKDTA
VS +1.2 V
General ground connection. Digital amplitude modulation can be imparted to the Power Amplifier through this pin. A logic high (ASKDTA > 1.5 V or open) enables the Power Amplifier.
+1.1 V 90 k 50 pF 30 A
60 k 6
A logic low (ASKDTA < 0.5 V) disables the Power Amplifier.
7
FSKDTA
VS +1.2 V
Digital frequency modulation can be imparted to the Xtal Oscillator by this pin. The VCO-frequency varies in accordance to the frequency of the reference oscillator. A logic high (FSKDTA > 1.5V or open) sets the FSK switch to a high impedance state. A logic low (FSKDTA < 0.5 V) closes the FSK switch from FSKOUT (pin 11) to FSKGND (pin 12). A capacitor can be switched to the reference crystal network this way. The Xtal Oscillator frequency will be shifted giving the designed FSK frequency deviation.
60 k 7 +1.1 V 90 k 30 A
Wireless Components
3-4
Specification, October 2001
TDA 5102
Functional Description
8
CLKOUT
VS 8 300
Clock output to supply an external device. An external pull-up resistor has to be added in accordance to the driving requirements of the external device. A clock frequency of 3.57 MHz is selected by a logic low at CLKDIV input (pin9). A clock frequency of 894 kHz is selected by a logic high at CLKDIV input (pin9).
9
CLKDIV
9
This pin is used to select the desired clock division rate for the CLKOUT signal. VS +1.2 V VS A logic low (CLKDIV < 0.2 V) applied to this pin selects the 3.57 MHz output signal at 5 A CLKOUT (pin 8). 60 k A logic high (CLKDIV open) applied to this +0.8 V pin selects the 894 kHz output signal at 60 k CLKOUT (pin 8).
10
COSC
VS VS
6 k 10
This pin is connected to the reference oscillator circuit. The reference oscillator is working as a negative impedance converter. It presents a negative resistance in series to an inductance at the COSC pin.
100 A
11
FSKOUT
VS VS
This pin is connected to a switch to FSKGND (pin 12). The switch is closed when the signal at FSKDTA (pin 7) is in a logic low state.
200 A 1.5 k 11
The switch is open when the signal at FSKDTA (pin 7) is in a logic high state. FSKOUT can switch an additional capacitor to the reference crystal network to pull the crystal frequency by an amount resulting in the desired FSK frequency shift of the transmitter output frequency.
12
Wireless Components
3-5
Specification, October 2001
TDA 5102
Functional Description
12 13
FSKGND PAGND
Ground connection for FSK modulation output FSKOUT. Ground connection of the power amplifier. The RF ground return path of the power amplifier output PAOUT (pin 14) has to be concentrated to this pin.
14
PAOUT
14
RF output pin of the transmitter. A DC path to the positive supply VS has to be supplied by the antenna matching network.
13
15
FSEL
VS +1.2 V
This pin has to be left open to select the 915 MHz transmitter frequency range. A logic low (FSEL < 0.5 V) applied to this pin sets the transmitter to the 457 MHz frequency range.
+1.1 V
30 k 15 90 k 30 A
A logic high (FSEL open) applied to this pin sets the transmitter to the 915 MHz frequency range.
16
CSEL
VS +1.2 V VS 5 A
This pin is used to select the desired reference frequency. A logic low (CSEL < 0.2 V) applied to this pin sets the internal frequency divider to accept a reference frequency of 7.15 MHz. A logic high (CSEL open) applied to this pin sets the internal frequency divider to accept a reference frequency of 14.3 MHz.
60 k 16
+0.8 V 60 k
Wireless Components
3-6
Specification, October 2001
Wireless Components
FSK Data Input ASK Data Input Low Power Detect Output Power Down Control Positive Supply VS
Figure 3-2
7 6 1 3 2
FSK Ground
12 OR
On
FSK Switch
11
Power Supply
Low Voltage Sensor 2.2V
3.3 Functional Block diagram
Functional Block diagram
3-7
Crystal 7.15/14.3 MHz
10
XTAL Osc PFD :128/64 VCO :1/2
Power AMP
14
Power Amplifier Output
13 :2/8 :4/16 LF
Power Amplifier Ground
Clock Output Frequency Select 0.894/3.57 MHz
9 8
Clock Output Crystal Select 7.15/14.3 MHz
16
4
Loop Filter
15
Frequency Select Open for 915 MHz
5
Ground
Functional Description
Funct_Block_Diagram.wmf
TDA 5102
Specification, October 2001
TDA 5102
Functional Description
3.4 Functional Blocks
3.4.1 PLL Synthesizer The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO), an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the VCO is 915 MHz. The oscillator signal is fed both, to the synthesizer divider chain and to the power amplifier. The overall division ratio of the asynchronous divider chain is 128 in case of a 7.15 MHz crystal or 64 in case of a 14.3 MHz crystal and can be selected via CSEL (pin 16). The phase detector is a Type IV PD with charge pump. The passive loop filter is realized on chip.
3.4.2 Crystal Oscillator The crystal oscillator operates either at 7.15 MHz or at 14.3 MHz. The reference frequency can be chosen by the signal at CSEL (pin 16).
Table 3-3
CSEL (pin 16) Low1) Open2) 1) Low: 2) Open: Voltage at pin < 0.2 V Pin open
Crystal Frequency 7.15 MHz 14.3 MHz
For both quartz frequency options, 894 kHz or 3.57 MHz are available as output frequencies of the clock output CLKOUT (pin 8) to drive the clock input of a micro controller. The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)
Table 3-4
CLKDIV (pin 9) Low1) Open2) 1) Low: 2) Open: Voltage at pin < 0.2 V Pin open
CLKOUT Frequency 3.57 MHz 894 kHz
Wireless Components
3-8
Specification, October 2001
TDA 5102
Functional Description
To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount by switching an external capacitor via FSKOUT (pin 11). The condition of the switch is controlled by the signal at FSKDTA (pin 7).
Table 3-5
FSKDTA (pin7) Low Open2), High3) 1) Low: 2) Open: 3) High: Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V
1)
FSK Switch CLOSED OPEN
3.4.3 Power Amplifier
For operation at 915 MHz, the power amplifier is fed directly from the voltage controlled oscillator. It is possible to feed the power amplifier with the VCO frequency divided by 2. This is controlled by FSEL (pin 15) as described in the table below.
Table 3-6
FSEL (pin 15) Low1) Open2) 1) Low: 2) Open: Voltage at pin < 0.5 V Pin open
Radiated Frequency Band 457 MHz 915 MHz
The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6).
Table 3-7
ASKDTA (pin 6) Low Open2), High3) 1) Low: 2) Open: 3) High: Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V
1)
Power Amplifier OFF ON
The Power Amplifier has an Open Collector output at PAOUT (pin 14) and requires an external pull-up coil to provide bias. The coil is part of the tuning and matching LC circuitry to get best performance with the external loop antenna. To achieve the best power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 14) should be twice the supply voltage. The power amplifier has its own ground pin PAGND (pin 13) in order to reduce the amount of coupling to the other circuits.
Wireless Components
3-9
Specification, October 2001
TDA 5102
Functional Description
3.4.4 Low Power Detect
The supply voltage is sensed by a low power detector. When the supply voltage drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To minimize the external component count, an internal pull-up current of 40 A gives the output a high-state at supply voltages above 2.15 V. The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off the PA as soon as the supply voltage drops below 2.15 V or it can be used to inform a micro-controller to stop the transmission after the current data packet.
3.4.5 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE MODE and the TRANSMIT MODE.
3.4.5.1 Power Down Mode In the POWER DOWN MODE the complete chip is switched off. The current consumption is typically 0.3 nA at 3 V 25C.
3.4.5.2 PLL Enable Mode In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off to avoid undesired power radiation during the time the PLL needs to settle. The turn on time of the PLL is determined mainly by the turn on time of the crystal oscillator and is typically less than 1 msec, depending on the crystal. The current consumption is typically 3.5 mA. 3.4.5.3 Transmit Mode In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too. The current consumption of the IC is typically 7 mA when using a proper transforming network at PAOUT, see Figure 4-1.
3.4.5.4 Power mode control The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1). When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up internally. Forcing the voltage at the pins low overrides the internally set state. Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open.
Wireless Components
3 - 10
Specification, October 2001
TDA 5102
Functional Description
The principle schematic of the power mode control circuitry is shown in Figure 3-5.
PDWN ASKDTA FSKDTA
On
OR
Bias Source 120 k Bias Voltage
120 k
On
FSK 915 MHz PA IC
FSKOUT
PLL
PAOUT
Power_Mode.wmf
Figure 3-5
Power mode control circuitry
Table 3-8 provides a listing of how to get into the different power modes
Table 3-8
PDWN Low1) Open2) High3) Open High Open Open 1) Low: 2) Open: 3) High:
FSKDTA Low, Open Low Low, Open, High High Low, Open, High High Low, Open, High
ASKDTA Low, Open Low Low
MODE POWER DOWN
PLL ENABLE Low Open, High Open, High High TRANSMIT
Voltage at pin < 0.7 V (PDWN) Voltage at pin < 0.5 V (FSKDTA, ASKDTA) Pin open Voltage at pin > 1.5 V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not recommended.
Wireless Components
3 - 11
Specification, October 2001
TDA 5102
Functional Description
3.4.6 Recommended timing diagrams for ASK- and FSK-Modulation ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
High
FSKDTA
Low
to t
DATA Open, High
ASKDTA
Low
to t
min. 1 msec.
ASK_mod.wmf
Figure 3-6
ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
DATA High
FSKDTA
Low
to t
High
ASKDTA
Low
to t
min. 1 msec.
FSK_mod.wmf
Figure 3-7
FSK Modulation
Wireless Components
3 - 12
Specification, October 2001
TDA 5102
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to t
DATA Open, High
ASKDTA
Low
to t
min. 1 msec.
Alt_ASK_mod.wmf
Figure 3-8
Alternative ASK Modulation
Alternative FSK Modulation
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to t
Open, High
ASKDTA
Low
to t
DATA Open, High
FSKDTA
Low
to t
min. 1 msec.
Alt_FSK_mod.wmf
Figure 3-9
Alternative FSK Modulation
Wireless Components
3 - 13
Specification, October 2001
4
Applications
Contents of this Chapter 4.1 4.2 4.3 4.4 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 4-2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 4-4 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
TDA 5102
Applications
4.1 50 Ohm-Output Testboard Schematic
X2SMA C8 C2
C4 L1 VCC
L2
C7 C3 C6 Q1
16
15
14
13
12
11
7.15 (14.3) MHz
TDA5102
1 2 3 4 5 6 7 8 FSK
VCC
T1
VCC
C1
R3A R3F R4 R2 ASK
10
0.89 (3.6) MHz
9
R1 X1SMA
C5
50ohm_test_v5.wmf
Figure 4-1
50 -Output testboard schematic
Wireless Components
4-2
Specification, October 2001
TDA 5102
Applications
4.2 50 Ohm-Output Testboard Layout
Figure 4-2
Top Side of TDA 5102-Testboard with 50 -Output. It is the same testboard as for the TDA 5100.
Figure 4-3
Bottom Side of TDA 5102-Testboard with 50 -Output. It is the same testboard as for the TDA 5100.
Wireless Components
4-3
Specification, October 2001
TDA 5102
Applications
4.3 Bill of material (50 Ohm-Output Testboard)
Table 4-1 Bill of material Part ASK 915 MHz R1 R2 R3A R3F R4 C1 C2 C3 C4 C5 C6 C7 C8 L1 L2 Q3 IC1 B1 T1 X1 X2 open 47 nF 47 pF 2.7 pF 100 pF 1 nF 5.6 pF 0 Jumper 8.2 pF 33 nH 15 nH 14.3 MHz TDA 5102 Battery clip Push-button SMA-S SMA-S 15 k 15 k open 47 nF 47 pF 2.7 pF 100 pF 1 nF 5.6 pF 47 pF 8.2 pF 33 nH 15 nH 14.3 MHz TDA 5102 Battery clip Push-button SMA-S SMA-S HU2031-1, RENATA replaced by a short SMA standing SMA standing 4.7 k FSK 915 MHz 4.7 k 12 k 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, X7R, 10% 0805, COG, 5% 0805, COG, 0.1 pF 0805, COG, 5% 0805, X7R, 10% 0805, COG, 0.1 pF 0805, COG, 5% 0805, 0 Jumper 0805, COG, 5% TOKO LL2012-J TOKO LL1608-J Specification
Wireless Components
4-4
Specification, October 2001
TDA 5102
Applications
4.4 Hints
1. Application Hints on the crystal oscillator
As mentioned before, the crystal oscillator achieves a turn on time less than 1 msec. To achieve this, a NIC oscillator type is implemented in the TDA 5102. The input impedance of this oscillator is a negative resistance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv.
-R
L
f, CL Cv
IC
Cv =
1 1 +2L CL
Formula 1)
CL: : L:
crystal load capacitance for nominal frequency angular frequency inductivity of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced by a short to ground. Assume a crystal frequency of 14.3 MHz and a crystal load capacitance of CL = 20 pF. The inductance L is specified within the electrical characteristics at 14.3 MHz to a value of 11 H. Therefore C6 is calculated to 7.2 pF.
Cv =
1 1 + 2L CL
= C6
Wireless Components
4-5
Specification, October 2001
TDA 5102
Applications
Example for the FSK-Mode: FSK modulation is achieved by switching the load capacitance of the crystal as shown below.
FSKDTA
FSKOUT
Csw -R L
COSC
f, CL Cv1
Cv2
IC
The frequency deviation of the crystal oscillator is multiplied with the divider factor N of the Phase Locked Loop to the output of the power amplifier. In case of small frequency deviations (up to +/- 1000 ppm), the two desired load capacitances can be calculated with the formula below.
CL # C 0 CL =
2(C 0 + CL ) f ) (1 + N * f1 C1 2(C 0 + CL ) f ) 1 (1 + N * f1 C1
C L: C 0: f: : N: df:
crystal load capacitance for nominal frequency shunt capacitance of the crystal frequency = 2f: angular frequency division ratio of the PLL peak frequency deviation
Because of the inductive part of the TDA 5102, these values must be corrected by formula 1). The value of Cv can be calculated.
Wireless Components
4-6
Specification, October 2001
TDA 5102
Applications
If the FSK switch is closed, Cv- is equal to Cv1 (C6 in the application diagram). If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
Cv 2 = C 7 =
Csw Cv1 - (Cv + ) (Cv1 + Csw) (Cv + ) - Cv1
Csw:
parallel capacitance of the FSK switch (3 pF)
Remark:
These calculations are only approximations. The necessary values depend on the layout also and must be adapted for the specific application board.
2. Design hints on the buffered clock output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be connected between this pin and the positive supply voltage. The value of RL is depending on the clock frequency and the load capacitance CLD (PCB board plus input capacitance of the microcontroller). RL can be calculated to:
RL =
1 fCLKOUT * 8 * CLD
Table 4-2 fCLKOUT= 894 kHz fCLKOUT= 3.57 MHz
CLD[pF] 5 10 20 Remark:
RL[kOhm] 27 12 6.8
CLD[pF] 5 10 20
RL[kOhm] 6.8 3.3 1.8
To achieve a low current consumption and a low spurious radiation, the largest possible RL should be chosen.
Wireless Components
4-7
Specification, October 2001
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.3.1 5.3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics at 3V, 25C . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics at 2.1 V ... 4.0 V, -25C ... +85C. . . . . . . . . . 5-6
TDA 5102
Reference
5.1 Absolute Maximum Ratings
The AC / DC characteristic limits are not guaranteed. The maximum ratings must not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Parameter Symbol Limit Values Min Junction Temperature Storage Temperature Thermal Resistance TJ Ts RthJA Max Unit Remarks
-40 -40
150 125 230
C C K/W
Supply voltage
ESD integrity, all pins ESD integrity, pins 11 and 14 not tested
VS
VESD VESD
-0.3 -1 -2
4.0
V
kV kV
+1 +2
100 pF, 1500 100 pF, 1500
Ambient Temperature under bias: TA=-25 to +85C
5.2 Operating Range
Within the operational range the IC operates as described in the circuit description.
Table 5-2 Parameter Symbol Limit Values Min Max Unit Test Conditions
Supply voltage Ambient temperature
VS TA
2.1 -25
4.0
V C
85
Wireless Components
5-2
Specification, October 2001
TDA 5102
Reference
5.3 AC/DC Characteristics
5.3.1
AC/DC Characteristics at 3V, 25C
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25C Parameter Symbol Min Current consumption Power down mode PLL enable mode Transmit mode IS PDWN IS PLL_EN IS TRANSM 0.3 3.3 7 100 4.2 9 nA mA mA Load tank see Figure 4-1 V (Pins 1, 6, and 7) < 0.2 V Limit Values Typ Max Unit Test Conditions
Power Down Mode Control (Pin 1) Power down mode PLL enable mode Transmit mode Input bias current PDWN VPDWN VPDWN VPDWN IPDWN 0 1.5 1.5 0.7 VS VS 30 V V V A VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = VS
Low Power Detect Output (Pin 2) Internal pull up current Input current low voltage Loop Filter (Pin 4) VCO tuning voltage Output frequency range 915 MHz-band VLF fOUT, 915 VS - 1.5 902 915 VS - 0.7 928 V MHz fVCO = 915 MHz VS-VLF = 0.54V...1.76V VFSEL = open I LPD1 I LPD2 30 1 A mA VS = 2.3 V ... VS VS = 1.9 V ... 2.1 V
ASK Modulation Data Input (Pin 6) ASK Transmit disabled ASK Transmit enabled Input bias current ASKDTA Input bias current ASKDTA ASK data rate VASKDTA VASKDTA IASKDTA IASKDTA fASKDTA -20 20 0 1.5 0.5 VS 30 V V A A kHz VASKDTA = VS VASKDTA = 0 V
Wireless Components
5-3
Specification, October 2001
TDA 5102
Reference
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25C Parameter Symbol Min FSK Modulation Data Input (Pin 7) FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate Clock Driver Output (Pin 8) Output current (Low) Output current (High) Saturation Voltage (Low) Clock Divider Control (Pin 9) Setting Clock Driver output frequency fCLKOUT=3.57 MHz Setting Clock Driver output frequency fCLKOUT=894 kHz Input bias current CLKDIV Input bias current CLKDIV VCLKDIV VCLKDIV ICLKDIV ICLKDIV -20 30 0 0.2 V V A A pin open VCLKDIV = VS VCLKDIV = 0 V ICLKOUT ICLKOUT VSATL 1 5 0.56 mA A V VCLKOUT = VS VCLKOUT = 0 V ICLKOUT = 1 mA VFSKDTA VFSKDTA IFSKDTA IFSKDTA fFSKDTA -20 20 0 1.5 0.5 VS 30 V V A A kHz VFSKDTA = VS VFSKDTA = 0 V Limit Values Typ Max Unit Test Conditions
Crystal Oscillator Input (Pin 10) Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin Serial Resistance of the crystal Input inductance of the COSC pin FSK Switch Output (Pin 11) On resistance On capacitance Off resistance Off capacitance RFSKOUT CFSKOUT RFSKOUT CFSKOUT 10 1.5 220 6 pF k pF VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS 11 12 100 CCOSCmax 5 100 pF H H f = 7.15 MHz f = 7.15 MHz f = 14.3 MHz f = 14.3 MHz
Wireless Components
5-4
Specification, October 2001
TDA 5102
Reference
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25C Parameter Symbol Min Power Amplifier Output (Pin 14) Output Power1) transformed to 50 Ohm POUT915 0 2 4 dBm fOUT = 915 MHz VFSEL = open Limit Values Typ Max Unit Test Conditions
Frequency Range Selection (Pin 15) Transmit frequency 915 MHz Transmit frequency 457 MHz Input bias current FSEL Input bias current FSEL VFSEL VFSEL IFSEL IFSEL -20 0 0.5 30 V V A A VFSEL = VS VFSEL = 0 V pin open
Crystal Frequency Selection (Pin 16) Crystal frequency 7.15 MHz Crystal frequency 14.3 MHz Input bias current CSEL Input bias current CSEL VCSEL VCSEL ICSEL ICSEL -25 50 0 0.2 V V A A pin open VCSEL = VS VCSEL = 0 V
1) Power amplifier in overcritical C-operation. Matching circuitry as used in the 50 Ohm-Output Testboard. Tolerances of the passive elements not taken into account.
Wireless Components
5-5
Specification, October 2001
TDA 5102
Reference
5.3.2
AC/DC Characteristics at 2.1 V ... 4.0 V, -25C ... +85C
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25C ... +85C Parameter Symbol Min Current consumption Power down mode PLL enable mode Transmit mode IS PDWN IS PLL_EN IS TRANSM 3.3 7 250 4.6 9.5 nA mA mA Load tank see Figure 4-1 and 4-2 V (Pins 1, 6, and 7) < 0.2 V Limit Values Typ Max Unit Test Conditions
Power Down Mode Control (Pin 1) Power down mode PLL enable mode Transmit mode Input bias current PDWN VPDWN VPDWN VPDWN IPDWN 0 1.5 1.5 0.5 VS VS 30 V V V A VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = VS
Low Power Detect Output (Pin 2) Internal pull up current Input current low voltage Loop Filter (Pin 4) VCO tuning voltage Output frequency range 915 MHz-band VLF fOUT, 915 VS - 1.74 905 915 VS - 0.52 925 V MHz fVCO = 915 MHz VS-VLF = 0.4V...1.95V VFSEL = open I LPD1 I LPD2 30 1 A mA VS = 2.3 V ... VS VS = 1.9 V ... 2.1 V
ASK Modulation Data Input (Pin 6) ASK Transmit disabled ASK Transmit enabled Input bias current ASKDTA Input bias current ASKDTA ASK data rate VASKDTA VASKDTA IASKDTA IASKDTA fASKDTA -20 20 0 1.5 0.5 VS 30 V V A A kHz VASKDTA = VS VASKDTA = 0 V
Wireless Components
5-6
Specification, October 2001
TDA 5102
Reference
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25C ... +85C Parameter Symbol Min FSK Modulation Data Input (Pin 7) FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate Clock Driver Output (Pin 8) Output current (Low) Output current (High) Saturation Voltage (Low)1) Clock Divider Control (Pin 9) Setting Clock Driver output frequency fCLKOUT=3.57 MHz Setting Clock Driver output frequency fCLKOUT=894 kHz Input bias current CLKDIV Input bias current CLKDIV VCLKDIV VCLKDIV ICLKDIV ICLKDIV -20 30 0 0.2 V V A A pin open VCLKDIV = VS VCLKDIV = 0 V ICLKOUT ICLKOUT VSATL 1 5 0.5 mA A V VCLKOUT = VS VCLKOUT = 0 V ICLKOUT = 0.8 mA VFSKDTA VFSKDTA IFSKDTA IFSKDTA fFSKDTA -20 20 0 1.5 0.5 VS 30 V V A A kHz VFSKDTA = VS VFSKDTA = 0 V Limit Values Typ Max Unit Test Conditions
Crystal Oscillator Input (Pin 10) Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin Serial Resistance of the crystal Input inductance of the COSC pin FSK Switch Output (Pin 11) On resistance On capacitance Off resistance Off capacitance RFSKOUT CFSKOUT RFSKOUT CFSKOUT 10 1.5 220 6 pF k pF VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS 11 12 100 CCOSCmax 5 100 pF H H f = 7.15 MHz f = 7.15 MHz f = 14.3 MHz f = 14.3 MHz
Wireless Components
5-7
Specification, October 2001
TDA 5102
Reference
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25C ... +85C Parameter Symbol Min Power Amplifier Output (Pin 14) Output Power 2) at 915 MHz transformed to 50 Ohm. VFSEL = open POUT, 915 POUT, 915 POUT, 915 -2.3 -2.0 -1.7 0.2 2 3.2 1.8 4.9 7.2 dBm dBm dBm VS = 2.1 V VS = 3.0 V VS = 4.0 V Limit Values Typ Max Unit Test Conditions
Frequency Range Selection (Pin 15) Transmit frequency 915 MHz Transmit frequency 457 MHz Input bias current FSEL Input bias current FSEL VFSEL VFSEL IFSEL IFSEL -20 0 0.5 30 V V A A VFSEL = VS VFSEL = 0 V pin open
Crystal Frequency Selection (Pin 16) Crystal frequency 7.15 MHz Crystal frequency 14.3 MHz Input bias current CSEL Input bias current CSEL VCSEL VCSEL ICSEL ICSEL -25 50 0 0.2 V V A A pin open VCSEL = VS VCSEL = 0 V
1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA 2) Matching circuitry as used in the 50 Ohm-Output Testboard for 915 MHz operation. Range @ 2.1 V, +25C: 0.2 dBm +/- 1.0 dBm Temperature dependency at 2.1 V: +0.6 dBm@-25C and -1.5 dBm@+85C, reference +25C. Range @ 3.0 V, +25C: 2.0 dBm +/- 2.0 dBm Temperature dependency at 3.0 V: +0.9 dBm@-25c and -2.0 dBm@+85C, reference +25C. Range @ 4.0 V, +25C: 3.2 dBm +/- 2.7 dBm Temperature dependency at 4.0 V: +1.3 dBm@-25c and -2.2 dBm@+85C, reference +25C. Tolerances of the passive elements not taken into account. A smaller load impedance reduces the supply-voltage dependency. A higher load impedance reduces the temperature dependency.
Wireless Components
5-8
Specification, October 2001

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