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| a FEATURES Fully Compliant with Standard and Enhanced GSM Specification DC-350 MHz RF Bandwidths 80 dB Gain Control Range I/Q Modulation and Demodulation Onboard Phase Locked Tunable Oscillator On-Chip Noise Roofing IF Filters Ultralow Power Design 2.7 V-3.6 V Operating Voltage User-Selectable Power-Down Modes Small 44-Lead TQFP Package Interfaces Directly with AD20msp410 and AD20msp415 GSM Baseband Chipsets APPLICATIONS I/Q Modulated Digital Wireless Systems GSM Mobile Radios GSM PCMCIA Cards GSM 3 V Transceiver IF Subsystem AD6432 FUNCTIONAL BLOCK DIAGRAM BP SAW PLO IF SYNTH RF SYNTH PA AD6432 OP AMP GENERAL DESCRIPTION The AD6432 IF IC provides the complete transmit and receive IF signal processing, including I/Q modulation and demodulation, necessary to implement a digital wireless transceiver such as a GSM handset. The AD6432 may also be used for other wireless TDMA standards using I/Q modulation. The AD6432's receive signal path is based on the proven architecture of the AD607 and the AD6459. It consists of a mixer, gain-controlled amplifiers, integrated roofing filter and I/Q demodulators based on a PLL. The low noise, high-intercept variable-gain mixer is a doubly-balanced Gilbert-cell type. It has a nominal -13 dBm input-referred 1 dB compression point and a 0 dBm input-referred third-order intercept. The gain-control input accepts an external control voltage input from an external AGC detector or a DAC. It provides an 80 dB gain range with 27.5 mV/dB gain scaling, where the mixer and the IF gains vary together. The I and Q demodulators provide inphase and quadrature baseband outputs to interface with Analog Devices' AD7015 and AD6421 (GSM, DCS1800, PCS1900) baseband converters. An onboard quadrature VCO, externally phase-locked to the IF signal, drives the I and Q demodulators. The quadrature phase-locked oscillator (QPLO) requires no external components for frequency control or quadrature generation, and demodulates signals at standard GSM system IFs of 13 MHz, or 26 MHz with a reference input frequency of 13 MHz; or, in general, 1X or 2X the reference frequency. Maximum reference frequency is 25 MHz. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. This reference signal is normally provided by an external VCTCXO under the control of the radio's digital signal processor. The transmit path consists of an I/Q modulator and buffer amplifier, suitable for carrier frequencies up to 300 MHz and provides an output power of -17.5 dBm in a 50 system. The quadrature LO signals driving the I and Q modulator are generated internally by dividing by two the frequency of the signal presented at the differential LO port of the AD6432. In both the transmit and receive paths, onboard filters provide 30 dB of stopband attenuation. The AD6432 comes in a 44-lead plastic thin quad flatpack (TQFP) surface mount package. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997 AD6432-SPECIFICATIONS (T = +25 C, V = 3.0 V, GREF = 1.25 V unless otherwise noted) A P Parameter RX RF MIXER RF Input Frequency AGC Conversion Gain Variation Input 1 dB Compression Point Input Third-Order Intercept SSB Noise Figure RX IF AMPLIFIER AGC Gain Variation Input Resistance Operating Frequency Range GAIN CONTROL Total Gain Control Range Control Voltage Range at GAIN Gain Scaling Gain Law Conformance Bias Current at GREF Input Resistance at Gain INTEGRATED IF FILTER BPF Center Frequency IFS0 = 1 IFS0 = 0 BPF -3 dB BW IFS0 = 1 IFS0 = 0 I AND Q DEMODULATOR Demodulation Gain Output Voltage Range Output Voltage Common-Mode Level Output Offset Voltage Error in Quadrature Amplitude Match I/Q Output BW Output Resistance QUADRATURE IF PLL Operating Frequency Range Reference Frequency Voltage Level Reference Frequency Range Acquisition Time TRANSMIT MODULATOR Carrier Output Frequency Output Power Input 1 dB Compression Point I/Q Input Signal Amplitude I/Q Input Signal Required DC Bias I/Q Input BW I/Q Input Resistance I/Q Phase Balance I/Q Amplitude Balance Output Harmonic Content Carrier Feedthrough Sideband Suppression Conditions Min Typ Max 350 Units MHz dB dBm dBm dB dB k MHz dB V mV/dB dB A k ZIN = 150 : 0.2 V < VGAIN < 2.4 V At VGAIN = 2.4 V, ZIN = 150 At VGAIN = 0.2 V, RFIN = -25 dBm At ZIN = 150 , FRF = 246 MHz, FLO = 272 MHz, VGAIN = 0.2 V 0.2 V < VGAIN < 2.4 V at VGAIN = 0.2 V 10 Mixer+IF+Demod, 0.2 V < VGAIN < 2.4 V 0.2 -3 to +15 -13 0 10 -14 to 48 5 50 80 2.4 27.5 0.1 -0.5 20 fREF = 13 MHz "0" = Connect to Ground, "1" = Connect to VP "0" = Connect to Ground, "1" = Connect to VP fREF = 13 MHz "0" = Connect to Ground, "1" = Connect to VP "0" = Connect to Ground, "1" = Connect to VP 13 26 5 10 17 MHz MHz MHz MHz dB V V mV Degrees dB MHz k MHz mV p-p MHz s MHz dBm dBm V p-p V MHz k Degrees dB dBc dBc dBc dBc REV. 0 Differential Not Power Supply Independent Differential, VGAIN = GREF Differential from I to Q, IF = 13 MHz CLOAD = 10 pF Each Pin 0.3 1.5 -150 1 0.25 3 4.7 10 200 VPOS - 0.2 +150 3.5 50 25 Using 1 k, 1 nF Loop Filter 80 300 -17.5 14 2.056 1.2 1 100 1.5 0.1 -45 (3rd) -65 (5th) -33 -37 RLOAD = 150 , Power at Final 50 , FIF = 272 MHz RLOAD = 150 (Differential) Differential With LOs 2nd Harmonic 30 dBc Bellow Fundamental With LOs 2nd Harmonic 30 dBc Bellow Fundamental RLOAD = 150 FCARRIER = 272 MHz I and Q Inputs Driven In Quadrature -2- AD6432 Parameter LO PORT (LOLO and LOHI) Input Frequency Input Signal Voltage Range Input Resistance AUXILIARY OP AMPLIFIER Small Signal -3 dB Bandwidth Input Signal Voltage Range Input Offset Voltage Input Bias Current Output Signal Voltage Range POWER CONSUMPTION Supply Voltage Transmit Mode Receive Mode Sleep Mode OPERATING TEMPERATURE RANGE NOTES All reference to dBm is relative to 50 . Specifications subject to change without notice. Conditions Min 200 200 Typ Max 600 Units MHz mV p-p MHz V mV nA V V mA mA A C Differential Input Pull-Up Resistors to VPOS (Each Pin) 500 50 0.1 4 -150 VPOS - 2.1 VPOS - 0.2 3 13 13 <5 3.6 With RLOAD > 4 k 0.1 2.7 At VGAIN = 1.2 V -25 +85 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION PCAM GND PCAO QTXN PCAP VPPC QTXP TXPU VPTX 1 Supply Voltage VPDV, VPPX, VPDM, VPFL, VPPC, VPRX, to CMTX, CMRX, CMIF, CMD . . . . . . . . . . . . . . +3.6 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . -25C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering (60 sec) . . . . . . . . . . . +300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 44-lead TQFP package: JA = 126C. 44 43 42 41 40 39 38 37 36 35 34 ITXP ITXN GND MODO 2 VPDV 3 CMTX 4 LOLO 5 LOHI 6 CMRX 7 GND 8 RFLO 9 RFHI 10 GND 11 33 32 31 30 FREF GND IFS0 CMDM FLTR VPFL VPDM IRXP IRXN QRXP QRXN AD6432 TOP VIEW (Pins Down) 29 28 27 26 25 24 23 RXPU MXLO GREF CMIF IFLO VPRX CMIF Model AD6432AST Temperature Range -25C to +85C Package Description 44-Pin Plastic TQFP Package Option* ST-44 *ST = Thin Quad Flatpack. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6432 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -3- GAIN MXHI GND IFHI ORDERING GUIDE 12 13 14 15 16 17 18 19 20 21 22 AD6432 PIN FUNCTION DESCRIPTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Label GND MODO VPDV CMTX LOLO LOHI CMRX GND RFLO RFHI GND VPRX MXHI MXLO CMIF IFLO IFHI CMIF RXPU GAIN GREF GND QRXN QRXP IRXN IRXP VPDM VPFL FLTR CMDM IFS0 GND FREF VPPC PCAO GND PCAM PCAP TXPU QTXN QTXP ITXN ITXP VPTX Description PCB Ground TX Modulator Output LO2 Divided by 2 Supply Voltage On-Chip TX Mixer Common Differential RX Mixer LO2 Input Negative Differential RX Mixer LO2 Input Positive On-Chip RX Mixer Common PCB Ground Differential RX Mixer IF1 Input Negative Differential RX Mixer IF1 Input Positive PCB Ground RX Section Supply Voltage Differential RX IF1/IF2 Mixer Output Positive Differential RX IF1/IF2 Mixer Output Negative On-Chip RX IF2 Common Differential RX IF2 Input Negative Differential RX IF2 Input Positive On-Chip RX IF2 Common RX Enable (Power-Up) RX VGA Gain Control Input RX VGA Reference Voltage PCB Ground Differential Demodulator Q Output Negative Differential Demodulator Q Output Positive Differential Demodulator I Output Negative Differential Demodulator I Output Positive Demodulator Supply Voltage I/Q LO PLL Filter Cap. Supply Voltage I/Q LO PLL Filter On-Chip Demodulator Common IF2 Frequency Select Bit PCB Ground Reference Input (13 MHz for GSM) Auxiliary Op Amp Supply Voltage Auxiliary Op Amp Output PCB Ground Differential Auxiliary Op Amp Input Negative Differential Auxiliary Op Amp Input Positive TX Enable (Power-Up) Differential Modulator Q Input Negative Differential Modulator Q Input Positive Differential Modulator I Input Negative Differential Modulator I Input Positive TX Section Supply Voltage Function Not Bonded to IC AC Coupled, Drives 150 into 50 VPOS Ground AC Coupled, VPOS to VPOS - 100 mV AC Coupled, VPOS - 100 mV to VPOS Ground Not Bonded to IC AC Coupled AC Coupled Not Bonded to IC VPOS See Figure 30 See Figure 30 Ground AC Coupled AC Coupled Ground Off = Low < 0.6 V, On = High > 2.5 V 0.2 V-2.4 V Using 3 V Supply. Max Gain at 0.2 V 1.2 V typ Not Bonded to IC Internal 4.7 k Resistor in Series with the Output Internal 4.7 k Resistor in Series with the Output Internal 4.7 k Resistor in Series with the Output Internal 4.7 k Resistor in Series with the Output VPOS To VPOS with Good Decoupling Referenced to VPFL Ground "0" = Low < 0.6 V, "1" = High > 2.5 V Not Bonded to IC AC Coupled. Use 200 mV p-p Input Signal VPOS Active when TXPU Is High Not Bonded to IC 0.1 V to VPOS - 2.1 V 0.1 V to VPOS - 2.1 V Low < 0.6 V, High > 2.5 V DC Coupled, 1.2 V 514 mV DC Coupled, 1.2 V 514 mV DC Coupled, 1.2 V 514 mV DC Coupled, 1.2 V 514 mV VPOS -4- REV. 0 AD6432 R30 49.9 PCAP C9 0.1 F TXPU R11 1k VS1 QTXN R10 500 QTXP PCAM ITXN R12 0 VS1 VPTX DECOUPLING ITXP C28 0.1 F C5 0.01 F R25 1k R39 OPEN R34 0 PCAO R8 0 VS2 MODO PCAM PCAO QTXN PCAP QTXP VPPC TXPU VPTX ITXP ITXN GND R9 84 R2 0 VS1 VPDV DECOUPLING T1 C29 0.1 F C14 0.01 F R23 123 C15 100pF GND MODO 2 VPDV 3 CMTX 4 R14 249 LOLO 5 LOHI 6 CMRX 7 C1 100pF RFHI R3 49.9 C2 100pF GND 8 RFLO 9 RFHI 10 GND 11 12 13 14 15 16 17 18 19 20 21 22 1 C11 0.01 F C32 0.1 F VPPC DECOUPLING 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 C36 1000pF FREF GND IFS0 CMDM FLTR VPFL VPDM IRXP IRXN QRXP QRXN R6 0 C41 0.01 F C17 0.1 F C23 0.01 F C10 R1 1000pF 1k IFS0 R32 49.9 R7 0 VS1 FREF LOLO 6 1 2 C18 0.1 F AD6432 TOP VIEW (Pins Down) 29 28 27 26 25 24 23 4 3 RXPU MXLO GREF CMIF IFLO VPRX CMIF GAIN MXHI GND IFHI IRXP C6 47pF IRXN GREF J1 TXPU VS2 C7 4.7 F VS1 C30 0.1 F R31 0 C43 0.047 F MXHI GAIN C44 0.047 F MXLO C4 0.047 F IFLO R4 49.9 R5 49.9 C7 0.047 F C3 0.01 F C39 0.01 F GAIN C8 47pF QRXP J3 IFS0 J4 RXPU VS1 C7 4.7 F J5 GND GREF C40 0.01 F QXRN RXPU IFHI Figure 1. Characterization Board REV. 0 -5- AD6432 QTXN QTXP R9 R10 25 10k R2 10k QTX R22 50 R3 20k VDC R4 20k R8 20k R6 20k C1 0.1F 4 VP VP 5 6 7 10 9 8 R12 R13 25 10k VGREF R29 10k C13 0.1F 1 V+ R14 10k R18 10k ITXP ITXN R1 10k 1 2 3 14 13 12 R11 10k R17 10k R15 R20 10k 25 C2 1pF AD824 VN 11 VN R16 R19 10k 25 VDC ITX R21 50 R7 10k R5 10k VDC VP AD1580 NC 3 2 V- IRX R23 50 VN C4 0.1F 5 VN 6 7 VP C3 0.1F 8 VP A=1 AD830 Gm 4 3 2 IRXN IRXP INTERFACE BOX TO TEST INSTR ITX IFIN Gm 1 QTX MODO LOIP FREF IRX QRX QRX R24 50 VN 5 VN 6 7 VP C6 0.1F 8 VP Gm A=1 AD830 Gm C5 0.1F 4 3 2 1 QRXN QRXP RFHI PCAP MXOUT PCAO VS1 VS2 GND VP VN GAIN 3 2 1 TXPU R25 50 MXOUT RXPU VN C8 0.1F 5 VN 6 7 A=1 AD830 Gm 4 3 2 R30 20k MXLO MXHI R31 20k 2 3 1 VP C7 0.1F 8 VP Gm 1 1 INTERFACE BOX TO CHAR BOARD 2 ITXP RFHI IRXP 3 ITXN QTXP QTXN MXHI MXLO IFLO IRXN IFIN QRXP QRXN R26 50 4 Gm A=1 Gm 8 7 6 5 C9 0.1F VP R27 50 IFHI AD830 C11 0.1F VN 1 2 3 Gm VP 8 7 A=1 C10 0.1F VP R28 50 IFLO MODO IFHI PCAP LOIP J1 VS2 IFS1 IFS0 RXPU VS1 FREF PCAO Gm 6 C12 0.1F VN 4 AD830 VN 5 GND TXPU GAIN GREF GND NOTES: VP = +5V VN = -5V VP IFS0 Figure 2. Characterization Test Set -6- REV. 0 AD6432 SINGLE SIDEBAND Rx MIXER NOISE FIGURE - dB 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 150 -5 0 VGAIN = 2.4V 20 RIN = 50, IF = 45MHz RIN = 50, IF = 26MHz 15 VGAIN = 0.2V RIN = 50, IF = 13MHz RIN = 400, IF = 13MHz GAIN - dB 10 5 VGAIN = 1.5V 200 250 300 350 RF FREQUENCY - MHz 400 450 10 14 18 22 30 38 26 34 IF FREQUENCY - MHz 42 46 50 Figure 3. Rx Mixer Noise Figure vs. RF Frequency, TA = +25C, VPOS = 3 V, VGREF = 1.2 V, VGAIN = 0.2 V Figure 6. Mixer Conversion Gain vs. IF Frequency, TA = +25C, VPOS = 3 V, VGREF = 1.2 V, FRF = 250 MHz 900 800 SHUNT RESISTANCE - 700 600 500 400 300 200 100 50 100 150 200 250 300 350 400 FREQUENCY - MHz 450 500 CS VGAIN = 2.4V RS VGAIN = 0.2V RS VGAIN = 2.4V RS VGAIN = 1.2V CS VGAIN = 1.2V CS VGAIN = 0.2V 5.0 70 AMP/DEMOD, VPOS = 2.7V TO 3.6V 4.5 SHUNT CAPACITANCE - pF 60 50 GAIN - dB 4.0 40 3.5 30 3.0 20 MIXER, VPOS = 2.7V TO 3.6V 2.5 550 10 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE - C 60 70 80 90 Figure 4. Rx Mixer Input Impedance vs. RF Frequency, VPOS = 3 V, TA = +25C, VGREF = 1.2 V Figure 7. Rx Mixer Conversion Gain and IF Amplifier/ Demodulator Gain vs. Temperature, VGAIN = 0.2 V, VGREF = 1.2 V, FIF = 26 MHz, FRF = 250 MHz 16 14 INPUT - dBm (REFERRED TO 50) -10 12 10 8 GAIN - dB VGAIN = 0.2V -11 VPOS = 2.7V, TA = +85 C -12 VPOS = 2.7V, TA = +25 C VPOS = 3.6V, TA = +85 C 6 4 2 0 -2 -4 -6 150 VGAIN = 2.4V 175 200 225 275 250 RF FREQUENCY - MHz 300 325 350 VGAIN = 1.5V -13 -14 VPOS = 2.7V, TA = -25 C -15 VPOS = 3.6V, TA = -40 C -16 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5 Figure 5. Rx Mixer Conversion Gain vs. RF Frequency, TA = +25C, VPOS = 3 V, VGREF = 1.2 V, FIF = 26 MHz Figure 8. Rx Mixer Input 1 dB Compression Point vs. VGAIN, VGREF = 1.2 V, FRF = 250 MHz, FIF = 26 MHz REV. 0 -7- AD6432 70 VGAIN = 0.2V 60 0.3 IF AMP/DEMOD GAIN - dB 0.4 50 40 30 20 10 0 VGAIN = 0.5V GAIN ERROR - dB 0.2 IF AMP/DEMOD 0.1 MIXER 0 VGAIN = 1.5V VGAIN = 2.4V -0.1 -10 10 -0.2 15 20 25 30 35 INTERMEDIATE FREQUENCY - MHz 40 45 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5 Figure 9. IF Amplifier and Demodulator Gain vs. IF Frequency, TA = +25C, VPOS = 3 V, VGREF = 1.2 V Figure 12. Gain Error vs. Gain Control Voltage, TA = +25C, VPOS = 3 V, VGREF = 1.2 V, FRF = 250 MHz, FIF = 26 MHz 12000 11000 10000 CS VGAIN = 0.2V CS VGAIN = 1.2V RS VGAIN = 2.4V 3.8 3.6 DEMODULATOR QUADRATURE ERROR - Degrees 13000 4.0 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 10 15 20 25 30 35 40 DEMODULATOR VCO FREQUENCY - MHz 45 9000 8000 7000 6000 5000 4000 3000 10 RS VGAIN = 0.2V 15 20 CS VGAIN = 2.4V 3.2 3.0 2.8 RS VGAIN = 1.2V 2.6 2.4 2.2 2.0 50 25 30 35 40 IF INPUT FREQUENCY - MHz 45 Figure 10. IF Amplifier Input Impedance vs. Frequency, TA = +25C, VPOS = 3 V, VGREF = 1.2 V CAPACITANCE - pF 3.4 RESISTANCE - Figure 13. Demodulator Quadrature Error vs. FREF Frequency, TA = +25C, VPOS = 3 V 0 IF INPUT 1dB COMPRESSION REFERRED TO 50 OHMS - dBm -80 -10 PHASE NOISE - dBc/Hz -85 -20 -90 IF = 26MHz -95 -30 -40 -100 -50 -105 IF = 13MHz -60 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5 -110 0.1 1.0 10 100 FREQUENCY OFFSET - kHz 1000 Figure 11. IF Amplifier/Demodulator Input 1 dB Compression Point vs. VGAIN , FIF = 26 MHz, VGREF = 1.2 V, TA = +25C, VPOS = 3 V Figure 14. PLL Phase Noise vs. Frequency, VPOS = 3 V, CFLTR =1 nF, RFLTR =1 k, FREF = 13 MHz -8- REV. 0 AD6432 0 -0.2 FILTER PIN VOLTAGE REFERENCED TO VPOS - Volts 12 16 14 -0.4 TA = -40 C -0.6 TA = +25 C -0.8 -1.0 -1.2 -1.4 10 TA = +85 C CONVERSION GAIN - dB 10 8 6 4 2 0 -2 -4 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5 15 20 25 30 35 40 45 50 FREQUENCY OF VCO - MHz Figure 15. PLL Loop Voltage at FLTR Pin (KVCO) vs. Frequency Figure 18. Rx Mixer Conversion Gain vs VGAIN, TA = +25C, VPOS = 3 V, FRF = 250 MHz, FIF = 26 MHz, VGREF = 1.2 V -10 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5 -30 -40 -50 -60 -70 0 0.5 1.0 1.5 GAIN VOLTAGE - Volts 2.0 2.5 Figure 16. System (Mixer + IF LC Filter + IF Amplifier + Demodulator) 1 dB Compression Point vs. VGAIN, TA = +25C, VPOS = 3 V, FRF = 250 MHz, FIF = 26 MHz, VGREF = 1.2 V Figure 19. IF Amplifier/Demodulator Gain vs. VGAIN, TA = +25C, VPOS = 3 V, FRF = 250 MHz, FIF = 26 MHz, VGREF = 1.2 V IF AMP/DEMODULATOR GAIN - dB INPUT 1dB COMPRESSION POINT REFERRED TO 50 OHMS - dBm -20 0 -10 80 70 60 SYSTEM GAIN - dB SYSTEM INPUT IP3 REFERRED TO 50 OHMS - dBm -20 -30 -40 -50 -60 -70 0 0.5 1.0 1.5 2.0 2.5 GAIN VOLTAGE - Volts 50 40 30 20 10 0 0 0.5 1.0 1.5 GAIN VOLTAGE - Volts 2.0 2.5 Figure 17. System (Mixer + IF LC Filter + IF Amplifier + Demodulator) IP3 vs. VGAIN, TA = +25C, VPOS = 3 V, FIF = 26 MHz, FRF = 250 MHz, VGREF = 1.2 V Figure 20. System (Mixer + IF LC Filter + IF Amplifier + Demodulator) Gain vs. VGAIN, TA = +25C, VPOS = 3 V, FIF =26 MHz, FRF = 250 MHz, VGREF = 1.2 V REV. 0 -9- AD6432 -16.0 TRANSMIT DESIRED SIDEBAND GAIN - dB -35.0 -35.5 -16.5 TYPICAL UNDESIRED SIDEBAND SUPPRESSION - dBc -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -17.0 -17.5 -18.0 -18.5 -19.0 -19.5 -20.0 -40 -20 0 20 40 60 TEMPERATURE - C 80 100 -40.0 100 120 140 160 180 200 220 240 260 CARRIER FREQUENCY - MHz 280 300 Figure 21. Tx Desired Sideband Gain vs. Temperature, TA = +25C, VPOS = 3 V, FCARRIER = 280 MHz, I and Q Inputs Driven in Quadrature Figure 24. Tx Typical Undesired Sideband Suppression vs. FCARRIER, TA = +25C, VPOS = 3 V -13.5 22 VPOS = 3.6V, TA = +85 C 20 VPOS = 2.7V, TA = +85 C VPOS = 3.6V, TA = +25 C VPOS = 3V, TA = +25 C VPOS = 2.7V, TA = +25 C 16 TRANSMIT DESIRED SIDEBAND GAIN - dB -14.0 -14.5 SUPPLY CURRENT - mA -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 -18.5 -19.0 100 120 140 160 180 200 220 240 260 CARRIER FREQUENCY - MHz 280 300 18 14 12 VPOS = 2.7V TA = -40 C 10 0 0.5 VPOS = 3.6V TA = -40 C 1.0 1.5 GAIN VOLTAGE - Volts 2.0 2.5 Figure 22. Tx Desired Sideband Gain vs. FCARRIER, TA = +25C, VPOS = 3 V Figure 25. Rx Mode Supply Current vs. VGAIN, VGREF = 1.2 V -35.0 -35.5 -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40 -20 0 20 40 60 TEMPERATURE - C 80 100 15.0 14.5 Tx MODE SUPPLY CURRENT - mA TYPICAL UNDESIRED SIDEBAND SUPPRESSION - dBc VPOS = 3.6V 14.0 13.5 13.0 VPOS = 2.7V 12.5 12.0 11.5 11.0 10.5 -40 VPOS = 3V -20 0 20 40 60 TEMPERATURE - C 80 100 Figure 23. Tx Typical Undesired Sideband Suppression vs. Temperature, TA = +25C, VPOS = 3 V Figure 26. Tx Mode Supply Current vs. Temperature -10- REV. 0 AD6432 PRODUCT OVERVIEW The AD6432 provides most of the active circuitry required to realize a complete low power, single-conversion superheterodyne time division transceiver, or the latter part of a doubleconversion transceiver, at input receive frequencies up to 350 MHz with an IF from 10 MHz to 50 MHz and transmit frequencies up to 300 MHz. The internal I/Q demodulators, with their associated phase-locked loop and the internal I/Q modulator, support a wide variety of modulation modes, including n-PSK, n-QAM, and GMSK. A single positive supply voltage of 3 V is required (2.7 V minimum, 3.6 V maximum) at a typical supply current of 13 mA at midgain in receive mode and 13 mA in transmit mode. In the following discussion, VPOS will be used to denote the power supply voltage, which will be assumed to be 3 V. Figure 27 shows the main sections of the AD6432. In the receive path, it consists of a variable-gain UHF mixer and linear two-stage IF strip, both of which together provide a calibrated voltage-controlled gain range of more than 80 dB, followed by a tunable IF bandpass filter and dual quadrature demodulators. These are driven by inphase and quadrature clocks generated by a Phase-Locked Loop (PLL) locked to a corrected external reference. In the transmit path it consists of a quadrature modulator followed by a low-pass filter. The quadrature modulator is driven by quadrature frequencies that are generated internally by dividing the external local oscillator frequency by two. A CMOS-compatible power-down interface completes the AD6432. 4.7k 25 IRXN RFHI 10 MXOP 13 IFIP 16 4.7k 3MHz 4.7k 26 IRXP RFLO 9 14 LC BANDPASS FILTER 17 23 QRXN MXOM IFIM 90 0 QUADRATURE VCO DIVIDE BY 1 OR 2 PHASE DETECTOR GAIN TEMP. COMPENSATION 4.7k 24 QRXP 31 IFS0 33 FREF 29 FLTR 20 GAIN LOHI 6 2 LOLO 5 0 90 RX, TX BIAS 21 GREF 19 RXPU 39 TXPU AD6432 42 ITXN 43 ITXP MODO 2 40 QTXN 41 QTXP 38 PCAP PCAO 35 37 PCAM Figure 27. Functional Block Diagram REV. 0 -11- AD6432 Receive Mixer 250 MXOP VPRX 250 MXOM The UHF mixer is an improved Gilbert-cell design that can operate from low frequencies (it is internally dc-coupled) up to an RF input of 350 MHz. The dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of 71 mV (-13 dBm in 50 between RFHI and RFLO) up to which the mixer remains linear and, at the lower end, by the noise level. It is customary to define the linearity of a mixer in terms of the 1 dB gain-compression point and thirdorder intercept, which for the AD6432 are -13 dBm and 0 dBm, respectively, in a 50 system. The mixer's RF input port is differential, that is, pin RFLO is functionally identical to RFHI, and these nodes are internally biased. The RF port can be modeled as a parallel RC circuit as shown in Figure 29. The local oscillator input of the receive mixer is internally provided by the LO divided by two. RFHI CSH RFLO RSH Figure 30. Mixer Output Port IF Amplifier Most of the gain in the AD6432 receive section is provided by the IF amplifier strip, which comprises two stages. Both are fully differential and each has a gain span of 31 dB for the AGC voltage range of 0.2 V to 2.4 V. Thus, in conjunction with the variable gain of the mixer, the total gain span is 80 dB. The overall IF gain varies from -14 dB to +48 dB for the nominal AGC voltage of 0.2 V to 2.4 V. Maximum gain is at VGAIN = 0.2 V. The IF input is differential, at IFHI and IFLO. Figure 32 shows a simplified schematic of the IF interface modeled as parallel RC network. The operative range of the IF amplifier is approximately 50 MHz from IFHI and IFLO through the demodulator. IFHI CSH RSH Figure 28. Mixer Port Modeled as a Parallel RC Network At V GAIN = 1.2 V and F RF = 250 MHz, C SH = 3.5 pF and RSH = 400 (See Figure 4) The output of the mixer is differential. The nominal conversion gain is specified for operation into a 26 MHz LC IF bandpass filter, as shown in Figure 29 and Table I. C1 MXOP IFIP IFLO Figure 31. IF Amplifier Port Modeled as a Parallel RC Network for VGAIN = 1.2 V and F IF = 26 MHz, CSH = 3 pF, RSH = 8.5 k (See Figure 10) Gain Scaling C2 L1 C1 MXOM IFIM Figure 29. Suggested IF Filter Inserted Between the Mixer's Output Port and the Amplifier's Input Port The overall gain of the AD6432, expressed in decibels, is linear with respect to the AGC voltage VGAIN at Pin GAIN. The gain of all sections is maximum when VGAIN is 0.2, and falls off as the bias is increased to VGAIN = 2.4 V and is independent of the power supply voltage. The gain of all stages changes simultaneously. The AD6432's gain scaling is also temperaturecompensated. Note that GAIN pin of the AD6432 is an input driven by an external low impedance voltage source, normally a DAC, under the control of radio's digital processor. The gain-control scaling is directly proportional to the reference voltage applied to the Pin GREF and is independent of the power supply voltage. When this input is set to the nominal value of 1.2 V, the scale is nominally 27.5 mV/dB (36.4 dB/V). Under these conditions, 80 dB of gain range (mixer plus IF) corresponds to a control voltage of 0.2 V < = VG < = 2.4 V. The final centering of this 2.2 V range depends on the insertion losses of the IF filters used. Pin GREF can be tied to an external voltage reference, VREF, provided, for example, by a AD1580 (1.21 V) voltage reference. When using the Analog Devices AD7013 (IS54, TETRA and satellite receiver applications) and AD7015 or AD6421 (GSM, DCS1800, PCS1900) baseband converters, the external reference may also be provided by the reference output of the The conversion gain is measured between the mixer input and the input of this filter, and varies between -3 dB and +15 dB. Table I. Filter Component Values for Selected Frequencies Frequency 13 MHz 26 MHz C1 27 pF 22 pF L1 0.82 H 0.39 H C2 180 pF 82 pF The maximum permissible signal level between MXOP and MXOM is determined by the maximum gain control voltage. The mixer output port, having pull-up resistors of 250 to VPRX, is shown in Figure 30. -12- REV. 0 AD6432 baseband converters. The interface between the AD6432 and the AD6421 baseband converter is shown in Figure 35. The AD7015 baseband converter provides a VR of 1.23 V; an auxiliary DAC in the AD7015 can be used to generate the AGC voltage. Since it uses the same reference voltage, the numerical input to this DAC provides an accurate RSSI value in digital form, no longer requiring the reference voltage to have high absolute accuracy. Tunable Filter and I/Q Demodulators integral sample-hold system ensures that the frequencycontrol voltage on Pin FLTR remains held during powerdown, so reacquisition of the carrier occurs in less than 80 s. In practice, the probability of a phase mismatch at powerup is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. This is typically < 80 s for a locking error of 3 at an IF of 26 MHz. Note that the VFQO always provides quadrature between its own I and Q outputs, but the phasing between it and the reference carrier will swing around the final value during the PLL's settling time. I and Q Transmit Modulator The demodulators (I and Q) receive their inputs internally from the IF amplifier through a two-pole tunable-frequency bandpass filter. This filter is centered on the IF frequency and its bandwidth is approximately equal to forty per cent of the IF frequency. The filter attenuates the amount of noise present at the input of the demodulators. Each demodulator comprises a full-wave synchronous detector followed by a 3 MHz, two-pole low-pass filter, producing differential outputs at pins IRXP and IRXN, and QRXP and QRXN. Using the I and Q demodulators for IFs above 50 MHz is precluded by the 10 MHz to 50 MHz range of the PLL used in the Demodulator section. The I and Q outputs are differential and can swing up to 2 V p-p at the low supply voltage of 2.7 V. They are nominally centered at 1.5 V independent of power supply. They can therefore directly drive the receive ADCs in the AD7015 or AD6421 baseband converters, which require an amplitude of 1.23 V to fully load them when driven by a differential signal. The conversion gain of the I and Q demodulators is 17 dB. A simple 1-pole RC filter at the I and Q outputs, with its corner above the modulation bandwidth is sufficient to attenuate undesired outputs. The design of the RC filter is eased by the 4.7 k resistor integrated into each I and Q output pin. Phase-Locked Loop The transmit modulator uses two standard mixer cells whose linear inputs are the differential voltages at the input Pins ITXP/ITXN and QTXP/QTXN, respectively and whose local oscillator inputs are derived from a divide-by-two cell, driven from the input applied to pins LOHI/LOLO. The outputs of the mixers are summed and converted to singlesided form. The output stage also filters the higher harmonics, minimizing the need for filtering before this signal is presented to the up-converter in a typical transmitter configuration. The I and Q inputs are intended to be driven using a fully-differential drive (for example from an AD7015 or AD6421) and need to be biased to a common-mode dc level of 1.2 V, with a typical differential amplitude of 1.028 V (that is, 514 mV at each input). Some small variation in the drive conditions is allowable, but will result in nonoptimal performance. The minimum instantaneous input should not go below 0.6 V and the maximum voltage should not exceed 1.8 V using a 2.7 V supply (in general, VP - 0.9 V). The impedance at these inputs is several M in parallel with approximately 1 pF; the bias currents flow out of the pins and are ~100 nA. These conditions permit the use of a high impedance low-pass filter if desired ahead of the modulator inputs. The dc modulator output is at a constant dc level of 1.5 V, independent of temperature and supply voltage. It is designed to drive a 150 load and should either be matched into a 50 load, using a simple LC network, or padded to 150 with a series 100 resistor (Figure 33). The output is short-circuit-proof. The output modulated signal at pin MODO has a power of -16 dBm when driving a 50 load with a 100 series resistor, as shown in Figure 33. This power is specified at a carrier frequency of 272 MHz with a maximum dc differential signal applied to the I or Q channel while the other channel has no differential signal applied. The transmit modulator is enabled only when the TXPU input (Pin 39) is taken HI. 100pF 100 50 MODO The demodulators are driven by quadrature signals that are provided by a variable-frequency quadrature oscillator (VFQO), phase-locked to the reference frequency. This frequency is equal or double the frequency of the signal applied to Pin FREF. When the quadrature signals are at the IF, inphase and quadrature baseband outputs are generated at the I output (IRXP and IRXN) and Q output (QRXP and QRXN), respectively. The quadrature accuracy of the VFQO is typically within 1 at 26 MHz. A simplified diagram of the FREF input is shown in Figure 32. VPOS 5k 20k FREF 5k 50 A PTAT Figure 32. Simplified Schematic of the FREF Interface The VFQO is controlled by the voltage between VPOS and FLTR. In normal operation, a series RC network, forming the PLL loop filter, is connected from FLTR to VPOS. The use of an REV. 0 -13- Figure 33. Output Impedance of Pin MODO Is Designed to Drive a 50 Load with a 100 Series Resistor AD6432 Local Oscillator Input USING THE AD6432 The Local Oscillator (LO) input port is differential and consists of two functionally identical pins, LOHI and LOLO. It accepts a signal of 200 mV p-p at a frequency between 200 MHz and 600 MHz. Inputs LOHI and LOLO are internally biased to the positive supply (Pin 3) through 500 resistors. While not usually needed, these inputs may be driven through a simple matching network to lower the LO power required from a 50 source. Single-sided drives are not recommended. The most noticeable effects will be degradation of phase balance and an increase in phase noise. This signal is fed internally to a divider by two that generates the mixing signals for the receive mixer and the transmit modulator. In order to meet the phase and amplitude balance of the transmit quadrature modulator, as stated in the specification table, the duty cycle of the LO signal must be such that the second harmonic is at least 30 dBc below the fundamental. I/Q Convention In this section, we will focus on a few areas of special importance through the real life example of interfacing the AD6432 to the AD6421 Base Band converter. As is true of any wideband high gain components, great care is needed in PC board layout. The location of the particular grounding points must be considered with due regard for the possibility of unwanted signal coupling. The high sensitivity of the AD6432 leads to the possibility that unwanted local EM signals may have an effect on the performance. During system development, carefully-shielded test assemblies should be used. The best solution is to use a fully enclosed box enclosing all components, with the minimum number of needed signal connectors (RF, LO, I and Q outputs) in miniature coax form. Interfacing the AD6432 to the AD6421 Baseband Converter The AD6421 Baseband Converter contains all the necessary elements to drive the AD6432. Receive Interface The AD6432 is a complete IF subsystem. Although not a requirement for using the AD6432, most applications will use a high side LO injection on the receive mixer. The I and Q convention on the receive section is such that when a spectrum with I leading Q is presented to the input of the receive mixer and a high side LO is presented to the receive mixer, I still leads Q at the baseband output of the AD6432. Likewise, the I and Q convention on the transmit section is such that when a spectrum with I leading Q is presented at the baseband input of the modulator, I still leads Q at the output of the modulator. Auxiliary Op Amp The interface between the two devices provides for quadrature I and Q channels that can be driven either differentially or in the single-ended configuration. Figure 35 shows the interface between the AD6432 and the AD6421 for the differential configuration. The respective pins (IRXP, IRXN, QRXP and QRXN) are dc coupled through 4.7 k resistors, which are integrated within the AD6432. Balanced coupling may be used with a single 50 pF capacitor between the complementary signals as illustrated in Figure 35. This low-pass filter is the only external filter required to prevent aliasing of the baseband analog signal prior to sampling within the AD6421. The AD6421 has an external autocalibration mode that can calibrate out any offsets resulting from the IF demodulation circuitry. Transmit Interface An auxiliary operational amplifier is available although it is important to remember that it is active only when TXPU is high. The positive and negative input terminals are PCAP and PCAM with PCAO being the output pin. The inputs are the bases of PNP transistors with a typical bias current of approximately 150 nA. The input offset voltage is typically < 4 mV and the open loop gain of the amplifier is 60 dB. The amplifier is unity gain stable with a -3 dB Bandwidth greater than 40 MHz. The input signal voltage range is from 0.1 V to VPOS - 2.1 V. Bias System The AD6432 operates from a single supply, VPOS, usually 3 V, at a typical supply current in receive mode of 13 mA at midgain and TA = +25C, corresponding to a power consumption of 39 mW. Any voltage from 2.7 V to 3.6 V may be used. The bias system includes a fast-acting active high CMOS-compatible power-up switch, allowing the part to idle at less than 100 A when disabled. Biasing is generally proportional-toabsolute temperature (PTAT) to ensure stable gain with temperature. Other special biasing techniques are used to ensure very accurate gain, stable over the full temperature range. The corresponding transmit (ITXP, ITXN, QTXP and QTXN) pins of the AD6421 and AD6432 are directly connected as these have compatible bias levels for dc coupling. To meet the more stringent phase two filter mask requirements, an external lowpass filter may be required, depending on the filtering capabilities of the radio section. A passive second order low-pass filter network with a cutoff frequency to 600 kHz is suggested as shown in Figure 34. Resistor values should range from 1.5 k-3.0 k to minimize AD6432 offsets. ITXP ITXP ITXN ITXN AD6432 QTXP QTXP AD6421 QTXN QTXN Figure 34. GSM Phase II Transmit Interface -14- REV. 0 AD6432 Gain Control The AD6432 contains a Gain TC Compensation circuit that provides a nominal 80 dB dynamic range of automatic gain control. The GAIN input pin of the gain circuit is driven by the AD6421 Automatic Gain Control DAC (AGCDAC), an integrated auxiliary DAC of the AD6421, controllable by the radio's digital processor. This connection should be made through a single pole RC to reduce high frequency noise into the gain control circuit. The values shown in Figure 35 provide a -3 dB point at approximately 1 MHz, sufficient for the gain control. Gain control scaling is directly proportional to the reference voltage applied to Pin GREF and is independent of the power supply voltage. A nominal 1.2 V reference for GREF can be provided by the AD6421 through BREFOUT. BREFOUT is a buffered output version of BREFCAP reference. This reference output feature is enabled on the AD6421 by setting Bit 2 in control register BCRB (BCRB2). See AD6421 data sheet. The VGAIN input range for this control signal is 0.2 V- 2.4 V where gain is maximum at 0.2 V and falls off as VGAIN is increased to 2.4 V. To avoid saturating the input to the baseband converter, the automatic gain control function of the receiver must limit the output signal swing of the AD6432 to 1.2 V, the full signal range of the input. Phase-Lock Loop Control ITXP ITXN QTXP QTXN IRXP 50pF ITXP ITXN QTXP QTXN IRXP IRXN QRXP 50pF QRXN MCLK 1k VCTCXO 100nF FREQUENCY SYNTHESIZER 0.1 F BREFOUT AGCDAC 1nF POWER CONTROL RAMDAC AFCDAC BREFCAP AD6432 IRXN QRXP QRXN 1nF FREF LOHI LOLO GREF AD6421 160 MXLO GAIN MXHI IFLO LC BANDPASS FILTER Figure 35. AD6432 to AD6421 Interface Transmit Power Control The AD6432 PLL/QVCO circuits require an external frequency reference for coherent modulation and demodulation of the baseband and IF signal. The external frequency reference control for the AD6432 PLL/QVCOs is typically generated through a 13 MHz voltage controlled temperature compensated crystal oscillator (VCTCXO). The control voltage for the VCTCXO is generated by an auxiliary DAC in the AD6421 designated as the Automatic Frequency Control DAC (AFCDAC). The PLL loop is closed through the radio's algorithm signal processor, which drives the AD6421 AFCDAC. The AD6432 FREF pin provides the VCTCXO reference signal to the AD6432 RX quadrature VCO (QVCO) circuit. The AD6432 FREF input must be an ac coupled signal 200 mV p-p or greater. The reference for the UHF TX QVCO and RX IF down converter is synthesized from the VCTCXO output reference signal through an external frequency synthesizer and VCO. This UHF reference is an ac coupled input into AD6432 LOHI and LOLO pins. An external series RC network connected between FLTR (Pin 29) and the VPOS supply pin provides the proper loop filter for the VCO/PLL as shown in Figure 35. A general purpose amplifier is available on the AD6432, which may be useful as part of an automatic control circuit for the power amplifier. Open ended, this amplifier will swing full scale from rail to rail. It is recommended that this amplifier be connected in the unity feedback configuration when not being used by connecting PCAO to PCAM. AD6432 EVALUATION BOARD The AD6432 Evaluation Board is designed to enable measurements of key parameters on the AD6432 IFIC, a device that provides the complete transmit and receive IF signal processing, including I/Q modulation and demodulation, necessary to implement a digital wireless transceiver. Many of the signal paths into and out of the AD6432 are differential, which is the preferred interface to and from single supply CODECS. To facilitate an interface to traditional lab equipment, the following interface circuitry is included on the board. A 20-pin Berg strip for bias, gain and Inphase and Quadrature signal interface. End Launch SMA connectors for RF, LO, MODO and FREF signals and provisions for breaking out MXOP and IFHI with RF transformers. A single-ended to differential RF transformer provides a balanced LO drive. An onboard 1.2 V dc reference IC is provided for application to GREF. REV. 0 -15- IFHI AD6432 Evaluation Board Description Interface Connector (Berg Strip) Pin Description This four layer board demonstrates both the transmit and receive functions of the AD6432. The top internal layer is a ground plane and the bottom internal layer is a strategically partitioned power plane with DUT power and bipolar support device power. A 20-pin Berg strip connector provides the external power and dc signal interface, which includes power-up, gain and external reference bias options. The various high frequency IF, LO, TX Modulation output (MODO) and the Demodulator Reference (FREF) are brought in and out of the board via end-launch SMA connectors. Appropriate terminations are provided for each signal. Several hardware jumpers are provided for bias and IF selection options. Figure 36 shows the placement of the different connectors used on the evaluation board. Building up a simple IDC connector/ribbon cable breakout to a vector board or box with banana plugs will facilitate testing. Figure 37 shows the signal's placement and Table II describes each signal. PCAM PCAO QRXN QRXP PCAP GREF QTXN RXPU QTXP TXPU GAIN IRXN IRXP ITXN GND ITXP GND IFS0 VS2 VS1 BOARD EDGE Figure 37. Evaluation Board Interface Connector MODO FREF J21 U1 OPTLO T1 J23 Q1 J22 RFHI AD6432 EVAL. REV. B MXOP IFIP J26 J24 J25 Figure 36. Evaluation Board Layout (Top View) Note: MXOP, IFHI, OPTLO are optional SMA connectors not supplied with the evaluation board. INTERFACE CONNECTOR LOINP 1 -16- REV. 0 AD6432 Table II. Connector Signal Description Table III. SMA End-Launch Connectors Pin Name GND ITXP ITXN QTXP QTXN TXPU PCAM PCAP VS2 VS1 PCAO IFS0 IRXP IRXN QRXP QRXN GREF SMA Description Analog and Power Ground. I Channel Transmit Plus Modulation Input. I Channel Transmit Minus Modulation Input. Q Channel Transmit Plus Modulation Input. Q Channel Transmit Minus Input. Transmit Section Power-Up. This function is also jumper selectable with J21. Auxiliary Op Amp Minus Input. Auxiliary Op Amp Plus Input. Power control op amp supply 2.7 V dc-3.6 V dc. The jumper, J26, connects VS1 and VS2 together. AD6432 main supply 2.7 V dc-3.6 V dc. Auxiliary Op Amp Output. Selects IF Pin. This function is also jumper programmable with J25. I Channel Receive Plus Modulation Output. I Channel Receive Minus Modulation Output. Q Channel Receive Plus Modulation Output. Q Channel Receive Plus Modulation Output. The AD6432 gain reference bias which is optimized for 1.2 V dc. This may be externally supplied; or by shorting J23, supplied directly from the AD1580 SOT-23 onboard, 1.2 V reference. Max RX gain occurs at 0.2 V dc. Minimum gain occurs at 2.4 V dc. Receive Section Power-Up. This function is also jumper selectable with J22. MODO Connector Description Transmit Modulator Output. This pin, which is designed to drive a 150 filter, has been resistively matched (loss) onboard to drive a 50 instrument such as a spectrum analyzer. Local Oscillator Input pin. This is actually fed with twice the LO frequency from a generator for both transmit and receive. The nominal LO level is -16 dBm (50 ). Optional differential minus local oscillator input (transformer can be removed). RF input Mixer Output (optional output that may be converted to single ended output with an RF transformer). IF Input (optional single ended input that may be converted to differential with an RF transformer). Frequency Reference for phase locked receive demodulator. The internal VCO frequency is equal to FREF in the 1X mode and equal to two times FREF in the 2X mode. LOIP OPTLO RFHI MXOP IFHI FREF GAIN RXPU Power Requirements The evaluation board uses two supplies, VS1 and VS2. VS1--2.7 V dc-3.6 V dc, 13 mA typical. This is the main supply for the AD6432. VS2--2.7 V dc-3.6 V dc, 2 mA typical. This is the supply for the on-chip op amp which is normally used in RF power control circuits. The op amp is active only in the Transmit mode. REV. 0 -17- AD6432 VS1 R19 20k TXPU PCAP R30 1k J21 QTXN QTXP ITXN ITXP R12 0 VS1 VPTX DECOUPLING MODO R9 84 R2 0 VS1 VPDV DECOUPLING C29 0.1 F C14 0.01 F C28 0.1 F C5 0.01 F C11 0.01 F R25 1k R39 OPEN PCAM R34 0 PCAO R8 0 C32 0.1 F VS2 VS1 J26 FREF PCAM GND PCAO PCAP QTXN QTXP VPPC TXPU VPTX ITXP ITXN R23 123 C15 100pF GND 1 MODO 2 VPDV 3 CMTX 4 J24 R18 20k IFS1 R17 20k J25 C10 R1 1nF 1k IFS0 R7 0 VS1 C23 0.01 F R6 0 C41 0.01 F C17 0.1 F 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 C36 1nF FREF GND IFS0 CMDM FLTR VPFL VPDM IRXP IRXN QRXP QRXN LOIP R20 OPEN OPTLO R21 0 6 T1 1 2 R35 125 R14 125 C18 0.1 F LOLO 5 LOHI 6 CMRX 7 GND 8 RFLO 9 RFHI 10 GND 11 AD6432 TOP VIEW (Pins Down) 29 28 27 26 25 24 23 4 3 C1 100pF RFHI R3 49.9 TX GND C2 100pF 12 13 14 15 16 17 18 19 20 21 22 IRXP C6 47pF IRXN QRXP GREF RXPU MXLO GREF CMIF IFLO VPRX CMIF ITXP ITXN QTXP QTXP TXPU PCAM PCAP VS2 C50 4.7 F C12 4.7 F PCAO GND IFS0 IRXP IRXN 1 QRXP QRXN GREF GAIN RXPU 20A 20B MXOP T2 6 4 IFIP 2 3 C42 0.01 F R6 OPEN L1 OPEN C18 OPEN L3 SHORT C19 22pF C20 82pF VS1 VS1 VS1 C30 0.1 F R31 0 C3 0.01 F RXPU C21 0.1 F GAIN J22 R15 20k MXHI GAIN GND IFHI C8 47pF QXRN J23 C44 0.01 F Q1 R16 TP1580 10k VS1 L2 SHORT C16 22pF L4 0.39 H R13 OPEN C43 0.01 F 1 T3 6 4 2 3 Figure 38. Evaluation Board Schematics -18- REV. 0 AD6432 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Thin Quad Flatpack (TQFP) (ST-44) 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 34 33 0.472 (12.00) SQ 23 22 SEATING PLANE TOP VIEW (PINS DOWN) 0.394 (10.0) SQ 44 1 11 12 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35) 0.031 (0.80) BSC 0.018 (0.45) 0.012 (0.30) REV. 0 -19- -20- C3061-12-4/97 PRINTED IN U.S.A. |
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