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Features
* * * * * * * *
4 Multiplier-Accumulators 40 Bits Accuracy 16 Bit Data and Coefficients 4-tap Filter With 27 MHz Sample Rate Programmable to Give up to 256 Taps With Sampling Reducing Proportionally to 421,875 kHz Programmable Rounding and Truncation to 16 Bit 8 Bit Standard Microprocessor Interface 64-pin PQFP, 68-pin PGA68 or 68-pin LCC68 Packaging
Description
The AT76C001 Programmable Finite Impulse Response (FIR) Filter implements a 4th order FIR cell built around 4 multiplier-accumulators. It contains a dual-port RAM and a RAM which are used to implement FIR filters of up to 256 taps. High order filters are achieved by multiplexing the 4th order cell and accumulating the intermediate results up to 40 bits, so that there is no loss of accuracy. The maximum frequency of the AT76C001 is 27 MHz. For 4-tap FIR filter, the incoming sample rate can be as high as 27 MHz. For higher order FIR filters, the sample rate can be as high as the circuit frequency divided by the 4th order cell multiplexing factor. A programmable normalization block allows the choice of the 16 significant bits from the 40 bit internal result which can be previously rounded by adding 0.5 LSB according to the 16 significant bit locations. The AT76C001 has a microprocessor interface which can be configured to be Intel or Motorola compatible.
CBIC Programmable FIR Filter AT76C001
Applications
* * *
Digital Filters (video, audio, etc.) Correlation Image Processing
AT76C001
Pin Description
Name Pin Number QFP64 Packaging LCC68 Packaging PGA68 Packaging IN<15:0> DIV RST_X1 OUT<15:0> DOV DATA<7:0> CS DS/WR RDWR/RD ADD<1:0> RESET CLOCK 34-40, 42, 44-51 33 32 18-12, 10, 8-1 19 21-24, 26, 28-30 52 53 54 63-64 31 56 27-33, 35, 37-44 26 24 9-3, 1, 67-60 10 13-16, 18, 20-22 46 47 48 57-58 23 50 55 12 K10-11, J10-11, H1011, G10, F10, E10-11, D10-11, C10-11, B11-10 L10 K9 K1, J1-2, H1-2, G1-2, F2, E2, D1-2, C1-2, B12, A2 K2 L3, K4, L4, K5-7, L7, K8 B9 A9 B8 A4, B3 L8 B7 A5 K3 I I I O O I/O I I I I I I I I Input sample Input sample valid. Active low Force input sample to 0. Useful for interpolation implementation Output filtered sample Output filtered sample valid. Active low Microprocessor interface data bus. Used for accessing internal registers and to write the coefficients of the filter Chip select. Active low Microprocessor interface data strobe (Motorola mode) or Write signal (Intel mode). Active low Microprocessor interface Read/Write signal (Motorola mode) or Read signal (Intel mode). Active low Microprocessor interface address bus Circuit master reset. Active low Circuit clock (27 MHz max) For internal use. Connect to ground For internal use. Connect to ground Power supply (+5V) Ground No connection Type Function
CLOCK_BIST 61 TEST_BIST VCC GND NC 20
11, 27, 43, 58, 60, 2, 19, 36, 52, 54, B4-6, F1, F11, L6 62 56 9, 25, 41, 55, 57, 17, 34, 49, 51, 53 59 11, 25, 45, 59 A6-8, E1, G11, L5 A3, A10, L2, L9
51
50
49
48
47
46
45
44
43
VCC
42
41
GND
40
39
38
37
36
35
34
33
DIV
RST-XI
IN5
IN0
IN1
IN2
IN3
IN4
IN6
IN7
IN8
IN9
IN14
IN10
IN11
52 53 54 55 56 57 58 59 60 61 62 63 64
IN12
IN15
IN13
CS DS/WR RDWR/RD GND CLOCK GND VCC GND VCC CLOCK_BIST(0) VCC ADD1 ADD 0
32 31 30 29 28 27 26 25 24 23 22 21 20
RESET DATA0 DATA1 DATA2 VCC
AT76C001 QFP64
DATA3 GND DATA4 DATA5 DATA6 DATA7 TEST_ BIST (0)
DOV
OUT11
OUT12
OUT13
OUT10
OUT14
GND
1 (0): Connect to GND
2
3
4
5
6
7
8
9
10
11
VCC
12
13
14
15
16
17
18
OUT15
OUT1
OUT6
OUT0
OUT2
OUT3
OUT4
OUT5
OUT7
OUT8
OUT9
19
Plan View of AT76C001 in QFP64 Package
2
AT76C001
AT76C001
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NC*
GND
VCC
RST_XI
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
RESET
DATA6
DATA7
27
28
IN15
IN14
TEST_BIST(0)
DOV
NC*
DIV
OUT15 OUT14
9
8
29 30 31 32 33 34 35 36 37 38
39
IN13 IN12 IN11 IN10 IN9 GND IN8 VCC IN7 IN6
IN5
O UT13 O UT12 O UT11 O UT10 O U T9 VC C
7 6 5 4 3 2 1 68 67 66
65
AT76C001 LCC68
O UT 8 GND O U T7 O U T6
OU T5
40 41 42 43
IN4
CLOCK_BIST(0)
O UT 4 OUT3 OUT2 OUT1
OUT0 ADD1 ADD0 VCC NC*
64 63 62 61
IN3
RDWR/RD
IN2 IN1
NC* IN0 CS DS/WR
CLOCK
GND
GND
GND
VCC
44 45 (0): Connect to GND
VCC
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 * No Connection
Plan view of AT76C001 in LCC68 package
1 L
2 NC*
3
4
5 GND
6 VCC
7
8
9 NC*
10 DIV
11
DATA7 DATA5
DATA1 RESET
K OUT15
DOV
TC(0)
DATA6 DATA4 DATA3 DATA2 DATA0 RST_XI
IN15
IN14
J OUT14 OUT13
IN13
IN12
H OUT12 OUT11
IN11
IN10
G OUT10
OUT9
IN9
GND
F
VCC
OUT8
AT76C001 PGA68
IN8
VCC
E
GND
OUT7
IN7
IN6
D
OUT6
OUT5
IN5
IN4
C
OUT4
OUT3 RDWR/ RD GND
IN3
IN2
B
OUT2
OUT1
ADD0
VCC
VCC
VCC
CLOCK
CS
IN0
IN1
A
OUT0
NC*
ADD1
CB(0)
GND
GND
DS/WR
NC*
(0): Connect to GND
* No Connection
Plan view of AT76C001 in PGA68 package
3
Block Diagram
ADD<1:0> CS D S/ W R R DW R /R D RST -XI DI V CL OC K RESET
DOV
C ontrol U nit
Internal Control Signals
D AT A < 7 :0>
Register
Coefficient RAM
Register
Normalisation
Fourth Order FIR Cell
OU T <15:0>
IN<15:0>
Register
Multiplexer
Sam ple RAM
Fourth Order FIR Cell
Fro m D ATA< 7 :0 > Fro m IN<1 5 :0 > Fro m Control U ni t
Mu x
Mul t
Mu x
Register
Mul t
Mu x
Mul t
Mu x
Mul t
Register
Register
Register
Register
Add
Add
Add
Add
Register
Register
Register
Register
To Normalisation
4
AT76C001
AT76C001
Functional Description
The AT76C001 has an architecture built around a 4-tap non-recursive filter cell. This allows a 4-tap filter to be implemented, e.g. y(n) = a(0)x(n) + a(1)x(n-1) + a(2)x(n-2) + a(3)x(n-3) where x = 16 bit incoming sample y = 16 bit filtered sample a = 16 bit coefficient This operating mode is called `single mode'. The AT76C001 can implement up to 256-tap filters by multiplexing the 4th order structure, using internal RAMs. Nth order FIR filters can be divided into P 4th-order FIR sub-filters where P is the integer part of (N+3)/4. Thus the complete filter is evaluated by accumulating the contributions of each elementary 4th order sub-filter: y(n) = y(n,0) + y(n,1) + ....... + y(n,P-1) where y(n,j) = a(4j)x(n-4j) + a(4j+1)x(n-4j-1) + a(4j+2)x(n-4j-2) + a(4j+3)x(n-4j-3) j = number of the sub-filter This operating mode is called `sequential mode'. If (N+3)/4 is greater than P, then some coefficients of the last sub-filter will be set to zero automatically by the circuit. In single mode, the incoming sample rate can be as high as the circuit frequency (27 MHz). A new incoming sample is notified by a low level on DIV input signal and clocked by the rising edge of the circuit clock CLOCK. If there is a low level set on DIV and then a low level is set on RST_XI input, then a `zero' sample is fed internally into the circuit. For each new sample, a filtered sample is calculated. Valid output filtered samples are notified by a low level on DOV output signal. The timing diagram below illustrates the single mode operation. In sequential mode, an N-tap filter is divided into P 4-tap filters. Consequently, the incoming sample rate must be at least P times slower than the circuit rate. As in single mode, a new incoming sample is notified by a low level on DIV input signal and clocked by the rising edge CLOCK. But here, DIV defines a temporal window where XIN is valid and whose width must be at least one CLOCK period and at most P-1 clock periods. The timing diagrams below illustrate the case for an N-tap filter, where N is greater than 4 but less than 9, i.e., DIV must go to high level between two incoming signals.
Timing Diagram for Single Mode Operation
CLOCK
DIV
Input valid
RST_XI
Input forced to 0
IN
X0
X1
X2=0
X3=0
X4
X5
X6
X7=0
X8
OUT
Y0
Y1
Y2
Y3
Y4
Y5
Y6
DOV
Output valid
5
Microprocessor Interface
The AT76C001 has an 8 bit configurable microprocessor interface comprising the following signals: DATA <7:0> AD- <1:0> CS DS/WR RDWR/RD 8 bit data bus 2 bit address bus Chip Select Data Strobe or Write signal Read/Write signal or Read signal
Internal Registers
The AT76C001 contains three internal registers accessible in Read and Write via the microprocessor interface, as soon as it is configured and locked. They are: Configuration register (CFGR) Normalization and Rounding Register (NORR) Filter Order Register (FILR)
Configuration Register
By setting bit 1 of the configuration interface (INTEL/ MOTO), it is possible to configure the microprocessor interface to be Motorola or Intel compatible. When chosen, the configuration must be locked by setting bit LOCK_CFG of the configuration register. This must be done first of all otherwise the circuit will not function properly.
Configuration Intel/Moto bit Signals Motorola Mode Bit set to 0 DATA<7:0> ADD<1:0> CS DS RD/WR Intel Mode Bit set to 1 DATA<7:0> ADD<1:0> CS WR RD
It is an 8 bit register mapped at address 1hex = 01bin Bit 0 = START/STOP Bit 1 = INTEL/MOTO Bit 2 = MSB/LSB Activates/deactivates filtering Configures microprocessor interface to be Intel or Motorola. Indicates if 16 bit coefficients are written with Most Significant Byte or Least Significant Byte ahead. Locks the microprocessor interface configuration. Indicates the operating mode of the 4th order cell, i.e. Single Mode or Sequential Mode. Indicates that the sample input buffer contains N samples when implementing an N-tap FIR filter.
Bit 3 = LOCK_CFG Bit 4 = SING/SEQ
Bit 5 = BUFF_FULL
(continued)
Timing Diagram for N-tap Filter where 4CLOCK
DIV
RS T_ XI
IN
X0
X1
X2 = 0
X3
X4 = 0
X5 = 0
OUT
Y0
Y1
Y2
Y3
Y4
DO V
6
AT76C001
AT76C001
Internal Registers (Continued)
Bit 6 = LAST_SFILT Indicates that the last sub-filter is accessed.
Filter Order Register
Bit 7 = END_INCOEFF Indicates that the last coefficient of the last sub-filter is being accessed.
Bit No Bit Name Acc. Mode Reset Value 7 END_IN COEFF R 1 6 5 4 SING/ SEQ R 0 3 CFG LOCK R/W 0 2 INT/ MOTO R/W 0 1 0 LAST_S BUFF_ FILT FULL R 0 R 1 MSB/LSB START/ STOP R/W 1 R/W 0
The filter order register is an 8 bit register mapped at address 3h=11b. It contains the number of the order of the filter to be implemented minus 1. Reset Values
Bit No Bit Name Acc. Mode Reset Value 7 FILT7 R/W 0 6 FILT6 R/W 0 5 FILT5 R/W 0 4 FILT4 R/W 0 3 FILT3 R/W 0 2 FILT2 R/W 0 1 FILT1 R/W 0 0 FILT0 R/W 0
Normalization and Rounding Register
Coefficient Writing
Filter coefficients are stored internally by writing to address 0hex = 00bin. The bit MSB/LSB of the configuration register indicates if the MSB is sent before the LSB and vice versa. Stored coefficients are not readable via the microprocessor interface. For an N-tap filter, 2xN writing is necessary. If N is not a multiple of 4, the remaining coefficients of the last sub-filter are set automatically to zero.
The normalization and rounding register is a 5 bit register mapped at address 2h = 10b allows the selection of the 16 bit significant part of the internal 40 bit result; also defines the number of bits rounding value if rounding is desired. Bit <3:0>= SEL <3:0> Selects the 16 bit part and defines the number of bits rounding value as illustrated in the following table:
Rounding Value (Hex) 00 0000 8000 00 0001 0000 00 0002 0000 00 0004 0000 00 0008 0000 00 0010 0000 00 0020 0000 00 0040 0000 00 0080 0000
Application Examples
A 4-Tap FIR Filter in Motorola Mode
Bit 3:0 0000 0001 0010 0011 0100 0101 0110 0111 1XXX
OUT<15:0> RES<31:16> RES<32:17> RES<33:18> RES<34:19> RES<35:20> RES<36:21> RES<37:22> RES<38:23> RES<39:24>
Example with coefficient MSB ahead and rounding enabled. yn = c0xn + c1xn-1 + c2xn-2 + c3xn-3 Where yn is the output filtered sample, c is the coefficient and x is the incoming samples. 1. Firstly, unlock the microprocessor interface by writing a zero to bit 3 (this is normally performed by applying a Master reset). 2. Write 1100bin in the configuration register. This sets the configuration with bit 0 selecting stop mode, bit 1 selecting Motorola mode, bit 2 selecting MSB ahead, and bit 3 locks the configuration. 3. Write the Filter Order-1 in the FILT_ORD register, i.e. 03hex. 4. Write the 4 coefficients starting with the Most Significant Byte of c0, then the LSB of c0, etc. 5. Write 00010bin in the NORM register to enable rounding, and to select range of bits, for example bits 33 to18 of the 40 bit internal result. 6. Write 1101bin in the Configuration register to start the filter. At each new incoming sample, XIN, specified by a low level on DIV. The filtered sample XOUT is calculated and is notified by a low level on DOV. The
Bit 4 = ROUNDEN
Enables/disables rounding of the 40 bit result before normalization.
4 3 SEL3 R/W 0 2 SEL2 R/W 0 1 SEL1 R/W 0 0 SEL0 R/W 0
Bit No Bit Name Access Mode Reset Value
ROUNDEN R/W 0
(continued)
7
Application Examples (Continued)
filtered XOUT is output 4 clock cycles after the sampling of the corresponding XIN input.
A 130-Tap FIR Filter in Intel Mode
Absolute Maximum Ratings (Continued)
TA TSG Temperature range Storage temperature -40 -65 +85 +150 C C Industrial
Example with coefficient LSB ahead and rounding disabled. yn=c0xn + c1xn-1 + ....... + c128xn-12 + c129xn-129 Firstly, unlock the microprocessor interface by writing a zero to bit 3 (this is normally performed by applying a Master reset). Write 1010bin in the configuration register. This sets the configuration with bit 0 selecting stop mode, bit 1 selecting Intel mode, bit 2 selecting LSB ahead, and bit 3 locks the configuration. Write the Filter Order-1 in the FILT_ORD register, i.e. 81hex Write the 130 coefficients beginning with the LSB of c0, then the MSB of c0, etc. Write 11xxx in the NORM register to disable rounding and to select bits 39 to 24 of the 40 bit internal result.. Write 1011bin in the Configuration register to start the filter. At each new transition high to low on DIV input signal, a new sample is fed into the filter. The corresponding filtered sample is output 4+33 clock cycles later and specified by a low level on DOV output signal. Here the incoming sample rate must at most be 33 times less than the circuit clock rate, where 33 represents the number of times the 4th order cell is multiplexed.
Recommended Operating Conditions
Symbol VDD VI VO TA TR TF Parameter DC supply voltage DC input voltage DC output voltage Temperature range Input rise time Input fall time Min 4.5 0 0 -40 Typ 5.0 5.0 5.0 Max 5.5 VDD VDD +85 15 15 Unit V V V C ns ns Ind 10%-90% CMOS 10%-90% CMOS Conditions
1.
2.
3. 4. 5. 6.
DC Characteristics
Symbol IIH IIL Parameter Input leakage, no pullup Input leakage, no pullup Highimpedance output current bi-directional pins Low level input voltage High level input voltage Low level output voltage High level output voltage Input capacitance VDD0.5 7 70% VDD 0.5 Min -1.0 -1.0 Max +1.0 +1.0 Unit uA uA Conditions VIN = VDD = 5.5V VIN = 0 VDD=5.5V
IOZ
-1.0
+1.0
uA
VDD=5.5V
VIL VIH VOL VOH
30% VDD
V V V V pF
CMOS inputs and bi-dir CMOS inputs and bi-dir IOL=5.0mA IOH=5.0mA
Electrical Specifications
Absolute Maximum Ratings
Symbol VDD VI VO +-IIk +-IOk IOLMAX IOHMAX TSH Parameter DC supply voltage DC input voltage DC output voltage DC input diode current DC output diode current Continuous output current Continuous output current Time of outputs shorted Min -0.5 -0.5 -0.5 Max 5.5 VDD+ 0.5V VDD+ 0.5V 10 20 10 10 5 Unit V V V mA mA mA mA sec or see +-IIk or see +-IOk VI<-0.5V VI>VDD+0.5V VO<-0.5V VO>VDD+0.5V Industrial Industrial Conditions
CIN
(continued)
8
AT76C001
AT76C001
AC Characteristics
Code TCPH TCLH TCLL TWRP TWRH TWRL TSIS TSIH TSOD TWRCLD TACWS TACWH TAOE TAOD Description Clock period Clock high Clock low Write/read period Write/read high Write/read low Synchronous signals to rising clock setup Synchronous inputs to rising clock hold Synchronous outputs to rising clock delay Write/read to clock high Asynchronous input setup Asynchronous inputs hold Asynchronous output enable Asynchronous output disable 5 20 5 12 7 Min 37 15 15 37 15 15 5 5 10 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
See the illustration below for the interpretations of these characteristics.
AC Characteristics for Single Mode Operation
T CL P TC LL
C LOC K
T CL H TS IS TS IH
RST_XI DIV XIN T SO D DOV
XOUT D S Motorola WR Intel RD Intel CS R D / W R M otor ola ADD TAOE D AT A DATA IN DATA O UT T AO D T WR L TWR CLD TWRH TACWS TWRP TACWH
9

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