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TDA7319
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
ONE STEREO INPUT ONE STEREO OUTPUT TWO INDEPENDENT VOLUME CONTROL IN 1.0dB STEPS TREBLE, MIDDLE AND BASS CONTROL IN 1.0dB STEPS ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DESCRIPTION The TDA7319 is a volume and tone (bass , middle and treble) processor for quality audio application in car radio and Hi-Fi system. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. BLOCK DIAGRAM AND APPLICATION CIRCUIT
R1 2.7K C3 5.6nF TREBLE(L) 3 C1 2.2F L 2 1st VOL TREBLE MIDDLE BASS C5 15nF MOUT(L) 5 C6 22nF 6 C9 100nF BIN(L) 7 2nd VOL R3 5.6K C10 100nF BOUT(L)
DIP20
SO20
ORDERING NUMBERS: TDA7319 (DIP20) TDA7319D (SO20)
Thanks to the used BIPOLAR/MOS Technology, Low Distortion, Low Noise and Low Dc stepping are obtained.
MIN(L) 4
8
OUT L
10 9 11 19 R 1st VOL TREBLE MIDDLE BASS 2nd VOL
SCL SDA DIGGND I2C BUS
SERIAL BUS DECODE & LATCHES C2 2.2F
13
OUT R
VS
1
SUPPLY 12 AGND CREF 20 TREBLE(R) CREF 10F C4 5.6nF 18 MIN(R) 17 MOUT(R) C7 15nF R2 2.7K C8 22nF 16 15 BIN(L) C11 100nF R4 5.6K 14 BOUT(R) C12 100nF
D93AU042E
May 1995
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TDA7319
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
PIN CONNECTION
VS IN L TREBLE L M IN L M OUT L B IN L B OUT L OUT L SDA SCL
1 2 3 4 5 6 7 8 9 10
D93AU041A
20 19 18 17 16 15 14 13 12 11
CREF IN R TREBLE R M IN R M OUT R B IN R B OUT R OUT R GND DIG GND
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-pins DIP20 150 SO20 150 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz 1st and 2nd Volume Control 1dB step Bass, Middle and Treble Control 1dB step Mute Attenuation -47 -14 100 Parameter Min. 6 2 0.01 106 100 0 +14 0.08 Typ. 9 Max. 10.5 Unit V Vrms % dB dB dB dB dB
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ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K; f = 1KHz; all control = flat (G = 0); Tamb = 25C Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT
Rin Input Resistance 35 50 65 K
1st VOLUME CONTROL
CRANGE AVMAX Astep EA Et Amute VDC Control Range Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error Mute Attenuation DC Steps 45 45 0.5 -1.0 -1.5 47 47 1.0 49 49 1.5 1.0 1.5 1 2 3 5 dB dB dB dB dB dB dB dB mV mV
G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB G = 24 to -47dB Adiacent Attenuation Steps From 0dB to AVMAX
80
100 0 0.5
2nd VOLUME CONTROL
CRANGE AVMAX Astep EA Et AMUTE VDC Control Range Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error Mute Attenuation DC Steps 45 45 0.5 -1.0 -1.5 47 47 1.0 49 49 1.5 1.0 1.5 1 2 3 5 dB dB dB dB dB dB dB dB mV mV
G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB G = 24 to -47dB Adiacent Attenuation Steps From 0dB to AVMAX
80
100 0 0.5
BASS
Rb CRANGE Astep Internal Feedback Resistance Control Range Step Resolution 32 11.5 0.5 44 14 1 56 16 1.5 K dB dB
MIDDLE
Rb CRANGE Astep Internal Feedback Resistance Control Range Step Resolution 18 11.5 0.5 13 0.5 25 14 1 14 1 32 16 1.5 15 1.5 K dB dB
TREBLE
CRANGE Astep Control Range Step Resolution dB dB
SUPPLY
VS IS SVR Supply Voltage (note1) Supply Current Ripple Rejection 6 4 60 9 7 90 10.5 10 V mA dB
AUDIO OUTPUT
Vclip ROl RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2 2 100 2.6 180 3.8 300 Vrms K V 3/16
TDA7319
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit V dB dB dB dB %
GENERAL
eNO Et S/N SC d Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation Distortion All Gains 0dB (B = 20 to 20kHz flat) AV = 0 to -24dB AV = -24 to -47dB All Gains = 0dB; VO = 1Vrms 80 AV = 0; Vin = 1Vrms 5 0 0 106 100 0.01 15 1 2
0.08
BUS INPUTS
Vil Vih Iin VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge 1 Vin = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 V V A V
Note 1: the device is functionally good at Vs = 5V. A step down, on VS, to 4V does't reset the device.
APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) with a 1dB step. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7319 audioprocessor provides 3 bands tones control. Bass, Middle Stages The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri = 44K typical. The Middle cell has an internal resistor Ri = 25K typical. Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT pins. Figure 1.
The fig.1 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: FC = 1 2 Ri, R2, C1, C2 R2 C2 + R2 C1 + Ri C1 R2 C1 + R2 C2 Ri R2 + C1 C2 R2 C1 + R2 C2
AV =
Q=
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: C1 = AV - 1 2 Ri Q C2 = Q2 C1 AV - 1 Q2
R2 =
Ri internal IN C1 R2
D95AU313
AV - 1 - Q2 2 C1 FC (AV - 1) Q
OUT C2
Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25K typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 10 to 13. CREF The suggested 10F reference capacitor (CREF) value can be reduced to 4.7F if the application requires faster power ON.
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TDA7319
Figure 2: Noise vs. volume setting Figure 3: SVRR vs. frequency
Figure 4: THD vs. frequency
Figure 5: THD vs. RLOAD
Figure 6: Channel separation vs. frequency
Figure 7: Output clip level vs. Supply voltage
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TDA7319
Figure 8: Quiescent current vs. supply voltage Figure 9: Quiescent current vs. temperature
Figure 10: Bass response
Figure 11: Middle response
Ri = 44k C9 = C10 = 100nF (Bout, Bin) R3 = 5.6k
Ri = 25k C9 = 15nF (MIN) C6 - 22nF (MOUT) R1 = 2.7k
Figure 12: Treble response
Figure 13: Typical tone response
CTREBLE = 5.6nF
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TDA7319
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7319 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Data Validity on the I2CBUS Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it generates the 9th clock pulse without checking the slave acknowledging, and then sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Timing Diagram of I2CBUS
Acknowledge on the I2CBUS
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TDA7319
SDA, SCL I2CBUS TIMING
Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DA tSU:DAT tR tF tSU:STO SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Parameter Min. 0 1.3 0.6 1.3 0.6 0.6 0.300 100 20 20 0.6 300 300 Typ. Max. 400 Unit kHz s s s s s s ns ns (*) ns (*) s
All values referred to VIH min. and VIL max. levels (*) Must be guaranteed by the I2C BUS master.
Definition of timing on the I2C-bus
SDA tBUF tR tF tHIGH tHD;STA tSP tSU;STO
SCL tLOW P S tHD;STA tF tSU;STA tSU;DAT Sr P
tHD;DAT
D95AU314
P = STOP S = START
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TDA7319
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7319 address (the 8th bit of the byte must be 0). The TDA7319 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
TDA7319 ADDRESS
MSB S 1 0
first byte 0 0 0 1 A
LSB 0 ACK
MSB DATA
LSB
AC K
MSB DATA
LSB
AC P K
Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 400kbits/s
SOFTWARE SPECIFICATION Chip address
1 MSB 0 0 0 0 1 1 0 LSB
FUNCTION CODES
MSB 1st VOLUME 2nd VOLUME TREBLE MIDDLE BASS MUTMUX 0 0 1 1 1 1 F6 F6 F6 0 0 1 1 F5 F5 F5 0 1 0 1 F4 F4 F4 F4 F4 F4 F4 F3 F3 F3 F3 F3 F3 F3 F2 F2 F2 F2 F2 F2 F2 F1 F1 F1 F1 F1 F1 F1 LSB 0 1 F0 F0 F0 F0
POWER ON RESET: 1st volume = 2nd volume = Mute Treble = Middle = Bass = -14dB Mutmux = Active Input
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TDA7319
1st VOLUME CODES
MSB 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 F6 F5 F4 F3 F2 F1 LSB 0 FUNCTION step 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB step 8dB 0dB -8dB -16dB -24dB -32dB -40dB MUTE
2nd VOLUME CODES
MSB 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 F6 F5 F4 F3 F2 F1 LSB 1 FUNCTION step 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB step 8dB 0dB -8dB -16dB -24dB -32dB -40dB MUTE
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TDA7319
TREBLE CODES
MSB 1 F6 0 F5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION TREBLE BOOST 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 14dB TREBLE CUT 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -14dB
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TDA7319
MIDDLE CODES
MSB 1 F6 0 F5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION MIDDLE BOOST 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 14dB MIDDLE CUT 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -14dB
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TDA7319
BASS CODES
MSB 1 F6 1 F5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION BASS BOOST 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 14dB BASS CUT 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -14dB
MUTMUX CODES
MSB 1 F6 1 F5 1 F4 X X X X F3 X X X 1 F2 X X X 1 F1 0 0 1 1 LSB 0 1 0 1 FUNCTION INPUTS NOT ALLOWED NOT ALLOWED NOT ALLOWED IN
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TDA7319
SO20 PACKAGE MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.4 0.5 12.6 10 1.27 11.43 7.6 1.27 0.75 8 (max.) 0.291 0.020 13.0 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.394 0.050 0.450 0.299 0.050 0.030 0.512 0.419 0.1 mm TYP. MAX. 2.65 0.3 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.012 0.096 0.019 0.013
14/16
TDA7319
DIP20 PACKAGE MECHANICAL DATA
DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 mm TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
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TDA7319
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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