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| ASAHI KASEI [AK2048] AK2048D 2M CMI Transceiver FEATURES - 2.048Mbps CMI Interface - CLOCK & DATA Recovery function - Loss of Lock Detection - Loss of Signal Detection - Transmitter Pulse Shape - Single 5.0V5% Operation - Low Power Consumption: 400mW (TYP) - Package: 44pin QFP BLOCK DIAGRAM TXA TXB TDATA DRIVER CMI ENCODER TCLK TCRV LOS RXA RXB LOS CLOCK RECOVER CMI DECODER RDATA RCRV RCLK RESET VREF CALIB LOCK LOCK RST REF25 RVDD RVSS TVDD TVSS 2M CMI Transceiver Block Diagram MS0073-E-00 1 2001/01 ASAHI KASEI [AK2048] GENERAL DESCRIPTIONS AK2048D is the 2.048Mbps CMI interface CMOS LSI for CMI interface card. It includes Clock and Data Recovery, Line Driver, LOS Detector, etc. Build in PLL clock recovery circuit eliminates the correlation of the frequency deviation due to the uneven quality of the devices and a secular change. PIN ASSIGNMENTS 44pin QFP RVDD RVSS RST NC NC NC NC NC NC NC 44 RDATA RCLK RCVR NC NC NC NC NC TDATA TCLK TCRV 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RXA NC REF25 NC RXB NC NC TXA TVDD TVSS TXB 1 2 3 4 5 6 7 8 9 10 11 12 NC (TOP VIEW) NC 28 27 26 25 24 23 13 TEST1 14 TEST2 15 LOCK 16 LOS 17 NC 18 NC 19 NC 20 NC 21 NC 22 NC MS0073-E-00 2 2001/01 ASAHI KASEI [AK2048] PIN ASSIGNMENTS Pin No. 1 2 3 9 10 11 13 14 15 16 23 24 25 26 29 31 33 40 41 Pin Name RDATA RCLK RCRV TDATA TCLK TCRV TEST1 TEST2 LOCK LOS TXB TVSS TVDD TXA RXB REF25 RXA RVDD RST I/O O O O I I I O O O O I O I I Type TTL TTL TTL TTL TTL TTL AC Load (MAX) 15pF 15pF 15pF DC Load (MIN) 4k 4k 4k Comment *2) *2) TTL TTL Analog 15pF 15pF 15pF 4k 4k *1) Analog Analog Analog Analog TTL 15pF 1F(typ) *1) Pulled up to VDD by the internal register (50Kmin) 42 RVSS - The other pins (4-8,12,17-22,27,28,30,32,34-39,43,44) are NC pins. NC pins are recommended to connect to VSS to avoid noise problem. *1) TXA, TXB can drive 110 connected between these pins. *2) Must be open. MS0073-E-00 3 2001/01 ASAHI KASEI [AK2048] PIN DESCRIPTIONS Pin Name RDATA RCLK RCRV I/O O O O Function Receive Data output recovered from the incoming data. Delay time from the incoming data to the RDATA is about 1.25bit. Output on the rising edge of RCLK. Receive Clock Output recovered from the incoming data. CRV (Code Rule Violation) output pin. When AK2048D detects the CRV of CMI codes from in the coming "1" data. Refer to Fig.6, 11 data, RCRV goes to "high" synchronized with the violation data. CRV is detected for both "0" data and TDATA TCLK TCRV I I I Transmit Data Input pin. Input on the falling edge of TCLK. Transmit Clock Input pin. If this input is "high", AK2048D generates CRV in the transmit data. CRV is generated for both "0"data and "1"data. "High" input TCRV is accepted until 5 clocks duration. If the duration of "High" input is longer than 6 clocks, TCRV input after 6th clock is ignored. Refer to Fig.4, 11 TEST1 TEST2 LOCK NC NC O Test pin. Should be floated. Test pin. Should be floated. LOCK indicates the PLL status whether PLL is in the LOCK status or PLL is in the UNLOCK status. LOCK status LOCK becomes "Low" when the sampled RCLK are all "Low" during the consecutive 32 RXA-RXB sample clock duration. UN LOCK status LOCK becomes "High" when the following both conditions are satisfied. - The sampled RCLK are "High" more than 5 clocks in the frame of the consecutive 256 RXA-RXB clock duration. - And the above happens in the 5 consecutive frames. In another condition, LOCK keeps the current output status without change. The output timing of this signal is asynchronous with RCLK. When RST is "Low", LOCK is fixed to "High". MS0073-E-00 4 2001/01 ASAHI KASEI [AK2048] Pin Name LOS TXB TVSS TVDD TXA RXB REF25 RXA RVDD RST I/O O O O I O I O Function LOS goes High within 12usec after AK2048D detects that the amplitude of the RXB input signal is lower than 135mVpp(typ). Output on the rising edge of RCLK. Transmit CMI signal output. TXA is to CMI+, and TXB is corresponds to CMI-. Delay time from TDATA to TXB is about 1bit. Negative power supply 0V Positive power supply 5V Transmit CMI signal output. TXA is to CMI+, and TXB is corresponds to CMI-. Delay time from TDATA to TXA is about 1bit. Receive CMI signal input. RXA is to CMI+, and RXB is corresponds to CMI-. Output reference voltage (about 2.5V) in order to decide middle point of input signal (RXA-RXB). Connected to middle point of the external equalizer. Receive CMI signal input. RXA is to CMI+, and RXB is corresponds to CMI-. Positive power supply. 5V "Low" input reset the calibration circuit and forces LOCK output "High" and TXA-TXB output "High-Z". When this input rise, PLL calibration restarts. Please set open or connect to VDD when not using. RVSS - Negative power supply 0V MS0073-E-00 5 2001/01 ASAHI KASEI [AK2048] ABSOLUTE MAXIMUM RATINGS Parameter DC Supply Input Voltage Input Current 1 Input Current 2 (TXA, TXB, RXA, RXB) Storage Temperature Tstg -65 150 C Symbol DVDD TVDD VIN I IN1 I IN2 RVSS-0.3 RVDD+0.3 V 10 200 mA mA *1) Min -0.3 Typ 6.0 Max V Units Conditions *1) Except for TXA, TXB, RXA, RXB RECOMMENDED OPERATING CONDITIONS Parameter DC Supply Ambient Operating Temperature Power Consumption PD1(RVDD) PD2(TVDD) 150 250 300 300 mW mW 110 LOAD Symbol RVDD TVDD Ta 0 25 +80 C min 4.75 5.0 typ max 5.25 V Unit Conditions TVDD Condition: VDD=5.0V5%, VSS=0V,Ta=0~80C Parameter Digital High-level input voltage Digital Low-level input voltage Digital High-Level output voltage Digital Low-level output voltage Input leak current 1 Input leak current 2 *1) When CMOS load is connected, output CMOS logic level. Symbol VIH VIL VOH VOL 2.4 0.5 10 100 min 2.4 0.8 typ max Unit V V V V A A IOUT=-40A *1) IOUT=1.6mA *1) Without RST, TEST1 RST, TEST1 Conditions MS0073-E-00 6 2001/01 ASAHI KASEI TRANSMITTER Parameter Symbol Va Output signal level VpeakH VpeakL Rise/Fall Time Pulse duty of transmit output Tr, Tf 43 2.55 20 50 50 57 ns % min 2.55 typ 3.3 max 3.90 4.05 Vp-p Unit [AK2048] Comments Refer to Fig.1, 2 Refer to Fig.1, 2 *1), *2) Refer to Fig.3 *3)Refer to Fig.4 Delay time from TDATA to TXA,TXB Ttd 1 Bit *1) The duty cycle of TCLK 50%4%. *2) Duty cycle = Tpwh / (Tpwh + Tpwl) x 100% *3) Signal output delay = (1bit logical delay) + (internal propagation delay) TXA 56 110 56 TXB Transmit output amplitude is specified at this point. (Va, VpeakH, VpeakL) Fig.1 Measurement circuit VpeakH Va VpeakL 0.8Va Tr,Tf Fig.2 Rise and fall times MS0073-E-00 7 2001/01 ASAHI KASEI [AK2048] Tpwh Tpwl 50% Fig.3 Transmit output pulse duty TCLK TCRV TDATA TXA-TXB Ttd A B A C B D C The shaded portion is CRV bit Fig.4 Data input to signal output delay time MS0073-E-00 8 2001/01 ASAHI KASEI [AK2048] RECEIVER Parameter REF25 output Signal loss threshold level Signal loss detection time Sensitivity Input jitter tolerance PSRR (Line Length 400m) S/X tolerance Line Length 400m 0m Signal input to Data output delay time RCLK Output Jitter 3 nsp-p *1) Reference output of fixed equalizer. *2) The amplitude of input data is 3.00.75Vp-p and the data pattern is 215-1. *3) Data output delay = (1.25bit logical delay) + (internal propagation delay) *4) Data pattern is "all space" with CRV every 8kHz cycle. RxA 135mVp-p RxB 50% TALM REF25 Symbol VREF Vth TALM min 2.0 85 typ 2.5 135 10 max 3.0 185 12 4.0 0.15 400 Unit V mVp-p usec Vp-p UIp-p mVp-p dB dB Comments Iout Jitter frequency 20KHz~100KHz *2) *2) frequency 1.9MHz Fig.6 *3) *4) 2 12 Trd 1.25 bit LOS Fig.5 LOS output signal RXA RXB RCLK RCRV RDATA A B C D E A Trd The shaded portion is CRV bit B C D Fig.6 Delay time from RXA,RXB to RDATA MS0073-E-00 9 2001/01 ASAHI KASEI [AK2048] AC CHARACTERISTICS Parameter Input Clock Frequency Duty Cycle Delay time from TCLK rising to TDATA, TCRV. Output Clock Frequency Output Clock Duty Delay time from RCLK rising to RDATA, RCRV. Pin Name TCLK TCLK TDATA TCRV Symbol fin 46 min typ 2.048 50 54 max Unit MHz % *1) Refer to Fig.7 Conditions Conditions Tpd -58 58 ns Refer to Fig.8 The bit rate of received signal is 2.048Mbps *1) Refer to Fig.7 Refer to Fig.8 RCLK RCLK RDATA RCRV LOS LOCK fout 43 Tpd -48 2.048 50 57 48 MHz % ns 15 Tr, Tf 30 ns Refer to Fig.9 Rise/Fall Time RDATA RCLK RCRV LOS 15 ns Delay time from RCLK rising to LOS Tpd -48 48 ns Refer to Fig.8 *1) Duty: Tpwh/(Tpwh+Tpwl) x 100% MS0073-E-00 10 2001/01 ASAHI KASEI [AK2048] Tpwh Tpwl 50% 50% 50% Fig.7 Clock timing TCLK, RCLK TDATA, RDATA TCRV, RCRV LOS 50% 50% 50% 50% Tpd Fig.8 Transmitter Timing VDD 4k OUTPUT PIN Measurement point 15p VSS Tr 90% 10% 90% 10% Tf Fig.9 Rise and fall times and a condition of measurement. MS0073-E-00 11 2001/01 ASAHI KASEI [AK2048] FUNCTIONAL DESCRIPTION PLL calibration function The calibration of PLL is caused in case of the following 3cases. (1) Power on (2) RST rising (3) LOCK rising (1) Power on After the power is on, the calibration is complete and LOCK goes to "Low" in less than 63ms from whichever the later happens, the input of signal (RXA-RXB) or the rising edge of RST. (2) RST rising The calibration is complete and LOCK goes to "Low" in less than 38ms from whichever the later happens, the input of signal (RXA-RXB) or the rising edge of RST. (3) LOCK rising When the device falls into unlock by some reasons and LOCK goes to "high", calibration restarts. The calibration is complete and LOCK goes to "Low" in less than 38ms from the rising edge of LOCK. PLL pull in time after loss of signal When LOS goes to "high" by loss of signal after the calibration, the pull in of the PLL restarts by signal input. If the device can pull in without calibration, pull-in completes less than 200us. In other case, LOCK goes to "high" and calibration restarts less than 2ms. LOS signal LOS goes to "high", when the amplitude of RXB is less than 135mVpp(typ) during 16 bits (about 8us). LOS signal goes to "Low", when amplitude of RXB is more than 135mVpp(typ). When the signal is lost during the calibration, LOS signal goes to "high" and the calibration circuit is reset. The calibration restarts after LOS signal goes to "Low". MS0073-E-00 12 2001/01 ASAHI KASEI [AK2048] CRV (Code Rule Violation) CMI code with violation is called as MD (Modified Dipulse) code. MD is refer to Fig.10. Generally speaking, CRV (Code Rule Violation) is generated at code "1". But AK2048D generates the violation for not only code "1", but also code "0". Violation of code "0" is refer to Fig.11. CLOCK NRZ MD violation MARK(1) SPACE(0) Fig.10 MD code CODE "0" Violation of CODE "0" Fig.11 Violation of CODE "0" MS0073-E-00 13 2001/01 ASAHI KASEI [AK2048] RECOMMENDED EXTERNAL CIRCUITS VDD R0 RXA(33) CMI input 1:1CT VDD EQL. C0 VSS VDD R1 REF25(31) RXB(29) AK2048D RVDD(40) TVDD(25) TXA(23) RVSS(42) VDD TVSS(24) TXA(26) CMI output 1:1CT R0 = 110 R1 = R2 = 56 C0 = 1 uF VDD R2 VDD Fig.12 The example of the external circuits It is recommended that Shott key diode in Fig 12 is connected for protection of latch-up. MS0073-E-00 14 2001/01 ASAHI KASEI [AK2048] PACKAGE 18.20.4 14TYP 0.5MAX 33 23 34 22 18.20.4 14TYP XXXXYZZ AK2048D JAPAN 44 0-15 12 1 0.40.1 10.16 11 2.9MAX 0.96TYP 0.150.05 15 10.4 MS0073-E-00 15 2001/01 ASAHI KASEI [AK2048] IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. As used MS0073-E-00 16 2001/01 |
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