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HIGH-SPEED 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
.eatures
x x
PRELIMINARY IDT709369L
x
x
x x
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access - Commercial: 7.5/9/12ns (max.) - Industrial: 9ns (max.) Low-power operation - IDT709369L Active: 1.2W (typ.) Standby: 2.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic
x
x
x x
x
Full synchronous operation on both ports - 4ns setup to clock and 0ns hold on all control, data, and address inputs - Data input, address, and control registers - Fast 7.5ns clock to data out in the Pipelined output mode - Self-timed write allows fast cycle time - 12ns cycle time, 83MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility TTL- compatible, single 5V (10%) power supply Industrial temperature range (-40C to +85C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) package
.unctional Block Diagram
R/WL
UBL CE0L
R/WR
UBR CE0R
CE1L
LBL OEL
1 0 0/1
1 0 0/1
CE1R
LBR OER
FT/PIPEL
0/1
1b 0b
ba
1a 0a
0a 1a
a
b
0b 1b
0/1
FT/PIPER
I/O9L-I/O17L I/O0L-I/O8L
I/O Control
I/O9R-I/O17R I/O Control I/O0R-I/O8R
A13L A0L CLKL
ADSL CNTENL CNTRSTL
A13R Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR
ADSR CNTENR CNTRSTR
5647 drw 01
MAY 2002
1
(c)2002 Integrated Device Technology, Inc. DSC-5647/1
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Description
The IDT709369 is a high-speed 16K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT709369 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 1.2W of power.
Pin Configurations(1,2,3)
INDEX
A9L A10L A11L A12L A13L NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL Vcc FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND GND ADSR CLKR
CNTENR A0R A1R A2R A3R A4R A5R A6R A7R
A8R A9R A10R A11R A12R A13R NC NC LBR UBR CE0R CE1R CNTRSTR R/WR GND OER . FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
5647 drw 02
05/13/02
709369PF PN100-1(4) 100-Pin TQFP Top View(5)
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O9L I/O8L Vcc I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R I/O10R
2 6.42
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Names
Left Port CE0L, CE1L R/WL OEL A0L - A13L I/O0L - I/O17L CLKL UBL LBL ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER A0R - A13R I/O0R - I/O17R CLKR UBR LBR ADSR CNTENR CNTRSTR FT/PIPER VCC GND Names Chip Enables (2) Read/Write Enable Output Enable Address Data Input/Output Clock Upper Byte Select
(1)
Lower Byte Select(1) Address Strobe Counter Enable Counter Reset Flow-Through/Pipeline Power Ground
5647 tbl 01
NOTES: 1. LB and UB are single buffered regardless of state of FT/PIPE. 2. CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
Truth Table IRead/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK X CE0 H X L L L L L L L L CE1 X L H H H H H H H H UB X X H L H L L H L L LB X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O9-17 High-Z High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z Lower Byte I/O0-8 High-Z High-Z High-Z High-Z DATAIN DATAIN High-Z DATAOUT DATAOUT High-Z Mode Deselected--Power Down Deselected--Power Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
5647 tbl 02
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal.
6.42 3
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2,6)
Address An X X X Previous Address X An An + 1 X Addr Used An An + 1 An + 1 A0 CLK (6) ADS L
(4)
CNTEN X L
(5)
CNTRST H H H L
(4)
I/O (3) DI/O (n) DI/O(n+ 1) DI/O(n+ 1) DI/O(0) E xte rnal A d d re s s Use d
MODE
H H X
Co unte r E nab le d -- Inte rnal A d d re s s g e ne ratio n E xte rnal A d d re s s B lo ck e d -- Co unte r d is ab le d (A n + 1 re use d ) Co unte r Re se t to A d d re ss 0
5647 tbl 03
H X
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
Recommended Operating Recommended DC Operating Temperature and Supply Voltage(1) Conditions
Grade Commercial Industrial Ambient Temperature(2) 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10%
5647 tbl 04
Symbol VCC GND VIH VIL
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage
Min. 4.5 0 2.2 -0.5(2)
Typ. 5.0 0
____
Max. 5.5 0 6.0(1) 0.8
Unit V V V V
5647 tbl 05
NOTES: 1. Industrial temperature: for specific speeds, packages and powers contact your sales office. 2. This is the parameter TA. This is the "instant on" case temperature.
____
NOTES: 1. VTERM must not exceed Vcc + 10%. 2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Symbol VTERM
(2)
Capacitance(1)
Unit V Symbol CIN COUT
(3)
Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current
Commercial & Industrial -0.5 to +7.0
(TA = +25C, f = 1.0MHz)
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
5647 tbl 07
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
o
C C
o
mA
5647 tbl 06
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
4 6.42
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.0V 10%)
709369L Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to VCC CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC IOL = +4mA IOH = -4mA Min.
___
Max. 5 5 0.4
___
Unit A A V V
5647 tbl 08
___
___
2.4
NOTE: 1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VCC = 5V 10%)
709369L7 Com 'l Only Sym bol ICC Param eter Dynam ic Op e rating Curre nt (Bo th Po rts A ctiv e ) S tand b y Curre nt (Bo th Po rts - TTL Le ve l Inp uts) S tand b y Curre nt (One P o rt - TTL Le ve l Inp uts) Full Stand b y Curre nt (Bo th Po rts CM OS Le ve l Inp uts ) Full Stand b y Curre nt (One P o rt CM OS Le ve l Inp uts ) Test Condition CEL and CER= V IL Outp uts Dis ab le d f = fMAX (1) CEL = CER = VIH f = fMAX (1) CE"A " = VIL and CE"B " = V IH (3) A ctive Po rt Outp uts Disab le d , f=fMAX (1) B o th Po rts CER and CEL > VCC - 0.2V VIN > V CC - 0.2V o r VIN < 0.2V , f = 0 (2) CE"A " < 0.2V and CE"B " > VCC - 0.2V (5) VIN > V CC - 0.2V o r VIN < 0.2V, A ctiv e P o rt Outp uts Dis ab le d , f = fMAX (1) Version COM 'L IND COM 'L IND COM 'L IND COM 'L IND COM 'L IND L L L L L L L L L L Typ. (4) 275
____
709369L9 Com 'l & Ind Typ. (4) 250 300 80 95 175 195 0.5 0.5 170 190 Max. 400 430 135 160 275 295 3.0 6.0 270 290
709369L12 Com 'l Only Typ. (4) 230
____
Max. 465
____
Max. 355
____
Unit mA
IS B1
95
____
150
____
70
____
110
____
mA
IS B2
200
____
295
____
150
____
240
____
mA
IS B3
0.5
____
3
____
0.5
____
3
____
mA
IS B4
190
____
290
____
140
____
225
____
mA
5647 tb l 0 9
NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port.
6.42 5
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3
5647 tbl 10
5V 893 DATAOUT 347 30pF DATAOUT 347
5V 893
5pF*
5647 drw 04
5647 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig.
8 7 6 5 tCD1, tCD2 (Typical, ns) 4 3 2 1 0 -1
- 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance
20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
5647 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6 6.42
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VCC = 5V 10%, TA = 0C to +70C)
709369L7 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSB tHB tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clo ck Cycle Tim e (Flo w-Thro ug h)(2) Clo ck Cycle Tim e (P ip e line d )
(2)
709369L9 Com'l & Ind Min. 25 15 12 12 6 6
____ ____
709369L12 Com'l Only Min. 30 20 12 12 8 8
____ ____
Parameter
Min. 22 12 7.5 7.5 5 5
____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Clo ck Hig h Tim e (Flo w-Thro ug h)(2) Clo ck Lo w Tim e (Flo w-Thro ug h) Clo ck Hig h Tim e (P ip e lined )
(2) (2)
Clo ck Lo w Tim e (P ip e lined )(2) Clo ck Rise Tim e Clo ck Fall Tim e A d d re ss S e tup Tim e A d d re ss Ho ld Tim e Chip E nab le S e tup Tim e Chip E nab le Ho ld Tim e B yte E nab le S e tup Tim e B yte E nab le Ho ld Tim e R/W S e tup Tim e R/W Ho ld Time Inp ut Data S e tup Tim e Inp ut Data Ho ld Tim e ADS S e tup Tim e ADS Ho ld Time CNTEN S e tup Tim e CNTEN Ho ld Time CNTRST S e tup Tim e CNTRST Ho ld Time Outp ut E nab le to Data Valid Outp ut E nab le to Outp ut Lo w-Z
(1)
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
9
____
12
____
12
____
2 1
____ ____
2 1
____ ____
2 1
____ ____
Outp ut E nab le to Outp ut Hig h-Z(1) Clo ck to Data Valid (Flo w-Thro ug h)(2) Clo ck to Data Valid (P ip e line d )(2) Data Outp ut Ho ld A fte r Clock Hig h Clo ck Hig h to Outp ut Hig h-Z
(1)
7 18 7.5
____
7 20 9
____
7 25 12
____
2 2 2
2 2 2
2 2 2
9
____
9
____
9
____
Clo ck Hig h to Outp ut Lo w-Z(1)
Port-to-Port Delay tCWDD tCCS W rite Po rt Clo ck Hig h to Re ad Data De lay Clo ck-to-Clo ck S e tup Time
____ ____
28 10
____ ____
35 15
____ ____
40 15
ns ns
5647 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
6.42 7
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for .low-Through Output (FT/PIPE"X" = VIL)(3,7)
tCYC1 tCH1 CLK CE0 tSC CE1 tSB UB, LB R/W tHB tSB tHB tHC tSC tHC tCL1
tSW tSA
tHW tHA An + 1 tCD1 tDC Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 2
An + 3 tCKHZ
(1)
DATAOUT
Qn + 1 tOHZ
(1)
Qn + 2 tOLZ
(1)
tDC
OE
(2)
tOE
5647 drw 07
Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,7)
tCYC2 tCH2 CLK CE0 tSC CE1 UB, LB tSB tHB tSB
(6)
tCL2
tHC
tSC
(4)
tHC
tHB
R/W
tSW tSA
tHW tHA An + 1 (1 Latency) An + 2 tDC Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 3
tCD2
DATAOUT
Qn + 1 tOHZ
(1)
Qn + 2 tOLZ
(1)
(6)
OE
(2)
tOE
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "X" here denotes Left or Right port. The diagram is with respect to that port.
5647 drw 08
8 6.42
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2 CLK tSA ADDRESS(B1) tSC tHA A0 tHC tSC tCD2 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 Q0 tDC tHC tCD2 tCKHZ Q1 tDC
(3)
tCYC2 tCL2
A1
A2
A3
A4
A5
A6
CE0(B1)
tCD2 Q3 tCKLZ
(3)
tCKHZ (3)
tSC CE0(B2) tSC tHC
tHC
tCD2 DATAOUT(B2) tCKLZ
(3)
tCKHZ (3) Q2
tCD2 tCKLZ
(3) 5647 drw 09
Q4
Timing Waveform of Write with Port-to-Port .low-Through Read(4,5,7)
CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" tHA
NO MATCH
MATCH
tSD DATAIN "A"
tHD
VALID
tCCS CLK "B"
(6)
tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA
NO MATCH
MATCH
tCWDD DATAOUT "B" tDC
(6)
tCD1
VALID VALID
tDC
5647 drw 10
NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709369 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.42 9
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2 tCH2 tCL2 CLK
CE0 tSC tHC CE1 tSB UB, LB tSW tHW R/W tSW tHW tHB
ADDRESS
(4)
An tSA tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
DATAIN
(2)
tCD2 Qn READ
tCKHZ
(1)
tCKLZ
(1)
tCD2 Qn + 3
DATAOUT
NOP
(5)
WRITE
READ
5647 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2 tCH2 CLK CE0 tSC CE1 tSB UB, LB tSW tHW R/W tSW tHW tHB tHC tCL2
ADDRESS
(4)
An tSA tHA
An +1
An + 2 tSD tHD
An + 3
An + 4
An + 5
DATAIN
(2)
tCD2 Qn tOHZ(1)
Dn + 2
Dn + 3
tCKLZ(1)
tCD2 Qn + 4
DATAOUT
OE READ WRITE READ
5647 drw 12
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
10 6.42
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of .low-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1 CLK tCYC1 tCL1
CE0 tSC CE1 tSB UB, LB tSW tHW R/W tSW tHW tHB tHC
ADDRESS
(4)
tSA DATAIN
(2)
An tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
tCD1 Qn tDC READ
tCD1 Qn + 1 tCKHZ (5) NOP
(1)
tCD1 Qn + 3 tCKLZ WRITE
(1)
tCD1
DATAOUT
tDC READ
5647 drw 13
Timing Waveform of .low-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1 tCH1 tCL1 CLK CE0 tSC CE1 tSB UB, LB tSW tHW R/W ADDRESS
(4)
tHC
tHB
tSW tHW An tHA An +1 An + 2 tSD tHD Dn + 2
(2)
An + 3
An + 4
An + 5
tSA DATAIN
Dn + 3
tCD1 Qn
tDC
tOE tCD1
(1)
tCD1 Qn + 4 tDC
DATAOUT
tOHZ OE READ
(1)
tCKLZ
WRITE
READ
5647 drw 14
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
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IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2
An tSAD tHAD
ADS
tSAD tHAD
CNTEN tCD2 DATAOUT Qx - 1(2) Qx tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn
tSCN tHCN
Qn + 1
Qn + 2(2)
Qn + 3
COUNTER HOLD
READ WITH COUNTER
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Timing Waveform of .low-Through Read with Address Counter Advance(1)
tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1
An tSAD tHAD
ADS
tSAD tHAD tSCN tHCN
CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER
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Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks.
12 6.42
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance (.low-Through or Pipelined Outputs)(1)
tCH2 CLK tSA ADDRESS tHA An tCYC2 tCL2
INTERNAL(3) ADDRESS tSAD tHAD ADS
An(7)
An + 1
An + 2
An + 3
An + 4
CNTEN tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
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Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2 CLK tSA tHA ADDRESS(4) INTERNAL(3) ADDRESS Ax(6) tSW tHW R/W ADS CNTEN tSRST tHRST CNTRST DATAIN DATAOUT(5) COUNTER(6) RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 tSD tHD D0 Q0 READ ADDRESS n Q1 READ ADDRESS n+1
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tCYC2 tCL2
An
An + 1
An + 2
0
1
An
An + 1
Qn
.
NOTES: 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. 7. CNTEN = VIL advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1' Address is written to during this cycle.
6.42 13
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
A .unctional Description
The IDT709369 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. CE0 = VIH or CE1 = VIL for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT709369's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
Depth and Width Expansion
The IDT709369 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT709369 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36-bit or wider applications.
A14
IDT709369
CE0 CE1 VCC
IDT709369
CE0 CE1 VCC
Control Inputs
Control Inputs
IDT709369
CE1 CE0
IDT709369
CE1 CE0 CNTRST CLK ADS CNTEN R/W LB, UB OE
Control Inputs
Control Inputs
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Figure 4. Depth and Width Expansion with IDT709369
14 6.42
IDT709369L High-Speed 16K x 18 Synchronous Pipelined Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range
Blank I(1)
Commercial (0C to +70C) Industrial (-40C to +85C)
PF
100-pin TQFP (PN100-1)
7 9 12 L
Commercial Only Commercial & Industrial Commercial Only Low Power
Speed in nanoseconds
709369 288K (16K x 18-Bit) Synchronous Dual-Port RAM
NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
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Preliminary Datasheet: Definition
"PRELIMINARY" datasheets contain descriptions for products that are in early release.
Datasheet Document History
5/13/02: Initial Public Release
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-611 6 fax: 408-492-8674 www.idt.com
6.42 15
for Tech Support: 831-754-4613 DualPortHelp@idt.com
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