View IS61C256AH_236802.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS61C256AH
32K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
* High-speed access time: 10, 12, 15, 20, 25 ns * Low active power: 400 mW (typical) * Low standby power -- 250 W (typical) CMOS standby -- 55 mW (typical) TTL standby * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 5V power supply
ISSI
(R)
MAY 1999
DESCRIPTION The ISSI IS61C256AH is a very high-speed, low power,
32,768 word by 8-bit static RAMs. They are fabricated using
ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 W (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C256AH is pin compatible with other 32K x 8 SRAMs and are available in 28-pin PDIP, SOJ, and TSOP (Type I) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K X 8 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99
1
IS61C256AH
PIN CONFIGURATION
28-Pin DIP and SOJ
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
ISSI
PIN CONFIGURATION
28-Pin TSOP
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
(R)
A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
PIN DESCRIPTIONS
A0-A14 Address Inputs Chip Enable Input Output Enable Input Write Enable Input Bidirectional Ports Power Ground
TRUTH TABLE
Mode
CE OE WE
I/O0-I/O7 Vcc GND
WE
CE OE
H L L L X H L X
I/O Operation Vcc Current High-Z High-Z DOUT DIN ISB1, ISB2 ICC ICC ICC
Not Selected X (Power-down) Output Disabled H Read H Write L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to +7.0 -55 to +125 -65 to +150 1.5 20 Unit V C C W mA
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99
IS61C256AH
OPERATING RANGE
Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Speed -10, -12 -15, -20, -25 -12 -15, -20, -25 VCC 5V 5% 5V 10% 5V 5% 5V 10%
ISSI
(R)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2.2 -0.5 -5 -10 -5 -10 Max. -- 0.4 VCC + 0.5 0.8 5 10 5 10 Unit V V V V A A
Note: 1. VIL = -3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol ICC ISB1 Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE VIH, f = 0 VCC = Max., CE VCC - 0.2V, VIN VCC - 0.2V, or VIN 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -10 -12 -15 -20 -25 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit -- -- -- -- -- -- 165 -- 25 -- 2 -- -- -- -- -- -- -- 155 165 25 30 2 10 -- -- -- -- -- -- 145 155 25 30 2 10 -- -- -- -- -- -- 135 145 25 30 2 10 -- -- -- -- -- -- 125 135 25 30 2 10 mA mA
ISB2
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99
3
IS61C256AH
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time -10 Min. Max 10 -- 2 -- -- 0 -- 2 -- 0 -- -- 10 -- 10 5 -- 5 -- 5 -- 10 -12 Min. Max. 12 -- 2 -- -- 0 -- 3 -- 0 -- -- 12 -- 12 5 -- 6 -- 7 -- 12 -15 Min. Max. 15 -- 2 -- -- 0 -- 3 -- 0 -- -- 15 -- 15 7 -- 7 -- 8 -- 15 -20 Min. Max. 20 -- 2 -- -- 0 -- 3 -- 0 -- -- 20 -- 20 8 -- 9 -- 9 -- 18 -25 Min. Max. 25 -- 2 -- -- 0 -- 3 -- 0 -- -- 25 -- 25 9 -- 10 -- 10 -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns
ISSI
(R)
tRC tAA tOHA tACE tDOE tLZOE tLZCE tPU tPD
(3) (3) (2) (2)
tHZOE
(2)
tHZCE(2)
CE Access Time OE Access Time OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
AC TEST LOADS
480 5V
5V 480
OUTPUT 30 pF Including jig and scope 255
OUTPUT 5 pF Including jig and scope 255
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99
IS61C256AH
AC WAVEFORMS READ CYCLE NO. 1(1,2)
t RC
ADDRESS
ISSI
(R)
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
OE
t OHA
t DOE
CE
t HZOE
t LZOE t ACE t LZCE t HZCE
DATA VALID
CE_RD2.eps
DOUT
HIGH-Z
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99
5
IS61C256AH
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter -10 Min. Max 10 9 9 0 0 8 6.5 7 0 -- 0 -- -- -- -- -- -- -- -- -- 6 -- -12 Min. Max. 12 10 10 0 0 8 7 7 0 -- 0 -- -- -- -- -- -- -- -- -- 6 -- -15 Min. Max. 15 10 12 0 0 10 8 9 0 -- 0 -- -- -- -- -- -- -- -- -- 7 -- -20 Min. Max. 20 13 15 0 0 13 10 10 0 -- 0 -- -- -- -- -- -- -- -- -- 8 -- -25 Min. Max. 25 15 20 0 0 15 12 12 0 -- 0 -- -- -- -- -- -- -- -- -- 10 -- Unit ns ns ns ns ns ns ns ns ns ns ns
ISSI
(R)
tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE
(2)
Write Cycle Time
CE to Write End
Address Setup Time to Write End Address Hold from Write End Address Setup Time
WE Pulse Width (OE LOW) WE Pulse Width (OE HIGH)
Data Setup to Write End Data Hold from Write End
tLZWE(2)
WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) WE
t WC
ADDRESS
VALID ADDRESS
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t HZWE t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99
IS61C256AH
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
ISSI
t HA
(R)
OE
CE
LOW
t AW t PWE1
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
CE_WR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE CE
LOW
t HA
LOW
t AW t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE VIH.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99
7
IS61C256AH
ORDERING INFORMATION: IS61C256AH Commercial Range: 0C to +70C
Speed (ns) 10 Order Part Number IS61C256AH-10N IS61C256AH-10J IS61C256AH-10T IS61C256AH-12N IS61C256AH-12J IS61C256AH-12T IS61C256AH-15N IS61C256AH-15J IS61C256AH-15T IS61C256AH-20N IS61C256AH-20J IS61C256AH-20T IS61C256AH-25N IS61C256AH-25J IS61C256AH-25T Package 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1)
ISSI
ORDERING INFORMATION: IS61C256AH Industrial Range: -40C to +85C
Speed (ns) 12 Order Part Number IS61C256AH-12NI IS61C256AH-12JI IS61C256AH-12TI IS61C256AH-15NI IS61C256AH-15JI IS61C256AH-15TI IS61C256AH-20NI IS61C256AH-20JI IS61C256AH-20TI IS61C256AH-25NI IS61C256AH-25JI IS61C256AH-25TI Package 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic DIP 300-mil Plastic SOJ TSOP (Type 1)
(R)
12
15
15
20
20
25
25
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR020-1O 05/24/99

▲Up To Search▲

Price & Availability of IS61C256AH

	To Download IS61C256AH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .