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Ordering number : EN6002
LB1875
Monolithic Digital IC
LB1875
Polygon Mirror Motor Predriver IC
Overview
The LB1875 is a predriver IC for polygon mirror motors. By using a driver array or discrete transistors (FETs) at the output, motor drive with high rotation precision is possible. PAM drive or direct PWM drive can be selected for the output to realize high-efficiency control with minimum power loss.
Package Dimensions
unit: mm 3235-HSOP36
[LB1875]
17.9
0.65 (4.9)
6.2 2.7 36
1 0.55
2.25
0.25 0.8 0.3
1.3
Features
* * * * * * * * * * * * * * * Three-phase bipolar drive Direct PWM drive (bottom side) or PAM drive selectable PLL speed control circuit PWM oscillator Quartz oscillator Frequency divider FG with Schmitt comparator FG input single edge, dual edge selector circuit Integrating amplifier Phase lock detector output Current limiter Motor lock protection Thermal protection Forward/reverse circuit 5V regulator output
2.5max
0.1
SANYO : HSOP36
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D0898RM(KI) No. 6002-1/17
10.5
7.9
LB1875 Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Output current Allowable power dissipation Symbol VCC max IO max Pd max IC only with substrate (114.3 x 76.1 x 1.6 mm , glass exposy) Operating temperature Storage temperature Topr Tstg
3
Conditions
Ratings 14.5 30 0.9 2.1 - 20 to +80 - 55 to +150
Unit V mA W W C C
Operation Conditions at Ta = 25C
Parameter Maximum supply voltage Symbol VCC1 VCC2 Output current 5V regulated output current Voltage applied at LD pin LD pin output current Voltage applied at PWM pin PWM pin output current IO IREG V LD IL D VPWM IPWM When shorted between VCC and VREG Conditions Ratings 8 to 13.5 4.5 to 5.5 20 0 to -20 0 to 13.5 0 to 10 0 to 13.5 0 to 20 Unit V V mA mA V mA V mA
2.4
Pd max - Ta
With substrate (114.3 x 76.1 x 1.6 mm, glass exposy)
Power dissipation, Pd max - W
2.1 2.0
1.6
1.2
IC only
0.9 0.8
1.18
0.5 0.4
0 -20
0
20
40
60
80
100
120
Ambient temperature, Ta - C
No. 6002-2/17
LB1875
Electrical Characteristics at Ta = 25C, VCC = 12V
Parameter Power supply current [5V regulated output ] Output fluctuation Voltage fluctuation Load fluctuation Temperature coefficcient [Output Section] Output saturation voltage VO(sat)1-1 UH, VH, WH "L" level, IO=50 A Vo(sat)1-2 UH, VH, WH "L" level, IO=10 mA VO(sat)2 VO(sat)3 Output leak current [Hall amplifier] Input bias current Same-phase input voltage range Hall input sensitivity Hysteresis width Input voltage L->H Input voltage H->L [FG/Schmitt comparator section] Input bias current Same-phase input voltage range Input sensitivity Hysteresis width Input voltage L->H Input voltage H->L [PWM oscillator] Output High level voltage Output Low level voltage Oscillator frequency Amplitude [PWM output] Output saturation voltage Output leak current [CSD oscillator ] Output High level voltage Output Low level voltage External C charge current External C discharge current Oscillator frequency Amplitude [Phase comparator output] Output High level voltage Output Low level voltage Output source current Output sink current [Phase lock detector output] Output saturation voltage Output leak current VOL(LD) IL(LD) ILD=10 mA VO=VCC 0.1 0.4 10 V A VPDH VPDL IPD+ IPD- IOH=-100 A IOH=100 A VPD=VREG/2 VPD=VREG/2 1.5 VREG-0.2 VREG-0.1 0.1 0.2 -0.6 V V mA mA VOH(CSD) VOL(CSD) ICHG 1 ICHG 2 fCSD VCSD C=0.068 F 1.75 2.5 0.55 -13 7 2.8 0.85 -10 10 35 1.95 2.15 3.1 1.15 -7 13 V V A A Hz VP-P VOL(PWM) IPWM=15 mA IL(PWM) VO=VCC 0.9 2.0 10 V A VOH(OSC) VOL(OSC) f(OSC) V(OSC) C=2200 pF 1.0 2.7 1.5 3.0 1.8 30 1.2 1.4 3.3 2.1 V V kHz VP-P IB(FGS) VICM(FGS) VIN(FGS) VIN(FGS) Design target value VSLH(FGS) Design target value VSHL(FGS) Design target value -4 0 30 8 14 7 -7 24 -1 VCC-2.0 A V mVP-P mV mV mV VIN(HA) VSLH VSHL IHB(HA) VICM -4 0 30 8 14 7 -7 24 -1 VCC-2.0 A V mVP-P mV mV mV IOleak UH, VH, WH "L" level, IO=20 mA UL, VL, WL, IO=20 mA UL, VL, WL 0.1 0.9 VCC-0.9 0.2 0.3 1.1 VCC-1.1 0.4 10 V V V V A VREG VREG1 VREG2 VREG3 VCC=8 to 13.5V IO=0 to -15 mA Design target value 4.65 5.0 40 20 0 5.35 100 100 V mV mV mV/C Symbol IC C Conditions min Ratings typ 30 max 40 mA Unit
Continued on next page
No. 6002-3/17
LB1875
Continued from preceding page
Parameter [ERR amplifier] Input offset voltage Input bias current Ouput High level voltage Ouput Low level voltage DC bias level [Current limiter] Limiter voltage [Low-voltage protection circuit] Operation voltage Release voltage Hysteresis width [Thermal shutdown operation] Termal shutdown temperature Hysteresis width [SOFT pin] Stop voltage External C discharge current [Quartz oscillator] Quartz oscillator frequency Low level pin voltage High level pin voltage [CLKOUT pin] Output saturation voltage Output leak current [CLKIN pin] External input frequency High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current [S/S pin] High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current [F/R pin] High level input voltage Low level input voltage Input open voltage High level input current Low level input current [FGSEL pin] High level input voltage Low level input voltage Input open voltage High level input current Low level input current VIH(FSEL) VIL(FSEL) VIO(FSEL) IIH(FSEL) VFSEL=VREG IIL(FSEL) VFSEL=0V 3.5 0 VREG-0.5 -10 -200 0 -140 VREG 1.5 VREG +10 V V V A A VIH(FR) VIL(FR) VIO(FR) IIH(FR) IIL(FR) VF/R=VREG VF/R=0V 3.5 0 VREG-0.5 -10 -200 0 -140 VREG 1.5 VREG +10 V V V A A VIH(SS) VIL(SS) VIO(SS) VIS(SS) IIH(SS) IIL(SS) VS/S=VREG VS/S=0V 3.5 0 VREG-0.5 0.3 -10 -200 0.4 0 -140 VREG 1.5 VREG 0.5 +10 V V V V A A fI(CKIN) VIH(CKIN) VIL(CKIN) VIO(CKIN) VIS(CKIN) IIH(CKIN) IIL(CKIN) VCKIN=VREG VCKIN=0V 0.1 3.5 0 VREG-0.5 0.3 -10 -200 0.4 0 -140 10 VREG 1.5 VREG 0.5 +10 kHz V V V V A A
VOL(CKOUT) ICKOUT=2 mA
Symbol
Conditions min
Ratings typ max
Unit
VIO(ER) IB(ER) VOH(ER) VOL(ER) VB(ER)
Design target value
-10 -1
+10 +1 VREG-0.9 0.9 1.2 + 5%
mV A V V V
IOH = -500 A IOL=500 A
VREG-1.2
-5%
VREG/2
VRF
0.45
0.5
0.55
V
VSDL VSDH VSD
3.55 3.8 0.15
3.75 4.0 0.25
3.95 4.2 0.35
V V C C C
TSD TSD
Design target value (junction temperature) Design target value (junction temperature)
150
180 30
VSFT ID C H G
In stop condition
3.0 4
3.3 6
3.6 8
V A
fOSC VOSCL VOSCH IOSC=-0.5 mA VOSC=VOSCL+0.6V
2 1.45 0.5
10
MHz V mA
0.1
0.4 10
V A
IL(CKOUT) VO=VCC
Continued on next page
No. 6002-4/17
LB1875
Continued from previous page
Parameter [CLKSEL pin] High level input voltage Middle level input voltage Low level input voltage Input open voltage High level input current Low level input current [LIM pin] High level input voltage Low level input voltage Input open voltage High level input current Low level input current VIH(LIM) VIL(LIM) VIO(LIM) IIH(LIM) IIL(LIM) VLIM=VREG VLIM=0V 3.5 0 VREG-0.5 -10 -200 0 -140 VREG 1.5 VREG +10 V V V A A VIH(CSEL) VIM(CSEL) VIL(CSEL) VIO(CSEL) IIH(CSEL) VCSEL=VREG IIL(CSEL) VCSEL=0V 4.0 2.0 0 VREG-0.5 -10 -200 0 -140 VREG 3.0 1.0 VREG +10 V V V V A A Symbol Conditions min Ratings typ max Unit
3-phase logic truth table (IN = "H" indicates the IN+ > IN- condition)
F/R= "L" IN1 1 2 3 4 5 6 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R= "H" IN2 H H L L L H IN3 L H H H L L Output SOURCE VH WH WH UH UH VH SYNC UL UL VL VL WL WL
S/S pin
Input state High or open L Condition Stop Start
FGSEL pin
Input state High or open L Edge detection FG dual edge FG single edge
CLKSEL pin
Input state High or open M L Divisor 1024 x 4 1024 1024 x 3
LIM pin
Input state High or open L Output pin (UH, VH, WH) No PWM (PAM operation) PWM (direct PWN operation) PWMOUT pin PWM output FG/Schmitt comparator output
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
LB1875
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FGSEL
CLKSEL
SOFT
CLKOUT
No. 6002-5/17
CPWM
A11348
XO
F/R
CLKIN
VREG
LD1
GND
LD2
S/S
EO
PD
XI
EI
TOC
LIM
PWMOUT
Pin Assignment
FGIN+ FGIN- GND IN1+ IN2+ IN3+ IN1- IN2- IN3- CSD VCC WH WL UH VH RF UL VL
LB1875 Block Diagram and Sample Application Circuit (Sample application: PAM drive, FET output)
VREG
LD2 FGIN- FGIN+
LD1 PD EI
- + - + FG FILTER LD VREG - + FG SELECT TOC 12V
+
EO
FGSEL
CLKIN
CLK
PLL LVSD CLK SELECT COMP PWM VCC
+
CLKOUT CLKSEL XI OSC XO VREG ECL 1/8 1/128 1/384 1/512
TSD
PWM OUT
24V
+
CPWM
PWM OSC
VREG
VREG
S/S
S/S PRI DRIVER
UL UH VL VH HALL LOGIC WL WH
F/R
F/R
LOGIC
CSD
SD OSC
HALL HYS AMP
CURR LIM
RF
IN1+ VCC
IN1-
IN2+
IN2-
IN3+
IN3- SOFT
LIM
GND
A11596
Note: For applications where the motor has variable speed and control at low motor voltages is required, the base voltage of the output interface transistor must be made low. In this case, a P-channel FET which can be used at low gate voltages must be selected.
No. 6002-6/17
LB1875 (Sample application: direct PWM drive, FET output)
VREG
LD2 FGIN- FGIN+
LD1 PD EI
- + - + FG FILTER LD VREG - + FG SELECT TOC VREG EO
FGSEL
CLKIN
CLK
PLL LVSD CLK SELECT COMP PWM VCC TSD PWMOUT
FGS 12V
+
CLKOUT CLKSEL XI OSC XO VREG CPWM PWM OSC ECL 1/8 1/128 1/384 1/512
24V
+
VREG
VREG
S/S
S/S PRI DRIVER
UL UH VL VH HALL LOGIC WL WH
F/R
F/R
LOGIC
CSD
SD OSC
HALL HYS AMP
CURR LIM
RF
IN1+ VCC
IN1-
IN2+
IN2-
IN3+
IN3-
SOFT
LIM
GND
A11597
No. 6002-7/17
LB1875 (Sample application: PAM drive, bipolar transistor output)
VREG
LD2 FGIN- FGIN+
LD1 PD EI
- + - + FG FILTER LD VREG - + FG SELECT TOC 5V
+
EO
FGSEL
CLKIN
CLK
PLL LVSD CLK SELECT COMP PWM VCC
+
CLKOUT CLKSEL XI OSC XO VREG CPWM PWM OSC ECL 1/8 1/128 1/384 1/512
TSD
PWM OUT
24V
+
VREG
VREG
S/S
S/S PRI DRIVER
UL UH VL VH HALL LOGIC WL WH
F/R
F/R
LOGIC
CSD
SD OSC
HALL HYS AMP
CURR LIM
RF
IN1+ VCC
IN1-
IN2+
IN2-
IN3+
IN3- SOFT
LIM
GND
A11598
No. 6002-8/17
LB1875
Description of the LB1875
1. Speed control circuit This IC uses the PLL speed control technique which allows stable, high-precision motor rotation with low jitter. The PLL circuit performs phase comparison of the falling edge of the clock input (CLKIN) with the edge of the FG input. Control is based on the differential output. When the FGSEL pin is Low, only the falling edge of the FG signal is valid. When the pin is High or open, both edges are valid. When both edges are used, the FG waveform precision becomes critical. When using an external clock input (supplied from CLKIN pin), the FG servo frequency is determined by the following equation. fFG (servo) = f CLK (FGSEL = Low) fFG (servo) = f CLK/2 (FG SEL = High or open) When using the internal clock, the FG servo frequency is determined by the following equation. The number of FG pulses and the quartz oscillator frequency determine the motor rotation speed. fFG (servo) = f OSC/N (FGSEL = Low) fFG (servo) = f OSC/2N (FGSEL = High or open) fOSC: Quartz oscillator frequency N: Clock divisor (see table) 2. Output drive This IC allows selection of PAM drive or direct PWM drive. When the LIM pin is Low, the direct PWM mode is selected. The ON duty cycle of the UH, VH, and WH output (external bottomside transistor drive output) changes, thereby controlling the motor speed. Current control is also realized by changing the ON duty cycle to limit the current. At this time, the Schmitt comparator output of the FG is supplied at the PWM OUT pin. When bipolar transistors are used externally, the top-side transistors should not have an integrated diode, but Schottky barrier diodes should be used instead (to prevent feedthrough current caused by diode reverse recovery during PWM switching). When the LIM pin is High or open, the PAM drive mode is selected. The PWMOUT pin carries the PWM signal. This output can drive an external switching regulator circuit for varying the motor supply voltage and thereby controlling motor speed. Current control is also realized by changing the motor supply voltage. In this case, a delay in the switching regulator circuit will cause a delay in the current control action. During the delay, a higher current than the set current may flow, which must be taken into consideration when selecting output transistors. For applications where the motor has variable speed and control at low motor voltages is required, the lowest operation voltage is limited by the base voltage of the interface transistor for top-side output transistor drive. If this causes a problem, the base voltage must be made low (for example by dividing the VREG voltage with resistors). When FETs are used as topside output transistors, types which can be used at low gate voltages must be selected. 3. Current limiting circuit The current limiting circuit limits the peak current to the value I = VRF/Rf (V RF = 0.5V typ., Rf: current detector resistor). As mentioned above, in PAM drive mode, a current higher than the set current may flow during the delay interval. If the capacitor charge current of the switching regulator circuit is a problem, a smoothing capacitor may be inserted, with the negative side connected to the RF pin. If PWM noise is a problem in the RF waveform, a filter should be provided at the input.
No. 6002-9/17
LB1875
4. Reference clock Since the clock input of the PLL circuit (CLKIN) and the internal divisor output (CLKOUT) are separate, various applications are possible. (1) Using the internal divider circuit Basically, CLKIN and CLKOUT are shorted. If a division ratio other than the built-in ratio is required, an external divider circuit can be inserted between these two pins. [1] Using a quartz oscillator An oscillator using a quartz crystal and C, R components can be configured as shown below.
XI C3 C1 C2 R1 XO
C1, R1 : For stable oscillation C2 : For overtone oscillation prevention C3 : For crystal coupling
VREG
A11349
(Reference values)
Oscillator frequency (MHz) 2 to 3 3 to 7 7 to 9 9 to 10 C1 (F) 0.1 0.1 0.1 0.1 C2 (pF) 10 None None None C3 (pF) 100 47 22 12 R1 ( ) 330k 330k 330k 330k
The circuit configuration and values are for reference only. The quartz crystal characteristics as well as the possibility of floating capacitance and noise due to layout factors must be taken into consideration when designing an actual application. [Precautions for wiring layout design] Since the quartz oscillator circuit operates at high frequencies, it is susceptible to the influence of floating capacitance from the circuit board. Wiring should be kept as short as possible and traces should be kept narrow. [2] External clock input (equivalent to quartz oscillator, several MHz) When using an external signal source instead of a quartz oscillator, a resistor of about 13 k should be inserted in series at the XI input. The XO pin should be left open. Signal input level Low: 0 to 0.8 V High: 2.5 to 5 V (2) When not using the internal divider circuit When using an external signal source to supply a signal equivalent to the FG frequency (several kHz), the signal is input via the CLKIN pin. When not using a quartz oscillator, the XI pin should be left open or connected to the VREG pin (XO is open). 5. Hall input signal The Hall input requires a signal with an amplitude of at least the hysteresis width (24 mV max.). Taking possible noise influences into consideration, an amplitude of at least 100 mV is desirable. If noise at the Hall input is a problem, a noise-canceling capacitor (about 0.001 to 0.1 F) should be connected across the Hall input pins . Since the same-phase input range is 0 to VCC-2V, a Hall element can be connected in series if 12V is applied at the VCC pin. 6. FG input signal The FG input is designed mainly for input from a Hall element and has the same specifications as the Hall input. If the input is to be used for an FG pattern or other very low-level signal, an external amplifier must be used to amplify the signal first. When there is noise at the FG input, locking may be impaired and jitter may increase. If PWM switching noise or other noise is found to be present, countermeasures such as making the Hall element power supply more stable or connecting a capacitor across the input will be necessary.
No. 6002-10/17
LB1875
7. PWM frequency The PWM frequency is determined by the capacitance connected to the CPWM pin. . f PWM = 1/(15000 x C) . The PWM frequency should be between 15 and 50 kHz. If the frequency is too low, noise and control performance may be a problem. If it is too high, switching losses will increase. 8. LD output The LD1 output is ON when phase lock is achieved. Phase lock is evaluated only by the phase (through edge comparison), not by speed deviation. Therefore when LD1 is ON, speed deviation is affected by the FG signal acceleration for example when establishing the lock condition. (The lower the acceleration, the lower the speed deviation.) When it is necessary to limit speed deviation when LD1 is ON, the results of actual motor speed measurement must be applied. 9. Power supply When using FETs as bottom-side output transistors, applying a voltage of 12V to the VCC pin makes it possible to supply a gate voltage of about 10V. When using FETs or bipolar transistors that can handle a low gate voltage, the VCC and VREG pins can also be short- circuited to apply 5V. (In this case, do not apply voltage higher than 5.5V.) Since this IC is designed for use in high-current motors, the power supply line may fluctuate easily. Therefore a capacitor of sufficient capacitance must be provided between the VCC pin and ground, to assure stable operation. If a diode is used in the power line for reverse-connection protection, power line fluctuations may be further increased, which will require more capacitance. 10. Motor lock protection circuit To protect the IC and the motor itself when rotation is inhibited, a motor lock protection circuit is provided. If the LD output is High (unlocked) for a certain interval in the start condition, the external bottom-side transistors are turned off. The length of the interval is determined by the capacitance at the CSD pin. A capacitance of 0.1 F results in a trigger interval of about 10 seconds. . Trigger interval (S) = 110 x C (F) . The trigger interval should be set so as to leave sufficient leeway for motor startup. Speed reduction due to clock frequency switching does not trigger the protection circuit. When the protection circuit has been triggered, the condition can only be canceled by setting the system to the stop condition or by turning the power off and on again. When wishing not to use the motor lock protection circuit, connect the CSD pin to ground. 11. Low voltage protection circuit The low voltage protection circuit cuts off the bottom-side output transistors (external) when the voltage at the VREG pin falls below 3.75V (typ.). The circuit action is released when the voltage rises above approx. 4.0V (typ.). 12. F/R switching Forward/reverse switching in principle should be carried out while the motor is stopped. If switching is carried out while the motor is running, feedthrough current (due to output transistor delay) is prevented by the circuit design, but a high current will flow in the output transistors (due to counterelectromotive voltage and coil resistance). If such a condition is anticipated, the output transistors must be selected appropriately, to allow handling even higher current than in normal use. 13. Soft start In PAM drive mode, connecting a capacitor (approx. 0.01 to 0.1 F) between the SOFT pin and ground enables soft start (gradual increase in PWM ON duty cycle, causing a sloped rise in motor supply voltage). This prevents the current flow exceeding the set current due to switching regulator circuit delay at startup. The Soft start function is active only immediately after motor startup. When the motor is stopped, the output transistors are turned off, therefore the charge accumulated in the switching regulator smoothing capacitors can only be discharged as leak current of the output transistors. When the motor is restarted before the supply voltage has dropped, the soft start function will not be active. Therefore it is necessary to discharge the capacitors via a resistor so that the soft start function operates properly.
No. 6002-11/17
LB1875
Pin Descriptions
Pin number
1
Pin name
VREG
Equivalent circuit
VCC
Pin function
5V regulator output (control circuit power supply) For stable operation, pin should be connected to ground via a capacitor (0.1 F or more).
1
A11350
2 3
XI XO
VREG
Pin 2: Quartz oscillator input. Maximum oscillation frequency is 10 MHz Pin 3: Quartz oscillator output Generates reference clock. When an external clock (several MHz) is used, connect a resistor of about 13 k in series to the XI pin, so that the signal is input via the resistor. Leave the X O pin open.
3 2
A11351
4
S/S
VREG
Start/stop pin Low: Start High: Stop High when open.
30 k 5.6 K 4
A11352
5
CLKSEL
VREG
Divisor selector pin "L": (divisor 3072): 0 to 1.0V "M": (divisor 1024): 2.0 to 3.0V "H": (divisor 4093): 4.0V to VREG
30 k 5.6 k 5
High when open.
A11353
Continued on next page
No. 6002-12/17
LB1875
Continued from preceding page
Pin number
6
Pin name
CLKIN
Equivalent circuit
VREG
Pin function
Clock input (max. 10 kHz) Low: 0 to 1.5V High: 3.5V to VREG High when open.
30 k 5.6 K 6
A11354
7
CLKOUT
VREG 7
Quartz oscillator divider output Ratio is selected with pin 5. Open collector output
A11355
8
F/R
VREG
30 k 5.6 k 8
Forward/reverse switching pin Low: 0 to 1.5V High: 3.5V to VREG High when open.
A11356
9
FGSEL
VREG
30 k 5.6 k 9
FG comparator selector pin Low: 0 to 1.5V -> Speed control on FG single edge High: 3.5V to VREG -> Speed control on FG dual edge High when open.
A11357
10
LIM
VREG
30 k 5.6 k 10
Drive mode selector pin Low: 0 to 1.5V -> Direct PWM drive mode High: 3.5 V to VREG -> PAM drive mode High when open.
A11358
Continued on next page
No. 6002-13/17
LB1875
Continued from preceding page
Pin number
11
Pin name
LD1I
Equivalent circuit
VREG
Pin function
Phase lock detector output On when PLL phase lock is achieved. Open collector output
12
LD2
11 12
Phase lock detector output (LD1 inverted output) On when PLL phase lock is achieved. Open collector output Phase comparator output (PLL output) Outputs the phase difference as a signal with changing pulse duty cycle. The higher the duty cycle, the higher the output current.
A11359
13
PD
VREG
13
A11360
14
EI
VREG
Differential amplifier input
200 14
A11361
15
EO
VREG
Differential amplifier output Output current increases at Low.
15 20 k
A11362
16
TOC
VREG
Torque control input Normally connected to EO pin. When TOC pin goes Low, duty cycle of UH, VH, WH (direct PWM mode) or PWM output (PAM mode) changes, resulting in increased torque.
200 17 200 16
17
SOFT
A11363
Soft start control pin Connect to ground via a capacitor. Leave open when soft start is not to be used.
Continued on next page
No. 6002-14/17
LB1875
Continued from preceding page
Pin number
18
Pin name
PWM
Equivalent circuit
VREG
Pin function
PWM oscillator pin Connect to ground with a capacitor to set oscillation frequency.
200 18 2 k
A11364
19
PWMOUT
VREG
19
PWM output Open collector output (Darlington connection). In direct PWM mode (LIM pin Low) the output is an FG Schmitt output.
A11365
20
RF
VREG
Output current detector pin Connect to ground via a lower resistor. Sets maximum output current IOUT = 0.5/Rf.
5 k 23
A11366
21 23 25
WH VH UH
VCC
Output pin (for external bottom-side transistor drive) Performs duty cycle control in direct PWM mode (LIM pin Low).
21 23 25
A11367
22 24 26
WL VL UL
VCC
Output pin (for external bottom-side transistor drive) . Open collector output.
22 24 26
A11368
Continued on next page
No. 6002-15/17
LB1875
Continued from preceding page
Pin number
27
Pin name
V CC
Equivalent circuit
Pin function
Power supply pin (output and regulator circuit power supply). Connect to ground via capacitor to prevent noise. When using the IC with a single 5V source, short this pin to the VREG pin.
VCC
33 32 31 30 29 28
IN1+ IN1- IN2+ IN2- IN3+ IN3-
Hall inputs for various phases Logic "High" indicates VIN+>VIN-.
29 31 33 200 200
28 30 32
A11369
35 34
FG
+ IN
VCC
FGIN-
FG comparator input Pin 35: Non-inverted input Pin 36: Inverted input
35 200 200
34
A11370
36
CSD
VREG
200 19
Reference signal oscillator for motor lock protection circuit, clock interruption error protection circuit etc. Connect to ground via capacitor. Connect directly to ground if protection circuit is not to be used.
A11371
FRAME
GND
Ground
No. 6002-16/17
LB1875
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 6002-17/17

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