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INTEGRATED CIRCUITS
74F1763 Intelligent DRAM controller (IDC)
Product specification Supersedes data of 1989 Nov 17 IC15 Data Handbook 1999 Jan 08
Philips Semiconductors
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
FEATURES
* DRAM signal timing generator * Automatic refresh circuitry * Selectable row address hold and RAS precharge times * Facilitates page mode accesses * Controls 1 MBit DRAMs * Intelligent burst-mode refresh after page-mode access cycles
PRODUCT DESCRIPTION
The Philips Semiconductors Intelligent Dynamic RAM Controller is a 1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM Controller. It contains automatic signal timing, address multiplexing and refresh control required for interfacing with dynamic RAMs. Additional features have been added to this device to take advantage of technological advances in Dynamic RAMs. A Page-Mode access pin allows the user to assert RAS for the entire access cycle rather than the pre-defined four-clock-cycle pulse width used for normal random access cycles. In addition, the user has the
ability to select the RAS precharge time and Row-Address Hold time to fit the particular DRAMs being used. DTACK has been modified from previous family parts to become a negative true, tri-stated output. The options for latched or unlatched address are contained on a single device by the addition of an Address Latch Enable (ALE) input. Finally, a burst refresh monitor has been added to ensure complete refreshing after length page-mode access cycles. With a maximum clock frequency of 100 MHz, the F1763 is capable of controlling DRAM arrays with access times down to 40 nsec. TYPICAL SUPPLY CURRENT (TOTAL) 150 mA
TYPE 74F1763
fMAX 100 MHz
ORDERING INFORMATION
PACKAGES 48-pin Plastic DIP COMMERCIAL RANGE VCC = 5V "10%; TA = 0_C TO 70_C N74F1763N PKG DWG # SOT240-1
INPUT AND OUTPUT LOADING FAN-OUT TABLENO TAG
PINS REQ CP PAGE PRECHRG HLDROW DTACK GNT RCP RA0-9 CA0-9 ALE RAS CAS MA0-9 DRAM Request Input Clock Input Page Mode Select Input RAS Precharge Select Input Row Hold Select Input Data Transfer Ack. Output Access Grant Output Refresh Clock Input Row Address Inputs Column Address Inputs Address Latch Enable Input Row Address Strobe Output Column Address Strobe Output DRAM Address Outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/80 50/80 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 NA NA NA LOAD VALUE HIGH/LOW 20 mA/0.6 mA 20 mA/0.6 mA 20 mA/0.6 mA 20 mA/0.6 mA 20 mA/0.6 mA 35 mA/60 mA 35 mA/60 mA 20 mA/0.6 mA 20 mA/0.6 mA 20 mA/0.6 mA 20 mA/0.6 mA 35 mA/60 mA 35 mA/60 mA 35 mA/60 mA
NOTES: One (1.0) FAST Unit Load is defined as 20 mA in the HIGH state and 0.6 mA in the LOW state. FAST Unit Loads do not correspond to DRAM Input Loads. See Functional Description for details.
1999 Jan 08
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853-1406 20619
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
BLOCK DIAGRAM
RAS CAS PAGE CP PRECHRG HLDROW DTACK
RAS, CAS, MUX, DTACK TIMING
REQ
REFRESH ARBITRATION
GNT
RCP
BURST REFRESH MONITOR REFRESH ADDRESS COUNTER
RA0-9
ROW ADDRESS LATCH
MULTIPLEXER MA0-9
CA0-9
COLUMN ADDR. LATCH
ALE
SF01400
DIP PIN CONFIGURATION
GNT HLDROW PRECHRG RAS CAS DTACK MA0 MA1 MA2 1 2 3 4 5 6 7 8 9 48 REQ 47 PAGE 46 CP
PLCC PIN CONFIGURATION
PRECHRG
REQ
PAGE
GNT
RCP
CAS
RAS
43 CA0 42 RA1 41 CA1 40 RA2 39 CA2 38 VCC 37 VCC 36 VCC 35 RA3 34 CA3 33 RA4 32 CA4 31 RA5 30 CA5 29 RA6 28 CA6 27 RA7 26 CA7 25 RA8 MA0 MA1 MA2 7 8 9
6
5
4
3
2
1
44 43 42 41 40 39 CA0 38 RA1 37 CA1 36 RA2 35 CA2 34 VCC 33 RA3 32 CA3 31 RA4 30 CA4 29 RA5
MA3 10 GND 11 GND 12 GND 13 GND 14 MA4 15 MA5 16 MA6 17 MA7 18 MA8 19 MA9 20 ALE 21 CA9 22 RA9 23 CA8 24
MA3 10 GND 11
GND 12 MA4 13 MA5 14 MA6 15 MA7 16 MA8 17 18 19 20 21 22 23 24 25 26 27 28 MA9 CA9 RA9 CA8 RA8 CA7 RA7 CA6 RA6 CA5 ALE
SF01401
CP
RA0
44 RA0
HLDROW
45 RCP DTACK
SF01402
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
PIN DESCRIPTION
PINS SYMBOL REQ GNT PAGE DIP 48 1 47 TYPE Input Output Input NAME AND FUNCTION Active Low Memory Access Request input, must be asserted for the entire DRAM access cycle. REQ is sampled on the rising edge of the CP clock. Active High Grant output. When High indicates that a DRAM access (inactive during refresh) cycle has begun. Asserted from the rising edge of the CP clock. Active Low Page-Mode Access input. Forces the IDC to keep RAS asserted for as long as the PAGE input is Low and REQ is asserted Low. Row Address Hold input. If Low will configure the IDC to maintain the row addresses for a full CP clock cycle after RAS is asserted. If High will program the IDC to maintain row addresses for a 1/2 CP clock cycle after RAS is asserted. RAS Precharge input. A Low will program the IDC to guarantee a minimum of 4 CP clock cycles of precharge. A High will guarantee 3 clock cycles of precharge. Clock input. Used by the Controller for all timing and arbitration functions. Refresh Clock input. Divided internally by 64 to produce an internal Refresh Request. Active Low, 3-state Data Transfer Acknowledge output. Enabled by the REQ input and asserted four clock cycles after the assertion of RAS, 3-stated when REQ goes High.
HLDROW
2
Input
PRECHRG CP RCP DTACK
3 46 45 6 44, 42, 40, 35, 33, 31, 29, 27, 25, 23 43, 41, 39, 34, 32, 30, 28, 26, 24, 22
Input Input Input Output
RA0-9
Inputs
Row Address inputs.
CA0-9
Inputs
Column Address inputs. Propagated to the MA0-9 outputs 1 CP clock cycle after RAS is asserted, if HLDROW = 0 or 1/2 clock cycle later if HLDROW is 1. Active Low Row Address Strobe. Asserted for four clock cycles during each refresh cycle regardless of the PAGE input. Also asserted for four clock cycles during processor access if the PAGE input is High. If PAGE is Low, RAS is negated upon negation of PAGE or REQ, whichever occurs first. Active Low Column Address Strobe. Always asserted 1.5 CP clock cycles after the assertion of RAS. Negated upon negation of REQ. HLDROW input pin does not affect RAS to CAS timing. DRAM multiplexed address outputs. Row and column addresses asserted on these pins during an access cycle. Refresh counter addresses presented on these outputs during refresh cycles. Active Low Address Latch Enable input. A Low on this pin will cause the address latches to be transparent. A High level will latch the RA0-9 and CA0-9 inputs. +5V "10% Supply voltage. Ground
RAS
4
Output
CAS MA0-9 ALE VCC GND
5 7-10, 15-20 21 36-38 11-14
Output Output Input
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
FUNCTIONAL DESCRIPTION
The 74F1763 1 Megabit Intelligent DRAM Controller (IDC) is a synchronous device with most signal timing being a function of the CP input clock.
RAS precharge timing
In order to meet the RAS precharge requirement of dynamic RAMs, the controller will hold-off a subsequent RAS signal assertion due to a processor access request or a refresh cycle for four or three full CP clock cycles from the previous negation of RAS, depending on the state of the PRECHRG input. If the PRECHRG input is Low, RAS remains High for at least 4 CP clock cycles. If the PRECHRG input is High RAS remains High for at least 3 CP clock cycles.
Arbitration
Once the DRAM's RAS precharge time has been satisfied, the REQ input is sampled on each rising edge of the CP clock and an internally generated refresh request is sampled on each falling edge of the same clock. When only one of these requests is sampled as active the appropriate memory cycle will begin immediately. For a memory access cycle this will be indicated by GNT and RAS outputs both being asserted and for a refresh cycle by multiplexing refresh address to the MA0-9 outputs and subsequent assertion of RAS after 1/2CP clock cycle. If both memory access and refresh requests are active at a given time the request sampled first will begin immediately and the other request (if still asserted) will be serviced upon completion of the current cycle and it's associated RAS precharge time.
Refresh timing
The refresh address counter wakes-up in an all 1's state and is an up counter. The refresh clock (RCP) is internally divided down by 64 to produce an internal refresh request. This refresh request is recognized either immediately or at the end of a running memory access cycle. Due to the possibility that page mode access cycles may be lengthy, the controller keeps track of how many refresh requests have been missed by logging them internally (up to 128) and servicing any pending refresh requests at the end of the memory access cycle. The controller performs RAS-only refresh cycles until all pending refresh requests are depleted.
Memory access
The row (RA0-9) and column (CA0-9) address inputs are latched when ALE input is High. When ALE is Low the input addresses propagate directly to the outputs. When GNT and RAS are asserted, after a REQ has been sampled the RA0-9 address inputs will have already propagated to the MA0-9 outputs for the row address. One or one-half CP clock cycles later (depending on the state of the HLDROW input) the column address (CA0-9) inputs are propagated to the MA0-9 outputs. CAS is always asserted one and one-half CP clock cycles after RAS is asserted. If the PAGE input is High, RAS will be negated approximately four CP clock cycles after its initial assertion. At this time the DTACK output becomes valid indicating the completion of a memory access cycle. The IDC will maintain the state of all its outputs until the REQ input is negated ( see timing waveforms).
Page-mode access
Fast accesses to consecutive locations of DRAM can be realized by asserting the PAGE input as shown in the timing waveforms. In this mode, the controller does not automatically negate RAS after four CP clock cycles, but keeps it asserted throughout the access cycle. By using external gates, the CAS output can be gated on and off while changing the column address inputs to the controller, which will propagate to the MA0-MA9 address outputs and provide a new column address. This is only useful if the ALE input is Low, enabling the user to charge addresses. This mode can be used with DRAMs that support page or nibble mode addressing.
Output driving characteristics
Considering the transmission line characteristic of the DRAM arrays, the outputs of the IDC have been designed to provide incident-edge switching (in Dual-Inline-Packaged memory arrays), needed in high performance systems. For more information on the driving characteristics, please refer to Philips Semiconductors application note AN218. The driving characteristics of the 74F1763 are the same as those of the 74F765 shown in the application note.
Row address hold times
If the HLDROW input of the IDC is High the row address outputs will remain valid 1/2 CP clock cycle after RAS is asserted. If the HLDROW input is Low the row address outputs will remain valid one CP clock cycle after RAS is asserted.
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT TA TSTG Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +VCC 120 0 to +70 -65 to +150 UNIT V V mA V mA _C _C
RECOMMENDED OPERATION CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL TA Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current1 Low-level output current1 Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -15 24 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA _C
NOTE: 1. Transient currents will exceed these values in actual operation.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN "10% VCC "5% VCC "5% VCC "10% VCC "5% VCC "5% VCC LIMITS MIN 2.5 2.7 2.4 0.35 0.35 0.35 -0.73 0.50 0.50 0.80 -1.2 100 20 -0.6 -100 -225 220 3.4 TYP2 MAX UNIT V V V V V V V mA mA mA mA mA
VOH
High-level output voltage
IOH = -15 mA IOH2 = -35 mA IOL = 24 mA IOL2 = 60 mA
4 3
VOL
Low-level output voltage
VIK II IIH IIL IOS ICC
Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Output current5 Supply current (total)
VCC = MIN, II = IIK VCC = 0.0V, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.25V VCC = MAX
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, TA = 25_C. 3. IOH2 is transient current necessary to guarantee a Low to High transition in a 70W transmission line. 4. IOL2 is transient current necessary to guarantee a High to Low transition in a 70W transmission line. 5. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
AC ELECTRICAL CHARACTERISTICS
LIMITS TEST CONDITIONS MIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 CP clock period (tcp) CP clock low time CP clock high time RCP clock period RCP clock low time RCP clock high time Setup time REQ(#) to CP(") REQ High hold time after REQ High pulse width2 Propagation delay CP(") to GNT High Propagation delay REQ(") to GNT Low ALE pulse width Low RA0-9, CA0-9 High or Low setup to ALE(") ALE(") to RA0-9, CA0-9 High or Low hold Propagation delay RA0-9, CA0-9 High or Low to MA0-93 Propagation delay ALE(#) to MA0-9 Propagation delay CP(") to RAS(#) RAS(#) to MA0-9 (column address) skew RAS(#) to MA0-9 (column address) skew RAS(#) to RAS(") skew Propagation delay CP(") to RAS(") Propagation delay REQ(") to RAS(")4 Propagation delay CP(#) to CAS(#) Propagation delay PAGE(") to RAS(")4 RAS(#) to CAS(#) skew Propagation delay REQ(") to CAS(") MA0-9 (column address) to CAS(#) skew MA0-9 (column address) to CAS(#) skew Set-up time PAGE(#) to CP(") HLDROW = 0 HLDROW = 1 HLDROW = 0 PAGE = 1 ALE Low CP(")1 10 5 5 100 10 10 4 0 1/2tcp + 5 8.5 8.5 4 2 1 4 5.5 8.5 1/2tcp - 2 1tcp - 2 4tcp + 1.5 12 14.5 6 10 1.5tcp-4.5 10 1tcp - 8 1/2tcp - 8 2 1/2tcp + 5 11 10.5 1 0 0 7.5 8.5 10.5 1/2tcp + 2 1tcp + 2 4tcp + 3.5 14 17.5 8 12.5 1.5tcp-2.5 12 1tcp - 4 1/2tcp - 4 11 13 12.5 1/2tcp + 5.5 1tcp + 5.5 4tcp + 6 16.5 20 10 15 1.5tcp-0.5 15 1tcp - 0.5 1/2tcp - 0.5 1/2tcp + 5 13.5 13 2 TA = 25_C VCC = +5.0V "10% CL = 300pF RL = 70W TYP MAX TA = 0_C to +70_C VCC = +5.0V "10% CL = 300pF RL = 70W MIN 10 5 5 100 10 10 4 0 1/2tcp + 5 8.5 8.5 4 2 1 4 5.5 8.5 1/2tcp - 2.5 1tcp - 2.5 4tcp + 1 12 14 6 10 1.5tcp-5.5 10 1tcp - 9 1/2tcp - 9 2 14 15 14 1/2tcp + 7 1tcp + 7 4tcp + 6.5 18.5 24 11 17 1.5tcp 17 1tcp - 0.5 1/2tcp - 0.5 1/2tcp + 5 15.5 14 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NO
PARAMETER
UNIT
1999 Jan 08
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
AC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS TEST CONDITIONS MIN 30 31 32 33 34 35 36 Propagation delay REQ(#) to DTACK(") Propagation delay CP(") to DTACK(#) Propagation delay REQ(") to DTACK (3-state) MA0-9 (refresh address) to RAS(#) skew RAS(#) to MA0-9 (refresh address) skew RAS(") to RAS(#) skew (precharge) RAS(") to RAS(#) skew (precharge) PRECHRG = 0 PRECHRG = 1 6 7.5 9 1/2tcp - 5 1tcp - 2 4tcp - 6 3tcp - 6 4tcp - 3.5 3tcp - 3.5 4tcp - 1.5 3tcp - 1.5 TA = 25_C VCC = +5.0V "10% CL = 300pF RL = 70W TYP 8 9.5 12 MAX 11.5 12 13 TA = 0_C TO +70_C VCC = +5.0V "10% CL = 300pF RL = 70W MIN 6 7.5 9 1/2tcp - 6.5 1tcp - 2.5 4tcp - 6.5 3tcp + 1 4tcp - 6.5 3tcp - 6.5 MAX 12 13 15.5 ns ns ns ns ns ns ns
NO
PARAMETER
UNIT
NOTES: 1. REQ High hold means that, if REQ is High at the rising clock edge, it is guaranteed that the REQ input was not sampled as Low. 2. A 50% duty cycle clock is recommended. If the duty cycle of the clock is not 50%, REQ should be held high for enough time such that a falling CP clock edge samples REQ as High. This is to ensure that refresh cycles don't get locked-up. 3. When ALE is Low, the address input latches are in the transparent mode and therefore any changes in the address inputs will be propagated to the MA0-9 outputs. Figure 2 illustrates RA0-9 inputs propagating to the MA0-9 outputs, but later in the cycle, if ALE is still Low when the CA0-9 inputs are multiplexed to the MA0-9 outputs the CA0-9 inputs will be in the transparent mode. 4. If PAGE is High and REQ is Low, RAS is automatically negated after approximately 4 CP clock cycles. If PAGE is Low and REQ is also Low, RAS will be negated when PAGE goes High. RAS will always be negated when REQ goes High regardless of the state of PAGE input.
TIMING DIAGRAMS
1 3
CP 2
4
6
RCP 5
SF01403
Figure 1. Clock cycle timing
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TIMING DIAGRAMS (Continued)
CP 8 7 REQ 11 9
10 GNT
ALE 12 13 14
RA0-9, CA0-9
MA0-9
RAS 23 25 CAS 27 28 PAGE = 1
PAGE
DTACK
NOTE 1: If the RA0-9 and CA0-9 address inputs are not latched, RA0-9 inputs should remain valid until row address hold time is met and CA0-9 inputs should remain valid until column address hold time is met. NOTE 2: MA0-9 outputs will contain the present row address on the RA0-RA9 inputs or the last row address latched into the device. NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low. SF01404
1999 Jan 08
CC CC CCCCCCCCCCCCCCCCCCCCCCCCC C CCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC
VALID ADDRESS 15 NOTE 1 HLDROW = 0 16 HLDROW = 1 NOTE 2 VALID ROW ADDRESS VALID COLUMN ADDRESS 18 17 19 21 22 20 24 26 3-STATE
CCCCCCCCCC CCCCCCCCCC CCCCCCCCCC
NOTE 3 30
29
31 32 3-STATE
Figure 2. Memory access cycle timing
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TIMING DIAGRAMS (Continued)
CP
REQ
GNT
ALE
RA0-9, CA0-9
MA0-9
RAS
CAS
DTACK
NOTE 1: REQ input is a don't care during a memory refresh cycle. If REQ is asserted during a refresh cycle, it will be recognized at the first rising CP clock edge, following the refresh cycle and its associated RAS precharge time (see Figure 4). NOTE 2: RA0-9 and CA0-9 address inputs may be latched at anytime during a memory refresh cycle. However, a memory access cycle will not begin until after the completion of the refresh cycle. NOTE 3: RA0-9 and CA0-9 if in the transparent mode do not propogate to the MA0-9 outputs during a refresh cycle. NOTE 4: MA0-9 output will contain the present row address on the RA0-RA9 inputs or the last row address latched into the device. SF01405
1999 Jan 08
CCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCC
NOTE 1 NOTE 2 NOTE 3 PRECHRG = 1 PRECHRG = 0 NOTE 4 REFRESH ADDR. 33 34 35 36 20 REFRESH ADDR. 33 34 20 NEXT REFRESH ADDRESS PRECHRG = 1 PRECHRG = 0 PRECHRG = 1 PRECHRG = 0 3-STATE
Figure 3. Refresh cycle timing following a memory access cycle
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TIMING DIAGRAMS (Continued)
CP 8 7 REQ 11 9
10 GNT
ALE 12 13 14
RA0-9, CA0-9
MA0-9
RAS 36 35 CAS 25 28 23 PAGE = 1
PAGE
DTACK
NOTE 1: If the RA0-9 and CA0-9 address inputs are not latched, RA0-9 inputs should remain valid until row address hold time is met and CA0-9 inputs should remain valid until column address hold time is met. NOTE 2: MA0-9 outputs will contain the present row address on the RA0-RA9 inputs or the last row address latched into the device. NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low. SF01406
1999 Jan 08
CCCCCCCCCCCCCCCCCC C C CCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCC C
VALID ADDRESS 15 NOTE 1 HLDROW = 0 16 HLDROW = 1 REFRESH ADDRESS PRECHRG = 0 REFRESH ADDRESS NOTE 2 VALID ROW ADDRESS 18 17 19 20 21 22 VALID COLUMN ADDRESS PRECHRG = 1 24 26 3-STATE
Figure 4. Memory access cycle timing following a refresh cycle
CCCCCCCCC CCCCCCCCC CCCCCCCCC
NOTE 3 30
27
29
31 32 3-STATE
11
Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
PU 1, 7, 9, 10 33.34 MHz CP F160A Q0 Q2 16.67 MHz CPU CLOCK
PU D Q D
CP PRECHRG
RCP RAS RAS
C
C
Q
HLROW 74F1763 DRAM CONTROLLER
CAS
MEMORY SELECT (FROM ADDRESS DECODER AS A3 A2 A4-A12 A13-A21
REQ PAGE ALE CA9 RA9 RA0-8 CA0-8 MA0-MA9 MA0-MA9
CAS0 A0 A1 PLD 10 CAS1
SIZ0
CAS2
SIZ1
CAS3
STERM D Q
C
Q DS Q3 F164 CP MR
CBACK
CBREQ DSACK0 DSACK1 D Q
C
SF01407
Figure 5. 16.67 MHz 68030 interface with 74F1763 for cache burst mode support using 4Mbytes of 100nsec. nibble-mode DRAMs (Four 32 bit words read to or written from cache in only clock cycles
1999 Jan 08
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT RL 90% VM 10% tTHL (tf ) CL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit Simulating RAM Boards DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM 74F 3.0V 1.5V Rep. Rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF01408
1999 Jan 08
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
DIP48: plastic dual in-line package; 48 leads (600 mil)
SOT240-1
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
NOTES
1999 Jan 08
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Philips Semiconductors
Product specification
Intelligent DRAM controller (IDC)
74F1763
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 02-99 Document order number: 9397-750-05195
Philips Semiconductors
1999 Jan 08 16

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