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UDA1384
Multichannel audio coder-decoder
Rev. 02 -- 17 January 2005 Product data sheet
1. General description
The UDA1384 is a single-chip consisting of 4 plus 1 Analog-to-Digital Converters (ADC) and 6 Digital-to-Analog Converters (DAC) with signal processing features employing bitstream conversion techniques. The multichannel configuration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature. The UDA1384 supports conventional 2 channels per line data transfer conformable to the I2S-bus format with word lengths of up to 24 bits, the MSB-justified format with word lengths of up to 24 bits and the LSB-justified format with word lengths of 16 bits, 20 bits and 24 bits, as well as 4 channels to 6 channels per line transfer mode. The device also supports a combination of the MSB-justified output format and the LSB-justified input format. The UDA1384 has special sound processing features in the Direct Stream Digital (DSD) playback mode, de-emphasis, volume and mute which can be controlled via the L3-bus or I2C-bus interface.
2. Features
2.1 General
s s s s s 2.7 V to 3.6 V power supply 5 V tolerant digital inputs 24-bit data path Selectable control: via L3-bus or I2C-bus microcontroller interface Supports sample frequency ranges for: x Audio ADC: fs = 16 kHz to 100 kHz x Voice ADC: fs = 7 kHz to 50 kHz x Audio DAC: fs = 16 kHz to 200 kHz Separate power control for ADC and DAC ADC plus integrated high-pass filter to cancel DC offset Integrated digital filter plus DAC Slave mode only applications Easy application
s s s s s
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
2.2 Multiple format data interface
s Audio interface supports standard I2S-bus, MSB-justified, LSB-justified and two multichannel formats s Voice interface supports I2S-bus and mono channel formats
2.3 Digital sound processing
s Control via L3-bus or I2C-bus: x Channel independent digital logarithmic volume x Digital de-emphasis for fs = 32 kHz, 44.1 kHz, 48 kHz or 96 kHz x Soft or quick mute x Output signal polarity control
2.4 Advanced audio configuration
s Inputs: x 4 single-ended audio inputs (2 x stereo) with programmable gain amplifiers x 1 single-ended voice input s Outputs: x 6 differential audio outputs (3 x stereo) s DSD mode to support stereo DSD playback s High linearity, wide dynamic range and low distortion s DAC digital filter with selectable sharp or soft roll-off
3. Applications
s Excellently suitable for multichannel home audio-video application
4. Quick reference data
Table 1: Quick reference data VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 C; RL = 22 k; all voltages referenced to ground (pins VSS); unless otherwise specified. Symbol Supplies VDDA(AD) VDDA(DA) VDDD IDDA(AD) IDDA(DA) IDDD ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current fADC = 48 kHz fDAC = 48 kHz 2.7 2.7 2.7 3.3 3.3 3.3 30 20 31 3.6 3.6 3.6 V V V mA mA mA Parameter Conditions Min Typ Max Unit
digital supply current fADC = fDAC = 48 kHz; fVOICE = 48 kHz
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Product data sheet
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UDA1384
Multichannel audio coder-decoder
Table 1: Quick reference data ...continued VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 C; RL = 22 k; all voltages referenced to ground (pins VSS); unless otherwise specified. Symbol IDDD(pd) Parameter Conditions Min -20 at 0 dB setting; 900 mV input at -1 dBFS at -60 dBFS; A-weighted code = 0; A-weighted
[1] [2]
Typ 18 14 -1.2 -88 -37 98 100
Max +85 -0.7 -82 -30 -
Unit mA mA C dB dB dB dB dB
digital supply current audio and voice in Power-down mode ADCs power-down DAC power-down ambient temperature digital output level total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation
Tamb D0 (THD+N)/S
Audio analog-to-digital converter -2.5 89 -
S/N cs
Digital-to-analog converter Differential mode Vo(rms) (THD+N)/S output voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation output voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation at 0 dBFS digital input at 0 dBFS at -60 dBFS; A-weighted code = 0; A-weighted at 0 dBFS digital input at 0 dBFS at -60 dBFS; A-weighted code = 0; A-weighted 1.9 100 2.0 -98 -50 110 114 1.0 -88 -45 105 110 2.1 -89 -45 V dB dB dB dB V dB dB dB dB
S/N cs Vo(rms) (THD+N)/S
Single-ended mode
S/N cs
[1] [2]
The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. The input voltage to the ADC scales proportionally with the power supply voltage.
5. Ordering information
Table 2: Ordering information Package Name UDA1384H QFP44 Description plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm Version SOT307-2 Type number
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Product data sheet
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UDA1384
Multichannel audio coder-decoder
6. Block diagram
VDDA(AD) 5 VINL1 2 PGA ADC 1L VSSA(AD) 3 VADCP 9 ADC 1R VADCN 7 PGA Vref 1 4 VINR1
VINL2
6 PGA 10 LNA
ADC 2L
ADC 2R
PGA
8
VINR2
VVOICE
DECIMATION FILTER ADC DC-CANCELLATION FILTER
TEST
11
TEST
DECIMATION FILTER HP FILTER DATAV BCKV WSV PLL 21 MCCLK MCMODE MCDATA I2C_L3 20 22 30 L3-BUS OR I2C-BUS CONTROL INTERFACE 16 17 18 I2S-BUS INTERFACE 3
CLOCK
19
SYSCLK
13 I2S-BUS INTERFACE 1 12 14 15
DATAAD1 DATAAD2 BCKAD WSAD
PLL 23 I2S-BUS INTERFACE 2 24 25 26 27 WSDA BCKDA DATADA1 DATADA2 DATADA3
VOLUME, MUTE, DE-EMPHASIS 29 28 NOISE SHAPER VDDD VSSD
INTERPOLATION FILTER
UDA1384
VOUT1N VOUT1P VOUT3N VOUT3P VOUT5N VOUT5P
32 31 36 35 42 41
- + - + - + 37 VDDA(DA) DAC 5 40 VSSA(DA) DAC 6 DAC 3 DAC 4 DAC 1 DAC 2
- + - + - +
34 33 39 38 44 43
VOUT2N VOUT2P VOUT4N VOUT4P VOUT6N VOUT6P
mce639
Fig 1. Block diagram
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UDA1384
Multichannel audio coder-decoder
7. Pinning information
7.1 Pinning
37 VDDA(DA) 40 VSSA(DA) 39 VOUT4N 42 VOUT5N 36 VOUT3N 34 VOUT2N 33 VOUT2P 32 VOUT1N 31 VOUT1P 30 I2C_L3 29 VDDD 28 VSSD 27 DATADA3 26 DATADA2 25 DATADA1 24 BCKDA 23 WSDA DATAAD2 12 DATAAD1 13 BCKAD 14 WSAD 15 DATAV 16 BCKV 17 WSV 18 SYSCLK 19 MCMODE 20 MCCLK 21 MCDATA 22
001aac311
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44 VOUT6N
41 VOUT5P
38 VOUT4P
Vref VINL1 VSSA(AD) VINR1 VDDA(AD) VINL2 VADCN VINR2 VADCP
1 2 3 4 5 6 7 8 9
UDA1384H
VVOICE 10 TEST 11
Fig 2. Pin configuration
7.2 Pin description
Table 3: Symbol Vref VINL1 VSSA(AD) VINR1 VDDA(AD) VINL2 VADCN VINR2 VADCP VVOICE TEST DATAAD2 DATAAD1 BCKAD WSAD
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Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type AIO AIO AGND AIO AS AIO AIO AIO AIO AIO DID DO DO DIS DI Description ADC reference voltage ADC 1 input left ADC analog ground ADC 1 input right ADC analog supply voltage ADC 2 input left ADC reference voltage N ADC 2 input right ADC reference voltage P voice ADC input test input; must be connected to digital ground (VSSD) in application ADC 2 data output ADC 1 data output ADC bit clock input ADC word select input
Product data sheet
Rev. 02 -- 17 January 2005
35 VOUT3P
43 VOUT6P
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UDA1384
Multichannel audio coder-decoder
Pin description ...continued Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Type DO DIS DIO DIS DI DIS IIC DI DIS DI DI DI DGND DS DI AIO AIO AIO AIO AIO AIO AS AIO AIO AGND AIO AIO AIO AIO Description voice data output voice bit clock input voice word select input or output system clock input: 256fs, 384fs, 512fs or 768fs L3-bus L3MODE input or I2C-bus DAC mute control input L3-bus L3CLOCK input or I2C-bus SCL input L3-bus L3DATA input and output or I2C-bus SDA input and output DAC word select input DAC bit clock input DAC channel 1 and channel 2 data input DAC channel 3 and channel 4 data input DAC channel 5 and channel 6 data input digital ground digital supply voltage selection input for L3-bus or I2C-bus control DAC 1 positive output DAC 1 negative output DAC 2 positive output DAC 2 negative output DAC 3 positive output DAC 3 negative output DAC analog supply voltage DAC 4 positive output DAC 4 negative output DAC analog ground DAC 5 positive output DAC 5 negative output DAC 6 positive output DAC 6 negative output
Table 3: Symbol DATAV BCKV WSV SYSCLK MCMODE MCCLK MCDATA WSDA BCKDA DATADA1 DATADA2 DATADA3 VSSD VDDD I2C_L3 VOUT1P VOUT1N VOUT2P VOUT2N VOUT3P VOUT3N VDDA(DA) VOUT4P VOUT4N VSSA(DA) VOUT5P VOUT5N VOUT6P VOUT6N
[1]
See Table 4.
Table 4: Type AGND AIO AS DGND DI DID DIO
Pin types Description analog ground analog input and output analog supply digital ground digital input digital input with internal pull-down resistor digital input and output
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UDA1384
Multichannel audio coder-decoder
Pin types ...continued Description digital Schmitt-triggered input digital output digital supply input and open-drain output for I2C-bus
Table 4: Type DIS DO DS IIC
8. Functional description
8.1 System clock
The UDA1384 operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock. The audio ADC part, the voice ADC part and the DAC part can operate at different sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency (SYSCLK, WSDA and DSD modes). The voice ADC part supports a sampling frequency up to 50 kHz and the audio ADC supports a sampling frequency up to 100 kHz. The DAC sampling frequency range is extended up to 200 kHz with the range above 100 kHz being supported through 192 kHz sampling mode, which halves the oversampling ratio of SYSCLK and internal clocks. The mode of operation of the audio and voice channels can be set via the L3-bus or I2C-bus microcontroller interface and are summarized in Table 5 and Table 6. When applied, the system clock must be locked in frequency to the corresponding digital interface clocks. The voice ADC part can either receive or generate the WSV signal as shown in Table 6.
Table 5: Mode SYSCLK Audio ADC and DAC operating clock mode Audio ADC Clock SYSCLK Frequency 256fs, 384fs, 512fs or 768fs Audio DAC Clock SYSCLK SYSCLK DAC-WS ADC-WS SYSCLK WSAD 256fs, 384fs, 512fs or 768fs 1fs WSDA SYSCLK SYSCLK WSDA DSD Table 6: Mode WSV-in WSV-out
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Frequency 256fs, 384fs, 512fs or 768fs 128fs, 192fs, 256fs or 384fs; 192 kHz sampling mode 1fs 256fs, 384fs, 512fs or 768fs 128fs, 192fs, 256fs or 384fs; 192 kHz sampling mode 1fs 44.1 kHz x 512
WSDA SYSCLK
1fs 44.1 kHz x 512
WSDA SYSCLK
Voice ADC operating clock mode Voice ADC Bit clock frequency (BCKV) input: 32fs, 64fs, 128fs or 256fs input: 32fs, 64fs, 128fs or 256fs Word select (WSV) input output
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UDA1384
Multichannel audio coder-decoder
8.2 Audio analog-to-digital converter (audio ADC)
The audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended ADCs with programmable gain stage (from 0 dB to 24 dB with 3 dB steps), controlled via the microcontroller interface. Using the PGA feature, it is possible to accept an input signal of 900 mV (RMS) or 1.8 V (RMS) if an external resistor of 10 k is used in series. The schematic of audio ADC front-end is shown in Figure 3.
10 k (0 dB setting) input signal 2 V (RMS) VINL, 10 k VINR 10 k ADC Vref VDDA = 3.3 V
mgu582
Fig 3. Schematic of audio ADC front-end
8.3 Voice Analog-to-Digital Converter (voice ADC)
The voice analog-to-digital front-end of the UDA1384 consists of a single-channel single-ended ADC with a fixed gain (26 dB) Low Noise Amplifier (LNA). Together with the digital variable gain amplification stage, the voice ADC provides optimal processing and reproduction of the microphone signal. The supported sampling frequency range is from 7 kHz to 50 kHz. Power-down of the LNA and the ADC can be controlled separately.
8.4 Decimation filter of audio ADC
sin x 4 The decimation from 64fs is performed in two stages. The first stage realizes ---------- x characteristics with a decimation factor of 8. The second stage consists of three half-band filters, each decimating by a factor of 2. The filter characteristics are shown in Table 7.
Table 7: Item Pass-band ripple Pass-band droop Stop band Dynamic range Decimation filter characteristics (audio ADC) Condition 0fs to 0.45fs 0.45fs > 0.55fs 0fs to 0.45fs Value (dB) 0.01 -0.2 -70 > 135
8.5 Decimation filter of voice ADC
The voice ADC decimation filter is realized with the combination of a Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter for shorter group delay. The filter characteristics are shown in Table 8. During the power-on sequence, the output of the ADC is hard muted for a certain period. This hard-mute time can be chosen between 1024 samples and 2048 samples.
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UDA1384
Multichannel audio coder-decoder
Decimation filter characteristics (voice ADC) Condition 0fs to 0.45fs 0.45fs > 0.55fs 0fs to 0.45fs Value (dB) 0.05 -0.2 -65 > 110
Table 8: Item
Pass-band ripple Pass-band droop Stop band Dynamic range
8.6 Interpolation filter of DAC
The digital interpolation filter interpolates from 1fs to 128fs (or to 64fs in the 192 kHz sampling mode) by cascading FIR filters, and has two sets of filter coefficients for sharp and slow roll-off as given in Table 9 and Table 10.
Table 9: Item Pass-band ripple Stop band Dynamic range Table 10: Item Pass-band ripple Pass-band droop Stop band Dynamic range Interpolation filter characteristics (sharp roll-off) Condition 0fs to 0.45fs > 0.55fs 0fs to 0.45fs Value (dB) 0.002 -75 > 135
Interpolation filter characteristics (slow roll-off) Condition 0fs to 0.22fs 0.45fs > 0.78fs 0fs to 0.22fs Value (dB) 0.002 -3.1 -94 > 135
8.7 Noise shaper of DAC
The 3rd-order noise shaper operates at either 128fs or 64fs (in the 192 kHz sampling mode), and converts the 24-bit input signal into a 5-bit signal stream. The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved.
8.8 Digital mixer
The UDA1384 has 6 digital mixers inside the interpolator (see Figure 4). The ADC signals can be mixed with the I2S-bus input signals. The mixing of the ADC signals can be selected by the bits MIX[1:0].
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UDA1384
Multichannel audio coder-decoder
MIX [1:0] from ADC ch1 ch2 ch3 ch4 DE-EMPHASIS from I 2S-bus VOLUME MUTE 1fs mixer input MIXER VOLUME MIXER MUTE
+
INTERPOLATION FILTER
DAC1
DATADA1 same as above DAC2
same as above DATADA2 same as above
DAC3
DAC4
same as above DATADA3
DAC5
same as above DIS [1:0]
mgw786
DAC6
ICS [1:0]
Fig 4. Block diagram of DAC mixer
8.9 Audio digital-to-analog converters
The audio digital-to-analog front-end of the UDA1384 consists of 6-channel differential SDACs: an SDAC is a multi-bit DAC based upon switched resistors. To minimize data dependent modulation effects, a Dynamic Element Matching (DEM) algorithm scrambler circuit and DC current compensation circuit are implemented with the SDAC.
8.10 Power-on reset
The UDA1384 has an internal power-on reset circuit which initializes the device (see Figure 5). All the digital sound processing features and the system controlling features are set to their default values in the L3-bus and the I2C-bus modes. The reset time (see Figure 6) is determined by an external capacitor which is connected between pin Vref and ground. The reset time should be at least 250 s for Vref < 1.25 V. When VDDA(AD) is switched off, the device will be reset again for Vref < 0.75 V. During the reset time, the system clock should be running.
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UDA1384
Multichannel audio coder-decoder
3.3 VDDD (V)
0 t VDDA(AD) 9 k Vref C1 > 10 F 9 k
mgu585
3.3 VDDA(AD) (V)
RESET CIRCUIT
0
t
Vref (V) 1.65 1.25 0.75 0 >250 s trst t
mgu586
Fig 5. Power-on reset circuit
Fig 6. Power-on reset timing
8.11 Audio digital interface
The following audio formats can be selected via the microcontroller interface:
* * * *
I2S-bus format with data word length of up to 24 bits MSB-justified format with data word length of up to 24 bits LSB-justified format with data word length of 16 bits, 20 bits or 24 bits Multichannel formats with data word length of 20 bits or 24 bits. The used data lines are DATAAD1 and DATADA1 and the sampling frequency must be below 50 kHz
The formats are illustrated in Figure 7 and Figure 8.
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Product data sheet Rev. 02 -- 17 January 2005
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WS 1 BCK 2 3
LEFT >=8 1 2 3
RIGHT >=8
DATA
MSB
B2
MSB
B2
MSB
I2S-BUS FORMAT
WS 1 BCK 2
LEFT 3 >=8 1 2
RIGHT 3 >=8
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT 16 15 2 1
RIGHT 16 15 2 1
BCK
DATA
MSB
B2
B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 20 19 18 17 16 15 2 1
RIGHT 20 19 18 17 16 15 2 1
BCK
Multichannel audio coder-decoder
DATA
MSB
B2
B3
B4
B5
B6
B19 LSB LSB-JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
WS 24 BCK 23 22 21
LEFT 20 19 18 17 16 15 2 1 24 23 22 21
RIGHT 20 19 18 17 16 15 2 1
UDA1384
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB LSB-JUSTIFIED FORMAT 24 BITS
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
mgt020
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Fig 7. Formats of input and output data (single-channel)
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Product data sheet Rev. 02 -- 17 January 2005
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Philips Semiconductors
WS 1 BCK 2 21 22 41 42 61 1 2 21 22 41 42 61
DATA
MSB CH1
LSB
MSB CH3
LSB
MSB CH5
LSB
MSB CH2
LSB
MSB CH4
LSB
MSB CH6
LSB
MULTICHANNEL FORMAT 20 BITS
WS 1 BCK 2 25 26 49 50 73 1 2 25 26 49 50 73
DATA
MSB CH1
LSB
MSB CH3
LSB
MSB CH5
LSB
MSB CH2
LSB
MSB CH4
LSB
MSB CH6
LSB
MULTICHANNEL FORMAT 24 BITS (1)
WS 1 BCK 25 26 49 50 73 74 97 1 25 26 49 50 73 74 97
DATA
MSB CH1
LSB MSB CH3
LSB MSB CH5
LSB
MSB CH2
LSB MSB CH4
LSB MSB CH6
LSB
Multichannel audio coder-decoder
MULTICHANNEL FORMAT 24 BITS (2)
mgu588
UDA1384
(1) Format 1. (2) Format 2.
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Fig 8. Formats of input and output data (multichannel)
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
8.12 Voice digital interface
The following voice formats can be selected via the microcontroller interface:
* I2S-bus format with data word length of up to 20 bits. The left and the right channels
contain the same data.
* Mono channel format with data word length of up to 20 bits.
The formats are illustrated in Figure 9.
WS 1 BCK 2 3
LEFT 8 1 2 3
RIGHT 8
DATA
MSB
B2
MSB I2S-BUS FORMAT
B2
MSB
WS 1 BCK 2 3 8 1 2
DATA
MSB
B2 MONO CHANNEL FORMAT
MSB
B2
mgu587
Fig 9. Voice digital interface formats
8.13 DSD mode
The UDA1384 can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The configuration of the UDA1384 in the DSD mode is shown in Figure 10.
left channel 2.8224 MHz DSD right channel
DATADA2 DECIMATION FILTER DATADA3 INTERPOLATION NOISE SHAPING
DAC
- + - +
VOUT1N VOUT1P VOUT2N VOUT2P right channel left channel analog output
DAC
5.6448 MHz 88.2 kHz
BCKAD WSAD I2S-BUS INTERFACE 1 I2S-BUS INTERFACE 2
mgu584
DATAAD1
DATADA1
WSDA BCKDA
SYSCLK
88.2 kHz PCM data I2S-bus (left and right)
88.2 kHz 22.5792 MHz 5.6448 MHz
Fig 10. DSD mode
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Multichannel audio coder-decoder
8.14 Microcontroller interface mode
The microcontroller interface mode can be selected as shown in Table 11:
* L3-bus mode when pin I2C_L3 = LOW * I2C-bus mode when pin I2C_L3 = HIGH
Table 11: Pin Pin function in the L3-bus or I2C-bus mode Level on pin I2C_L3 LOW L3-bus mode signal MCCLK MCDATA MCMODE Table 12: LOW HIGH QMUTE Function no muting muting L3CLOCK L3DATA L3MODE HIGH I2C-bus mode signal SCL SDA QMUTE
Signal QMUTE
All the features are accessible with the I2C-bus interface protocol as with the L3-bus interface protocol. The detailed description of the device operation in the L3-bus mode and I2C-bus mode is given in Section 9 and Section 10, respectively.
9. L3-bus interface
9.1 General
The UDA1384 has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The exchange of data and control information between the microcontroller and the UDA1384 is LSB first and is accomplished through a serial hardware L3-bus interface comprising the following pins:
* MCCLK: clock line with signal L3CLOCK * MCDATA: data line with signal L3DATA * MCMODE: mode line with signal L3MODE
The L3-bus format has two modes of operation:
* Address mode * Data transfer mode
The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by signal L3MODE = LOW and a burst of 8 pulses for signal L3CLOCK, accompanied by 8 bits (see Figure 11).
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Multichannel audio coder-decoder
The data transfer mode is characterized by signal L3MODE = HIGH and is used to transfer one or more bytes representing a register address, instruction or data. Basically, two types of data transfers can be defined:
* Write action: data transfer to the device * Read action: data transfer from the device. 9.2 Device addressing
The device address consists of one byte with:
* Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see
Table 13)
* Address bits 2 to 7 representing a 6-bit device address. The address of the UDA1384
is 01 0100 (bits 2 to 7).
Table 13: DOM Bit 1 0 0 1 1 Bit 0 0 1 0 1 not used not used write data or prepare read read data Selection of data transfer Transfer
9.3 Register addressing
After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. Basically, there are 3 methods for register addressing: 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Figure 11). 2. Addressing for prepare read: bit is logic 1, indicating that data will be read from the register (see Figure 12). 3. Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid (see Figure 12).
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Product data sheet Rev. 02 -- 17 January 2005
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L3CLOCK
L3MODE device address L3DATA 0 1 0
mbl567
register address
data byte 1
data byte 2
DOM bits
write
Fig 11. Data write mode
L3CLOCK
Multichannel audio coder-decoder
L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 valid/invalid sent by the device
mbl565
requesting register address
data byte 1
data byte 2
UDA1384
17 of 55
Fig 12. Data read mode
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
9.4 Data write mode
The data write mode is explained in the signal diagram of Figure 11. For writing data to a device, 4 bytes must be sent (see Table 14): 1. Byte 1 starting with `01' for signalling the write action to the device, followed by the device address `01 0100' 2. Byte 2 starting with a `0' for signalling the write action, followed by 7 bits indicating the destination address in binary format with bit A6 being the MSB and bit A0 being the LSB 3. Byte 3 with bit D15 being the MSB 4. Byte 4 with bit D0 being the LSB It should be noted that each time a new destination register address needs to be written, the device address must be sent again.
Table 14: Byte 1 2 3 4 L3-bus write data Action device address register address data byte 1 data byte 2 First in time Bit 0 0 0 D15 D7 Bit 1 1 A6 D14 D6 Bit 2 0 A5 D13 D5 Bit 3 1 A4 D12 D4 Bit 4 0 A3 D11 D3 Bit 5 1 A2 D10 D2 Latest in time Bit 6 0 A1 D9 D1 Bit 7 0 A0 D8 D0
L3-bus mode address data transfer data transfer data transfer
9.5 Data read mode
To read data from the device, a prepare read must first be done and then data read. The data read mode is explained in the signal diagram of Figure 12. For reading data from a device, the following 6 bytes are involved (see Table 15): 1. Byte 1 with the device address, including `01' for signalling the write action to the device. 2. Byte 2 is sent with the register address from which data needs to be read. This byte starts with a `1', which indicates that there will be a read action from the register, followed by 7 bits for the destination address in binary format, with bit A6 being the MSB and bit A0 being the LSB. 3. Byte 3 with the device address, including `11' is sent to the device. The `11' indicates that the device must write data to the microcontroller. 4. Byte 4 sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1). 5. Byte 5 sent by the device to the bus, with the data information in binary format, with bit D15 being the MSB. 6. Byte 6 sent by the device to the bus, with the data information in binary format, with bit D0 being the LSB.
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UDA1384
Multichannel audio coder-decoder
L3-bus read data Action device address register address device address register address data byte 1 data byte 2 First in time Bit 0 0 1 1 0 or 1 D15 D7 Bit 1 1 A6 1 A6 D14 D6 Bit 2 0 A5 0 A5 D13 D5 Bit 3 1 A4 1 A4 D12 D4 Bit 4 0 A3 0 A3 D11 D3 Latest in time Bit 5 1 A2 1 A2 D10 D2 Bit 6 0 A1 0 A1 D9 D1 Bit 7 0 A0 0 A0 D8 D0
Table 15: Byte 1 2 3 4 5 6
L3-bus mode address data transfer address data transfer data transfer data transfer
10. I2C-bus interface
10.1 General
The UDA1384 has an I2C-bus microcontroller interface. All the features are accessible with the I2C-bus interface protocol. In the I2C-bus mode, the DAC mute function is accessible via pin MCMODE with signal QMUTE. The exchange of data and control information between the microcontroller and the UDA1384 is accomplished through a serial hardware interface comprising the following pins as shown in Table 11:
* MCCLK: clock line with signal SCL * MCDATA: data line with signal SDA 10.2 Characteristics of the I2C-bus
The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the supply voltage VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC, the recommendation for this type of bus from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 pF and 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy.
10.3 Bit transfer
One data bit is transferred during each clock pulse (see Figure 13). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run on this high frequency, all the inputs and outputs connected to this bus must be designed for this high-speed I2C-bus according to the Philips specification.
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UDA1384
Multichannel audio coder-decoder
SDA
SCL data line stable; data valid change of data allowed
mbc621
Fig 13. Bit transfer on the I2C-bus
10.4 Byte transfer
Each byte (8 bits) is transferred with the MSB first (see Table 16).
Table 16: MSB 7 6 5 4 3 2 1 Byte transfer LSB 0
Bit number
10.5 Data transfer
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves.
10.6 Start and stop conditions
Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S); see Figure 14. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P).
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 14. START and STOP conditions on the I2C-bus
10.7 Acknowledgment
The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Figure 15). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse.
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UDA1384
Multichannel audio coder-decoder
A slave receiver which is addressed, must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 15. Acknowledge on the I2C-bus
10.8 Device address
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with byte 1 transmitted after the start procedure. The UDA1384 acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1384 device address is shown in Table 17.
Table 17: A6 0 I2C-bus device address of UDA1384 R/W A4 1 A3 1 A2 0 A1 0 A0 0 0/1 0 A5
Device address
10.9 Register address
The register addresses in the I2C-bus mode are the same as in the L3-bus mode. The register addresses are defined in Section 11.
10.10 Write and read data
The I2C-bus configurations for a write and read cycle are shown in Table 18 and Table 19, respectively.
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The write cycle is used to write groups of two bytes to the internal registers for the settings. It is also possible to read the registers for the device status information.
10.11 Write cycle
The I2C-bus configuration for a write cycle is shown in Table 18. The write cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a pair of two bytes. The format of the write cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `0011 000' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1384. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1384 must start. 5. The UDA1384 acknowledges this register address (A). 6. The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the UDA1384. 7. If repeated groups of 2 bytes data are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the UDA1384. 8. Finally, the UDA1384 frees the I2C-bus and the microcontroller can generate a stop condition (P).
Table 18: Master transmitter writes to UDA1384 registers in the I2C-bus mode R/W A Register address ADDR Data 1 Data 2
[1]
Device address S
Data n LS2 A MSn
[1]
0011 000 0
A MS1 A LS1 A MS2 A
A LSn A
P
A = acknowledge from UDA1384
[1] Auto increment of register address.
10.12 Read cycle
The read cycle is used to read the data values from the internal registers. The I2C-bus configuration for a read cycle is shown in Table 19. The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `0011 000' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1384. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the reading of the register content of the UDA1384 must start. 5. The UDA1384 acknowledges this register address. 6. Then the microcontroller generates a repeated start (Sr).
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UDA1384
Multichannel audio coder-decoder
7. Then the microcontroller generates the device address `0011 000' again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1384. 8. The UDA1384 sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller (master). 9. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the microcontroller. 10.The microcontroller stops this cycle by generating a Negative Acknowledge (NA). 11.Finally, the UDA1384 frees the I2C-bus and the microcontroller can generate a stop condition (P).
Table 19: Master transmitter reads from the UDA1384 registers in the I2C-bus mode R/W A Register address ADDR A Device address R/W Data 1 MS1 A LS1 A Data 2 [1] MS2 A LS2 A Data n [1] MSn A LSn NA P
Device address S
0011 000 0
Sr 0011 000 1 A
A = acknowledge from UDA1384
[1] Auto increment of register address.
A = acknowledge from master
11. Register mapping
In this chapter the register addressing and mapping of the microcontroller interface of the UDA1384 is given. In Table 20 an overview of the register mapping is given. In Table 21 the actual register mapping is given and the register definitions are explained in Section 11.3 to Section 11.14.
11.1 Address mapping
Table 20: Address 00h 01h 02h 0Fh 10h 11h 12h 13h 14h 15h
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Overview of register mapping Function system audio ADC and DAC subsystem voice ADC system status outputs DAC channel and feature selection DAC feature control DAC channel 1 DAC channel 2 DAC channel 3 DAC channel 4
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System settings
Status (read out registers) Interpolator settings
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UDA1384
Multichannel audio coder-decoder
Overview of register mapping ...continued Function DAC channel 5 DAC channel 6 DAC mixing channel 1 DAC mixing channel 2 DAC mixing channel 3 DAC mixing channel 4 DAC mixing channel 5 DAC mixing channel 6 audio ADC input amplifier gain voice ADC input amplifier gain supplemental settings 1 supplemental settings 2
Table 20: Address 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 20h 21h 30h 31h
ADC input amplifier gain settings
Supplemental settings
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11.2 Register mapping
Table 21: Add 00h 01h 02h UDA1384 register mapping [1] D15 D14 D13 VFS0 0 PAA 0 0 MC5 0 DE2 0 DE2 0 DE2 0 DE2 0 DE2 0 DE2 0 DE2 0 0 D12 VCE 1 MTB 0 0 MC4 0 DE1 0 DE1 0 DE1 0 DE1 0 DE1 0 DE1 0 DE1 0 0 D11 VAP 0 MTA 0 0 MC3 0 DE0 0 DE0 0 DE0 0 DE0 0 DE0 0 DE0 0 DE0 0 0 D10 DSD 0 AIF2 0 0 MC2 0 PD 0 PD 0 PD 0 PD 0 PD 0 PD 0 PD 0 PD 0 D9 SC1 0 AIF1 0 0 MC1 0 MT 0 MT 0 MT 0 MT 0 MT 0 MT 0 MT 0 MT 0 D8 SC0 0 AIF0 0 0 MC0 0 QM 0 QM 0 QM 0 QM 0 QM 0 QM 0 QM 0 QM 0 D7 OP1 0 DAG 0 0 SEL1 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 D6 OP0 0 FIL 0 1 SEL0 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 D5 FS1 0 DVD 0 1 VS CS5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 D4 FS0 1 DIS1 0 VH1 0 AS1 CS4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 D3 ACE 1 DIS0 0 VH0 1 AS0 CS3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 D2 ADP 0 DIF2 0 PVA 0 DS2 CS2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 D1 DCE 1 DIF1 0 MTV 0 DS1 CS1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 D0 DAP 0 DIF0 0 VIF 0 DS0 CS0 0 VC0 0 VC0 0 VC0 0 VC0 Function system
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System settings RST [2] VFS1 audio ADC and DAC DC subsystem 1 voice ADC system 0 Status (read out only) 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h status outputs DAC channel and feature selection DAC feature control DAC channel 1 DAC channel 2 DAC channel 3 DAC channel 4 DAC channel 5 DAC channel 6 DAC mixing channel 1 MIX1 0 ICS1 0 ICS1 0 0 ICS1 0 0 ICS1 0 0 ICS1 0 MIX0 0 ICS0 0 ICS0 0 0 ICS0 0 0 ICS0 0 0 ICS0 0 Interpolator settings 0 PAB 0 0
BCK1 BCK0 WSM
Multichannel audio coder-decoder
0 VC0 0 VC0 0 VC0 0 VC0 0
UDA1384
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Table 21: Add 19h 1Ah 1Bh 1Ch 1Dh UDA1384 register mapping [1] ...continued D15 0 ICS1 0 0 ICS1 0 0 0 0 0 D14 0 ICS0 0 0 ICS0 0 0 0 0 0 D13 0 0 0 0 0 0 0 0 D12 0 0 0 0 0 0 0 0 D11 0 0 0 0 0 IB3 0 0 0 D10 PD 0 PD 0 PD 0 PD 0 PD 0 IB2 0 0 0 D9 MT 0 MT 0 MT 0 MT 0 MT 0 IB1 0 0 0 D8 QM 0 QM 0 QM 0 QM 0 QM 0 IB0 0 0 0 D7 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 0 0 PDT 0 0 D6 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 0 0 0 0 D5 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 0 0 0 0 D4 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 0 IV4 0 0 0 D3 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 IA3 0 IV3 0 0 0 D2 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 IA2 0 IV2 0 0 0 D1 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 IA1 0 IV1 0 0 0 D0 VC0 0 VC0 0 VC0 0 VC0 0 VC0 0 IA0 0 IV0 0 0 0
Product data sheet Rev. 02 -- 17 January 2005
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Philips Semiconductors
Function DAC mixing channel 2 DAC mixing channel 3 DAC mixing channel 4 DAC mixing channel 5 DAC mixing channel 6
ADC input amplifier gain settings 20h 21h ADC 1 and ADC 2 input amplifier gain voice ADC input amplifier gain
Supplemental settings 30h 31h supplemental settings 1 supplemental settings 2
DITH2 DITH1 DITH0 -
VMTP PDLNA
Multichannel audio coder-decoder
[1] [2]
When writing new settings via the L3-bus interface, the default values should always be set to warrant correct operation. Read access to the DAC features register 11h will not return valid data. When bit RST is set to logic 1, the default values are set to all the registers as shown in Table 21. When start-up, all the registers in 00h are initialized as the default values and the mute control bits MTA, MTB, MTV, MT and QM are set to logic 1. All other registers have non fixed values.
UDA1384
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Multichannel audio coder-decoder
11.3 System settings
Table 22: Bit Symbol Reset Access Bit Symbol Reset Access Table 23: Bit 15 7 OP1 0 6 OP0 0 5 FS1 0 System register (address 00h) bit allocation 15 RST 14 VFS1 0 13 VFS0 0 12 VCE 1 4 FS0 1 11 VAP 0 3 ACE 1 10 DSD 0 2 ADP 0 9 SC1 0 1 DCE 1 8 SC0 0 0 DAP 0
read and write
read and write Description of system register bits Symbol RST Description Reset. Bit RST initializes the L3-bus registers with the default settings. 1 = Reset to default settings 0 = No reset
14 to 13 12
VFS[1:0] VCE
Voice ADC sampling frequency. A 2-bit value to select the voice ADC sampling frequency. Default 00. See Table 24. Voice ADC clock enable. 1 = clock enabled (default) 0 = clock disabled
11
VAP
Voice ADC power control. Bit VAP is to reduce the power consumption of the voice ADC. 1 = state is power-on 0 = state is power-off (default)
10
DSD
DSD mode selection. Bit DSD selects the DSD mode. 1 = DSD mode 0 = normal mode (default)
9 to 8
SC[1:0]
System clock frequency. A 2-bit value to select the used external clock frequency. 128fs system clock for the DAC can be used by setting bit DVD = 1. Default 00. See Table 25. Operating mode selection. A 2-bit value to select the operation mode of the audio ADC and DAC. Default 00. See Table 26. Sampling frequency. A 2-bit value to select the sampling frequency of the audio ADC and DAC in the WS mode. Default 01. See Table 27. ADC clock enable. Bit ACE enables the audio ADC clock 1 = clock enabled (default) 0 = clock disabled
7 to 6 5 to 4 3
OP[1:0] FS[1:0] ACE
2
ADP
ADC power control. Bit ADP is to reduce the power consumption of the audio ADC. 1 = state is power-on 0 = state is power-off (default)
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Description of system register bits ...continued Symbol DCE Description DAC clock enable. Bit DCE enables the DAC clock. 1 = clock enabled (default) 0 = clock disabled
Table 23: Bit 1
0
DAP
DAC power control. Bit DAP is to reduce the power consumption of the DAC. 1 = state is power-on 0 = state is power-off (default)
Table 24: VFS1 0 0 1 1 Table 25: SC1 0 0 1 1 Table 26: OP1 0 0 1 1 Table 27: FS1 0 0 1 1 0 1 0 1
Voice ADC sampling frequency bits VFS0 0 1 0 1 Function 6.25 kHz to 12.5 kHz (default) 12.5 kHz to 25 kHz 25 kHz to 50 kHz reserved
System clock frequency bits SC0 0 1 0 1 ADC 256fs 384fs 512fs 768fs DAC Bit DVD = 0 256fs 384fs 512fs 768fs Bit DVD = 1 128fs 192fs 256fs 384fs default Remark
Operating mode bits ADC mode SYSCLK (256fs, 384fs, 512fs or 768fs) SYSCLK (256fs, 384fs, 512fs or 768fs) WSAD (1fs) WSDA (1fs) DAC mode SYSCLK (128fs, 256fs, 384fs, 512fs or 768fs) WSDA (1fs) SYSCLK (128fs, 256fs, 384fs, 512fs or 768fs) WSDA (1fs) Remark default
OP0
Audio ADC and DAC sampling frequency bits FS0 0 1 0 1 Function 12.5 kHz to 25 kHz 25 kHz to 50 kHz (default) 50 kHz to 100 kHz 100 kHz to 200 kHz
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11.4 Audio ADC and DAC subsystem settings
Table 28: Bit Symbol Reset Access Bit Symbol Reset Access Table 29: Bit 15 7 DAG 0 6 FIL 0 5 DVD 0 Audio ADC and DAC subsystem register (address 01h) bit allocation 15 DC 1 14 PAB 0 13 PAA 0 12 MTB 0 4 DIS1 0 11 MTA 0 3 DIS0 0 10 AIF2 0 2 DIF2 0 9 AIF1 0 1 DIF1 0 8 AIF0 0 0 DIF0 0
read and write
read and write Description of the audio ADC and DAC subsystem register bit Symbol DC Description ADC DC-filter. Bit DC enables the digital DC-filter of the ADC. 1 = DC-filtering is active (default) 0 = no DC-filtering
14
PAB
Polarity ADC 2 control. Bit PAB controls the ADC 2 polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default)
13
PAA
Polarity ADC 1 control. Bit PAA controls the ADC 1 polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default)
12
MTB
Mute ADC 2. Bit MTB enables the digital mute of ADC 2. 1 = ADC 2 is soft muted 0 = ADC 2 is not muted (default)
11
MTA
Mute ADC 1. Bit MTA enables the digital mute of ADC 1. 1 = ADC 1 is soft muted 0 = ADC 1 is not muted (default)
10 to 8 7
AIF[2:0] DAG
ADC output data interface format. A 3-bit value to select the used data format to the I2S-bus ADC output interface. Default 000. See Table 30. DAC gain switch. Bit DAG selects the DAC gain. 1 = gain = 6 dB 0 = gain = 0 dB (default)
6
FIL
Filter selection. Bit FIL selects the interpolation filter characteristics. 1 = slow roll-off 0 = sharp roll-off (default)
5
DVD
192 kHz sampling mode selection. Bit DVD selects the oversampling rate of the noise shaper. 1 = 64fs rate; used for 192 kHz and 176.4 kHz sampling frequencies 0 = 128fs rate (default)
4 to 3 2 to 0
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DIS[1:0] DIF[2:0]
Data interface selection. A 2-bit value to select the data interface connection. Default 00. See Table 31. DAC input data interface format. A 3-bit value to select the used data format to the I2S-bus DAC input interface. Default 000. See Table 30.
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Multichannel audio coder-decoder
Data interface format bits AIF1 DIF1 0 0 1 1 0 0 1 1 AIF0 DIF0 0 1 0 1 0 1 0 1 I2S-bus format (default) LSB-justified format, 16 bits LSB-justified format, 20 bits LSB-justified format, 24 bits MSB-justified format multichannel format, 20 bits multichannel format, 24 bits (format 1) multichannel format, 24 bits (format 2) Function
Table 30: AIF2 DIF2 0 0 0 0 1 1 1 1 Table 31: DIS1 0 0 1 1
Data interface selection bits DIS0 0 1 0 1 Input to DAC DATADA1 to DAC channel 1 and 2, DATADA2 to DAC channel 3 and 4, and DATADA3 to DAC channel 5 and 6 (default) DATADA1 to DAC channels 1 to 6 DATADA2 to DAC channels 1 to 6 DATADA3 to DAC channels 1 to 6
11.5 Voice ADC system settings
Table 32: Bit Symbol Reset Access Bit Symbol Reset Access Table 33: Bit 15 to 8 7 to 6 7 BCK1 0 6 BCK0 1 5 WSM 1 Voice ADC system register (address 02h) bit allocation 15 14 13 12 4 VH1 0 11 3 VH0 1 10 2 PVA 0 9 1 MTV 0 8 0 VIF 0
read and write
read and write Description of the voice ADC system register bits Symbol BCK[1:0] Description default 0000 0000 BCK frequency of voice ADC. A 2-bit value to select the BCK frequency of the voice ADC in the WSV-out mode. Default 01. See Table 34. WSV mode selection. Bit WSM selects the WSV mode of the voice ADC 1 = WSV-in mode (default) 0 = WSV-out mode
5
WSM
4 to 3
VH[1:0]
Voice ADC high-pass filter setting. A 2-bit value to enable the high-pass filter of the voice ADC. Default 01. See Table 35.
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Description of the voice ADC system register bits ...continued Symbol PVA Description Polarity voice ADC control. Bit PVA controls the voice ADC polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default)
Table 33: Bit 2
1
MTV
Mute voice ADC. Bit MTV enables the digital mute of the voice ADC. 1 = ADC 1 is soft muted 0 = ADC 1 is not muted (default)
0
VIF
Voice ADC interface format. Bit VIF selects the data interface format of the voice ADC. 1 = mono-channel format 0 = I2S-bus format (default)
Table 34: BCK1 0 0 1 1 Table 35: VH1 0 0 1 1
BCK frequency of voice ADC bits BCK0 0 1 0 1 Function 32fs 64fs (default) 128fs 256fs
Voice ADC high-pass filter setting bits VH0 0 1 0 1 Function high-pass filter off fc = 0.00008fs (default) fc = 0.0125fs fc = 0.025fs
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11.6 Status output register
Table 36: Bit Symbol Reset Access Bit Symbol Reset Access Table 37: Bit 15 to 6 5 VS 7 6 5 VS 4 AS1 read only Description of status output register bits Symbol Description not used Voice ADC status. Bit VS indicates the hard mute status of the voice ADC. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 4 AS1 ADC 2 status. Bit AS1 indicates the hard mute status of ADC 2. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 3 AS0 ADC 1 status. Bit AS0 indicates the hard mute status of ADC 1. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 2 DS2 DAC channel 5 and 6 status. Bit DS2 indicates the hard mute status of DAC channel 5 and 6. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 1 DS1 DAC channel 3 and 4 status. Bit DS1 indicates the hard mute status of DAC channel 3 and 4. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled 0 DS0 DAC channel 1 and 2 status. Bit DS0 indicates the hard mute status of DAC channel 1 and 2. 1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled Status output register (address 0Fh) bit allocation 15 14 13 12 read only 3 AS0 2 DS2 1 DS1 0 DS0 11 10 9 8 -
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Multichannel audio coder-decoder
11.7 DAC channel selection
Table 38: Bit Symbol Reset Access Bit Symbol Reset Access Table 39: Bit 15 to 14 13 to 8 7 SEL1 0 6 SEL0 0 5 CS5 0 DAC channel select register (address 10h) bit allocation 15 MIX1 0 14 MIX0 0 13 MC5 0 12 MC4 0 4 CS4 0 11 MC3 0 3 CS3 0 10 MC2 0 2 CS2 0 9 MC1 0 1 CS1 0 8 MC0 0 0 CS0 0
read and write
read and write Description of DAC channel select register bits Symbol MIX[1:0] MC[5:0] Description DAC mixer setting. A 2-bit value to enable the DAC mixer. Default 00. See Table 40. DAC mixing channel selection. A group of 6 enable bits to make DAC mixing channels ready for receiving feature settings through register address 11h. Only selected registers accept new settings. Default 00 0000 (no channel ready). See Table 41. Feature selection. A 2-bit value to select the features to be set through register address 11h. When the feature settings are written, only selected feature settings are changed and non selected features are kept unchanged. Default 00. See Table 42. DAC channel selection. A group of 6 enable bits to make DAC channel ready for receiving feature settings through register address 11h. Default 00 0000 (no channel ready). See Table 41.
7 and 6
SEL[1:0]
5 to 0
CS[5:0]
Table 40: MIX1 0 0 1 1 Table 41: MC5 CS5 0 0 : 0 : 1
DAC mixer setting bits MIX0 0 1 0 1 Function no mixing (default) no mixing mixing ADC 1 mixing ADC 2
DAC channel and mixing channel selection bits MC3 CS3 0 0 : 1 : 1 MC2 CS2 0 0 : 0 : 1 MC1 CS1 0 0 : 1 : 1 MC0 Function CS0 0 1 : 0 : 1 all channels selected channel 2 and channel 4 selected no channel ready (default) channel 1 selected
MC4 CS4 0 0 : 0 : 1
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Multichannel audio coder-decoder
Feature selection bits SEL0 0 1 0 1 Function all features (default) volume mute and quick mute de-emphasis, polarity and input channel selection
Table 42: SEL1 0 0 1 1
11.8 DAC features settings
Table 43: Bit Symbol Reset Access Bit Symbol Reset Access Table 44: Bit 15 to 14 7 VC7 0 6 VC6 0 5 VC5 0 DAC features register (address 11h) bit allocation 15 ICS1 0 14 ICS0 0 13 DE2 0 12 DE1 0 4 VC4 0 11 DE0 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
read and write
read and write Description of DAC features register bits Symbol ICS[1:0] Description Input channel selection. A 2-bit value to select the input channels. As the controlled channels are paired off, this 2-bit value must be written to each odd channel register. Default 00. See Table 45. De-emphasis setting. A 3-bit value to enable the digital de-emphasis filter. Default 000. See Table 46. Polarity DAC control. Bit PD controls the DAC polarity. 1 = polarity is inverted 0 = polarity is not-inverted (default)
13 to 11 10
DE[2:0] PD
9
MT
Muting. Bit MT enables the digital mute. All the DAC outputs are muted at start-up. It is necessary to explicitly switch off for the audio output by means of bit MT. 1 = muting (start-up) 0 = no muting (default)
8
QM
Quick mute. Bit QM sets the quick mute mode. 1 = quick mute mode 0 = soft mute mode (default)
7 to 0
VC[7:0]
Interpolator volume control. An 8-bit value to program the volume attenuation of each channel. The range is from 0 dB to -53 dB in steps of 0.25 dB, from -53 dB to -80 dB in steps of 3 dB and - dB. Default 0000 0000. See Table 47.
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Input channel selection bits ICS0 0 1 0 1 Input to DAC output left channel input data to odd channel output; right channel input data to even channel output left channel input data to odd and even channel outputs right channel input data to odd and even channel outputs left channel input data to even channel output; right channel input data to odd channel output
Table 45: ICS1 0 0 1 1
Table 46: DE2 0 0 0 0 1 1 1 1 Table 47: VC7 0 0 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 : 1
De-emphasis bits DE1 0 0 1 1 0 0 1 1 DE0 0 1 0 1 0 1 0 1 Function no de-emphasis (default) de-emphasis of 32 kHz de-emphasis of 44.1 kHz de-emphasis of 48 kHz de-emphasis of 96 kHz not used not used not used
Interpolator volume control bits VC6 0 0 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 : 1 VC5 0 0 0 0 0 0 : 0 0 0 1 1 1 1 1 1 1 1 : 1 VC4 0 0 0 0 0 0 : 1 1 1 0 0 0 0 1 1 1 1 : 1 VC3 0 0 0 0 0 0 : 0 1 1 0 0 1 1 0 0 1 1 : 1 VC2 0 0 0 0 1 1 : 1 0 1 0 1 0 1 0 1 0 1 : 1 VC1 0 0 1 1 0 0 : 0 0 0 0 0 0 0 0 0 0 0 : 1 VC0 0 1 0 1 0 1 : 0 0 0 0 0 0 0 0 0 0 0 : 1 Volume (dB) 0 (default) -0.25 -0.50 -0.75 -1.00 -1.25 : -53 -56 -59 -62 -65 -68 -71 -74 -77 -80 - : -
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Multichannel audio coder-decoder
11.9 DAC channel 1 to channel 6 settings
All the DAC features which are written in register 11h are copied into the odd channel registers.
Table 48: Bit Symbol Reset Access Bit Symbol Reset Access 7 VC7 0 6 VC6 0 5 VC5 0 DAC channel 1, 3 and 5 registers (address 12h, 14h and 16h) bit allocation 15 ICS1 0 14 ICS0 0 13 DE2 0 12 DE1 0 4 VC4 0 11 DE0 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
read and write
read and write
All the DAC features which are written in register 11h are copied into the even channel registers, except the bits ICS[1:0].
Table 49: Bit Symbol Reset Access Bit Symbol Reset Access 7 VC7 0 6 VC6 0 5 VC5 0 DAC channel 2, 4 and 6 registers (address 13h, 15h and 17h) bit allocation 15 0 14 0 13 DE2 0 12 DE1 0 4 VC4 0 11 DE0 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
read and write
read and write
11.10 DAC mixing channel settings
All the DAC features which are written in register 11h are copied into the odd mixing channel registers, except the bits DE[2:0].
Table 50: Bit Symbol Reset Access Bit Symbol Reset Access 7 VC7 0 6 VC6 0 5 VC5 0 DAC mixing channel 1, 3 and 5 registers (address 18h, 1Ah and 1Ch) bit allocation 15 ICS1 0 14 ICS0 0 13 0 12 0 4 VC4 0 11 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
read and write
read and write
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Multichannel audio coder-decoder
All the DAC features which are written in register 11h are copied into the even channel registers, except the bits ICS[1:0] and DE[2:0].
Table 51: Bit Symbol Reset Access Bit Symbol Reset Access 7 VC7 0 6 VC6 0 5 VC5 0 DAC mixing channel 2, 4 and 6 registers (address 19h, 1Bh and 1Dh) bit allocation 15 0 14 0 13 0 12 0 4 VC4 0 11 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
read and write
read and write
11.11 Audio ADC 1 and ADC 2 input amplifier gain settings
Table 52: Bit Symbol Reset Access Bit Symbol Reset Access Table 53: Bit 15 to 12 11 to 8 7 to 4 3 to 0 7 0 6 0 5 0 Audio ADC input amplifier gain register (address 20h) bit allocation 15 0 14 0 13 0 12 0 4 0 11 IB3 0 3 IA3 0 10 IB2 0 2 IA2 0 9 IB1 0 1 IA1 0 8 IB0 0 0 IA0 0
read and write
read and write Description of audio ADC input amplifier gain register bits Symbol IB[3:0] IA[3:0] Description default 0000 Audio ADC 2 input amplifier gain. A 4-bit value to program the input amplifier gain in steps of 3 dB (9 settings). Default 0000. See Table 54. default 0000 Audio ADC 1 input amplifier gain. A 4-bit value to program the input amplifier gain in steps of 3 dB (9 settings). Default 0000. See Table 54.
Table 54: IA3 IB3 0 0 0 0 0 0
Audio ADC input amplifier gain bits IA2 IB2 0 0 0 0 1 1 IA1 IB1 0 0 1 1 0 0 IA0 IB0 0 1 0 1 0 1 0 (default) +3 +6 +9 +12 +15 Gain (dB)
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Multichannel audio coder-decoder
Audio ADC input amplifier gain bits ...continued IA2 IB2 1 1 0 IA1 IB1 1 1 0 IA0 IB0 0 1 0 +18 +21 +24 Gain (dB)
Table 54: IA3 IB3 0 0 1
11.12 Voice ADC gain settings
Table 55: Bit Symbol Reset Access Bit Symbol Reset Access Table 56: Bit 15 to 8 7 to 5 4 to 0 7 0 6 0 5 0 Voice ADC input amplifier gain register (address 21h) bit allocation 15 14 13 12 4 IV4 0 11 3 IV3 0 10 2 IV2 0 9 1 IV1 0 8 0 IV0 0
read and write
read and write Description of voice ADC input amplifier gain register bits Symbol IV[4:0] Description not used default 000 Voice ADC input amplifier gain. A 5-bit value to program the voice amplifier gain in steps of 1.5 dB (21 settings). Default 0 0000. See Table 57.
Table 57: IV4 0 0 0 0 0 0 : 1 1 : 1
Voice ADC input amplifier gain bits IV3 0 0 0 0 0 0 : 0 0 : 1 IV2 0 0 0 0 1 1 : 0 1 : 1 IV1 0 0 1 1 0 0 : 1 0 : 1 IV0 0 1 0 1 0 1 : 1 0 : 1 Gain (dB) 0 (default) +1.5 +3 +4.5 +6 +7.5 : +28.5 +30 not used not used
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11.13 Supplemental settings 1
Table 58: Bit Symbol Reset Access Bit Symbol Reset Access Table 59: Bit 15 to 8 7 7 PDT 0 6 0 5 0 Supplemental settings 1 register (address 30h) bit allocation 15 0 14 0 13 0 12 0 4 0 11 0 3 0 10 0 2 0 9 0 1 0 8 0 0 0
read and write
read and write Description of supplemental settings 1 register bits Symbol PDT Description default 0000 0000 Power down time. Bit PDT selects the time of the SDAC power-down sequence. 1 = 1024/fs seconds 0 = 512/fs seconds (default)
6 to 0
-
default 000 0000
11.14 Supplemental settings 2
Table 60: Bit Symbol Reset Access Bit Symbol Reset Access Table 61: Bit 15 to 7 6 to 4 3 to 2 1 7 0 6 DITH2 0 5 DITH1 0 Supplemental settings 2 register (address 31h) bit allocation 15 0 14 0 13 0 12 0 4 DITH0 0 11 0 3 0 10 0 2 0 9 0 1 VMTP 0 8 0 0 PDLNA 0
read and write
read and write Description of supplemental settings 2 register bits Symbol DITH[2:0] VMTP Description default 0000 0000 0 DAC dither control. A 3-bit value to control the dithering of the SDAC. Default 000. See Table 62. default 00 Voice mute period control. Bit VMPT selects the voice ADC mute period at power-up. 1 = mute for 1024 samples (1024/fs) 0 = mute for 2048 samples (2048/fs; default)
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Description of supplemental settings 2 register bits ...continued Symbol PDLNA Description Power-down voice LNA. Bit PDLNA is to power-down the voice ADC LNA. It should be noted that disabling the LNA requires a recovery time defined by the external RC circuit. 1 = power-down 0 = power-on (default)
Table 61: Bit 0
Table 62: DITH2 0 0 0 0 1 1 1 1
DAC dither control bits DITH1 0 0 1 1 0 0 1 1 DITH0 0 1 0 1 0 1 0 1 Function DC dither (mid level); default reserved reserved reserved DC dither (low level) DC plus AC dither (low level) DC dither (high level) DC plus AC dither (high level)
12. Limiting values
Table 63: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Txtal(max) Tstg Tamb Vesd Parameter supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic discharge voltage HBM MM
[2] [2]
Conditions
[1]
Min -65 -20 -2000 -200
Max 4.0 150 +125 +85 +2000 +200
Unit V C C C V V
[1] [2]
All supply connections must be made to the same power supply. ESD behavior is tested in accordance with JEDEC II standard: a) Human Body Model (HBM); equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. b) Machine Model (MM); equivalent to discharging a 200 pF capacitor through a 0.75 H series inductor.
13. Thermal characteristics
Table 64: Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 85 Unit K/W
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14. Static characteristics
Table 65: Characteristics VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 C; RL = 22 k; all voltages referenced to ground (pins VSS); unless otherwise specified. Symbol Supplies VDDA(AD) VDDA(DA) VDDD IDDA(AD) IDDA(DA) IDDD ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current digital supply current fADC = 48 kHz fADC = 96 kHz fDAC = 48 kHz fDAC = 96 kHz fADC = fDAC = 48 kHz; fVOICE = 48 kHz fADC = fDAC = 96 kHz; fVOICE = 48 kHz IDDD(pd) digital supply current in Power down-mode audio and voice ADCs power-down DAC power-down Digital input pins (5 V tolerant TTL compatible) VIH VIL ILI Ci VOH VOL HIGH-level input voltage LOW-level input voltage input leakage current input capacitance HIGH-level output voltage LOW-level output voltage reference voltage on pin Vref positive reference voltage of ADC negative reference voltage of ADC output resistance on pin Vref input resistance of audio ADC IOH = -2 mA IOL = 2 mA 2.0 0.85VDDD 0.8 1 10 0.4 V V A pF V V
[1]
Parameter
Conditions
Min 2.7 2.7 2.7 -
Typ 3.3 3.3 3.3 30 31 20 32 31 55 18 14
Max 3.6 3.6 3.6 -
Unit V V V mA mA mA mA mA mA mA mA
[1]
[1]
Digital output pins
Analog-to-digital converter Vref VADCP VADCN Ro Ri(ADC) with respect to VSSA(AD) 0.45VDDA(AD) 0.0 0.5VDDA(AD) VDDA(AD) 0.0 5 10 0.55VDDA(AD) V 0.0 V V k k
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Multichannel audio coder-decoder
Table 65: Characteristics ...continued VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 C; RL = 22 k; all voltages referenced to ground (pins VSS); unless otherwise specified. Symbol Ri(VADC) Parameter input resistance of voice ADC load resistance output resistance
All supply connections must be made to the same power supply unit.
Conditions
Min -
Typ 5
Max -
Unit k
Digital-to-analog converter RL Ro
[1]
4 -
1
-
k k
15. Dynamic characteristics
Table 66: Characteristics VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; fi = 1 kHz; Tamb = 25 C; RL = 22 k; sampling frequency fs = 48 kHz; all voltages referenced to ground (pins VSS); unless otherwise specified. Symbol D0 Parameter digital output level Conditions at 0 dB setting; 900 mV input at 3 dB setting; 637 mV input at 6 dB setting; 451 mV input at 9 dB setting; 319 mV input at 12 dB setting; 226 mV input at 15 dB setting; 160 mV input at 18 dB setting; 113 mV input at 21 dB setting; 80 mV input at 24 dB setting; 57 mV input Vi input voltage unbalance between channels
[1] [2] [2] [2] [2] [2] [2] [2] [2] [2]
Min -2.5 -
Typ -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 0.1
Max -0.7 -
Unit dB dB dB dB dB dB dB dB dB dB
Audio analog-to-digital converter
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Multichannel audio coder-decoder
Table 66: Characteristics ...continued VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; fi = 1 kHz; Tamb = 25 C; RL = 22 k; sampling frequency fs = 48 kHz; all voltages referenced to ground (pins VSS); unless otherwise specified. Symbol Parameter Conditions Min Typ -88 -88 -88 -88 -88 -87 -85 -83 -82 Max -82 Unit dB dB dB dB dB dB dB dB dB (THD + N)/S total harmonic normal mode; at -1 dBFS distortion-plus-noise to signal ratio at 0 dB setting at 3 dB setting at 6 dB setting at 9 dB setting at 12 dB setting at 15 dB setting at 18 dB setting at 21 dB setting at 24 dB setting normal mode; at -60 dBFS; A-weighted at 0 dB setting at 3 dB setting at 6 dB setting at 9 dB setting at 12 dB setting at 15 dB setting at 18 dB setting at 21 dB setting at 24 dB setting S/N cs Vi(rms) signal-to-noise ratio channel separation input voltage (RMS value) at 0 dBFS digital output; 2.2 k source impedance code = 0; A-weighted 89 -37 -37 -37 -37 -37 -37 -35 -32 -30 98 100 50.0 -78 -65 -47 87 -30 dB dB dB dB dB dB dB dB dB dB dB mV dB dB dB dB
Voice analog-to-digital converter
(THD + N)/S total harmonic at -1 dBFS distortion-plus-noise to signal ratio at -20 dBFS at -40 dBFS; A-weighted S/N signal-to-noise ratio code = 0; A-weighted Digital-to-analog converter Differential mode Vo(rms) Vo output voltage (RMS value) output voltage unbalance between channels at 0 dBFS digital input
1.9 100 -
2.0 < 0.1 -98 -90 -50 110 114
2.1 -93 -45 -
V dB dB dB dB dB dB
(THD + N)/S total harmonic at 0 dBFS distortion-plus-noise to signal ratio at -20 dBFS at -60 dBFS; A-weighted S/N cs
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signal-to-noise ratio channel separation
code = 0; A-weighted
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Multichannel audio coder-decoder
Table 66: Characteristics ...continued VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; fi = 1 kHz; Tamb = 25 C; RL = 22 k; sampling frequency fs = 48 kHz; all voltages referenced to ground (pins VSS); unless otherwise specified. Symbol Vo(rms) Vo Parameter output voltage (RMS value) output voltage unbalance between channels Conditions at 0 dBFS digital input Min Typ 1.0 < 0.1 -88 -85 -45 105 110 Max Unit V dB dB dB dB dB dB Single-ended mode
(THD + N)/S total harmonic at 0 dBFS distortion-plus-noise to signal ratio at -20 dBFS at -60 dBFS; A-weighted S/N cs
[1] [2]
signal-to-noise ratio channel separation
code = 0; A-weighted
The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. The input voltage to the ADC scales proportionally with the power supply voltage.
15.1 Timing
Table 67: Timing VDDD = VDDA(AD) = VDDA(AD) = 2.7 V to 3.6 V; Tamb = -20 C to +85 C; typical timing specified at sampling frequency fs = 48 kHz; unless otherwise specified. Symbol Tsys Parameter system clock cycle time Conditions fsys = 256fs fsys = 384fs fsys = 512fs fsys = 768fs tCWL tCWH I2S-bus fBCK Tcy(BCK) tBCKH tBCKL tr tf tsu(WS) th(WS) tsu(DATAI) th(DATAI) th(DATAO)
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Min
[1] [1] [1] [1]
Typ 81 54 41 27 -
Max 780 520 390 260 0.7Tsys 0.6Tsys 0.7Tsys 0.6Tsys
Unit ns ns ns ns ns ns ns ns
System clock (see Figure 16) 35 23 17 17 0.3Tsys 0.4Tsys 0.3Tsys 0.4Tsys
system clock LOW time system clock HIGH time interface audio bit clock frequency BCK cycle time bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data input set-up time data input hold time data output hold time
fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz
Serial data of audio ADC and DAC (see Figure 17)
[2]
30 30 10 10 10 10 0
-
12.8 78 20 20 -
MHz ns ns ns ns ns ns ns ns ns ns
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Multichannel audio coder-decoder
Table 67: Timing ...continued VDDD = VDDA(AD) = VDDA(AD) = 2.7 V to 3.6 V; Tamb = -20 C to +85 C; typical timing specified at sampling frequency fs = 48 kHz; unless otherwise specified. Symbol td(DATAO-BCK) td(DATAO-WS) Parameter data output to bit clock delay data output to word select delay voice bit clock frequency BCKV cycle time bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data output hold time data output to bit clock delay data output to word select delay word select to bit clock delay WSV-out mode
[2]
Conditions
Min -
Typ -
Max 30 30
Unit ns ns
Serial data of voice ADC fBCKV Tcy(BCKV) tBCKVH tBCKVL tr tf tsu(WSV) th(WSV) th(DATAV) td(DATAV-BCKV) td(DATAV-WSV) td(WSV-BCKV) 50 50 10 10 0 -30 6.4 156 20 20 30 30 +30 MHz ns ns ns ns ns ns ns ns ns ns ns
L3-bus interface (see Figure 18 and Figure 19) L3CLOCK timing fcy(CLK)L3 Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tstp(L3) L3DATA timing tsu(L3)DA th(L3)DA td(L3)R L3DATA set-up time in data transfer and address mode L3DATA hold time in data transfer and address mode L3DATA delay time for read data 190 30 0 50 ns ns ns L3CLOCK frequency L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode L3MODE stop time in data transfer mode 500 250 250 190 190 190 190 190 2000 kHz ns ns ns ns ns ns ns ns
L3MODE timing
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Table 67: Timing ...continued VDDD = VDDA(AD) = VDDA(AD) = 2.7 V to 3.6 V; Tamb = -20 C to +85 C; typical timing specified at sampling frequency fs = 48 kHz; unless otherwise specified. Symbol tdis(L3)R Parameter L3DATA disable time for read data Conditions Min 0 Typ Max 50 Unit ns
I2C-bus interface timing (see Figure 20) SCL timing fSCL tLOW tHIGH tr tf SDA timing tBUF tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO tSP Cb bus free time between STOP and START condition set-up time repeated START hold time START condition data set-up time data hold time set-up time STOP condition pulse width of spikes capacitive load for each bus line
The system clock should not exceed 58 MHz in any mode. The bit clock frequency should not exceed 256 times the corresponding sampling frequency. Cb is the total capacitance for each bus line. To be suppressed by the input filter.
[4]
SCL clock frequency SCL LOW time SCL HIGH time rise time SDA and SCL fall time SDA and SCL
[3] [3]
0 1.3 0.6
-
400 300 300 50 400
kHz s s ns ns s s s ns s s ns pF
20 + 0.1Cb 20 + 0.1Cb 1.3 0.6 0.6 100 0 0.6 0 -
[1] [2] [3] [4]
t CWH
t CWL Tsys
mgr984
Fig 16. System clock timing
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Multichannel audio coder-decoder
WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK)
tr
tf
t d(DATAO-WS)
t h(DATAO)
t su(DATAI) t h(DATAI) DATAI
mgs756
Fig 17. I2S-bus serial interface timing
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
mgl723
Fig 18. L3-bus address mode timing
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tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK tsu(L3)DA th(L3)DA L3DATA write
BIT 0
BIT 7
L3DATA read ten(L3)R th(L3)R tsu(L3)R tdis(L3)R
mgu015
Fig 19. L3-bus data transfer (write and read) mode timing
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA S tSU;STA Sr tSU;STO
tHD;DAT
tHIGH
P
S
msc610
Fig 20. I2C-bus timing
16. Test information
16.1 Quality information
The General Quality Specification for Integrated Circuits, SNW-FQ-611 is applicable.
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17. Package outline
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.1 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.4 0.2 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-01 03-02-25
Fig 21. Package outline SOT307-2 (QFP44)
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Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
18. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
19. Soldering
19.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
19.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
19.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
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Product data sheet
Rev. 02 -- 17 January 2005
50 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
19.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
19.5 Package related soldering information
Table 68: Package [1] BGA, LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8],
[1]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave Reflow [2] suitable suitable not suitable not suitable [4]
HTSSON..T [3],
suitable not WQCCN..L [8] recommended [5] [6] not recommended [7] not suitable
suitable suitable suitable not suitable
PMFP [9],
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office.
9397 750 14366
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 17 January 2005
51 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[3]
[4]
[5] [6] [7] [8]
[9]
9397 750 14366
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 17 January 2005
52 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
20. Revision history
Table 69: Revision history Release date 20050117 Data sheet status Product data sheet Change notice Doc. number 9397 750 14366 Supersedes UDA1384_1 Document ID UDA1384_2 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors Section 4 "Quick reference data": Added values for IDDD(pd) Section 14 "Static characteristics": Added values for IDDD(pd) Section 15 "Dynamic characteristics": Removed PSRR specification and (THD+N)/S at -20 dBFS, added (THD+N)/S for DAC differential mode Preliminary specification 9397 750 12043 -
UDA1384_1
20031009
9397 750 14366
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 17 January 2005
53 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
21. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
22. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
23. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
24. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14366
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 17 January 2005
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