View CY7C09089V_240410.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1
PRELIMINARY
CY7C09079V/89V/99V CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
Features
* True Dual-Ported memory cells which allow simultaneous access of the same memory location * 6 Flow-Through/Pipelined devices -- 32K x 8/9 organizations (CY7C09079V/179V) -- 64K x 8/9 organizations (CY7C09089V/189V) -- 128K x 8/9 organizations (CY7C09099V/199V) * 3 Modes -- Flow-Through -- Pipelined -- Burst * Pipelined output mode on both ports allows fast 100-MHz operation * 0.35-micron CMOS for optimum speed/power
v
* High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns (max.) * 3.3V low operating power -- Active= 115 mA (typical) -- Standby= 10 A (typical) * Fully synchronous interface for easier operation * Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise * * * * -- Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP
Logic Block Diagram
R/WL OEL R/WR OER
CE0L CE1L
1
0/1
1
0/1
0
0
CE0R CE1R
FT/PipeL
[3]
0/1
1
0
0
1
0/1
FT/PipeR
[3]
8/9
8/9
I/O0L-I/O 7/8L I/O Control
[4]
I/O0R-I/O 7/8R I/O Control
15/16/17
[4]
15/16/17
A0-A14/15/16L CLKL ADSL CNTENL CNTRSTL
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0-A 14/15/16R CLKR ADSR CNTENR CNTRSTR
Notes: 1. Call for availability. 2. See page 6 for Load Conditions. 3. I/O0-I/O7 for x8 devices; I/O0-I/O8 for x9 devices. 4. A0-A14 for 32K; A0-A15 for 64K; and A0-A16 for 128K devices.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 September 23, 1999
PRELIMINARY
Functional Description
The CY7C09079V/89V/99V and CY7C09179V/89V/99V are high-speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[5] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1, 2] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.
CY7C09079V/89V/99V CY7C09179V/89V/99V
A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
CNTENR CNTENL
100-Pin TQFP (Top View)
ADSR CLKR ADSL CLKL GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L A13L A14L
[6] [7]
NC 75 74 73 72 71 70 69 68 67 66
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER [8] GND NC
[6] [7]
A15L A16L VCC NC NC NC NC CE0L CE1L
CY7C09099V (128K x 8) CY7C09089V (64K x 8) CY7C09079V (32K x 8)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CNTRSTL R/WL OEL
[8]
FT/PIPEL NC NC
I/O0R
I/01R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
GND
NC
GND
VCC
GND
VCC
NC
NC
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Notes: 5. When writing simultaneously to the same location, the final value cannot be guaranteed. 6. This pin is NC for CY7C09079V. 7. This pin is NC for CY7C09079V and CY7C09089V. 8. For CY7C09079V and CY7C09089V, pin #23 connected to VCC is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin compatible with an IDT 5V x16 flow-through device.
I/O0L
2
NC
PRELIMINARY
Pin Configurations (continued)
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL GND GND A0R A1R A2R A3R
CY7C09079V/89V/99V CY7C09179V/89V/99V
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L A13L A14L
[9] [10]
NC 75 74 73 72 71 70 69 68 67 66
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R [9] A16R [10] GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER GND NC
A15L A16L VCC NC NC NC NC CE0L CE1L
CY7C09199V (128K x 9) CY7C09189V (64K x 9) CY7C09179V (32K x 9)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CNTRSTL R/WL OEL FT/PIPEL NC NC
I/O0R
I/01R
VCC
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
GND
GND
GND
NC
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Selection Guide
CY7C09079V/89V/99V CY7C09179V/89V/99V -6[1, 2] fMAX2 (MHz) (Pipelined) Max. Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (A) (Both Ports CMOS Level) 100 6.5 CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V -7[2] -9 83 7.5 67 9 CY7C09079V/89V/99V CY7C09179V/89V/99V -12 50 12
175 25
I/O0L
155 25
135 20
NC
115 20
10 A
10 A
10 A
10 A
Notes: 9. This pin is NC for CY7C09179V. 10. This pin is NC for CY7C09179V and CY7C09189V.
3
PRELIMINARY
Pin Definitions
Left Port A0L-A16L ADSL Right Port A0R-A16R ADSR Description
CY7C09079V/89V/99V CY7C09179V/89V/99V
Address Inputs (A0-A 14 for 32K; A0-A15 for 64K; and A0-A16 for 128K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0-I/O7 for x8 devices; I/O0-I/O8 for x9 devices). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current ...................................................... >200mA
CE0L,CE1L CLKL CNTENL
CE0R,CE1R CLKR CNTENR
CNTRSTL I/O0L-I/O 8L OEL R/WL FT/PIPEL GND NC VCC
CNTRSTR I/O0R-I/O8R OER R/WR FT/PIPE R
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ..-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................-0.5V to VCC+0.5V DC Input Voltage......................................-0.5V to VCC+0.5V
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 300 mV 3.3V 300 mV
4
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C09079V/89V/99V CY7C09179V/89V/99V
CY7C09079V/89V/99V CY7C09179V/89V/99V -6[1, 2] Max. Typ. Min. Min. Parameter VOH VOL VIH VIL IOZ ICC Description Output HIGH Voltage (VCC=Min., IOH= -4.0 mA) Output LOW Voltage (VCC=Min., IOH= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC=Max., IOUT=0 mA) Outputs Disabled Com'l. Indust. 25 95 25 85 -10 175 2.0 0.8 10 320 -10 155 -7[2] Max. Typ. Min. -9 Max. Typ. Min. -12 Units V 0.4 2.0 0.8 -10 135 185 20 35 115 175 105 165 95 105 10 250 10 250 10 10 105 135 95 125 85 95 10 225 295 65 75 150 160 250 250 115 125 75 100 10 250 85 140 20 50 -10 115 0.8 10 205 V V V A mA mA mA mA mA mA A A mA mA Max. Unit pF pF Typ.
2.4 0.4
2.4 0.4 2.0 0.8 10 275
2.4 0.4 2.0
2.4
ISB1
Standby Current (Both Com'l. Ports TTL Level)[11] CEL Indust. & CER VIH, f=fMAX Standby Current (One Com'l. Port TTL Level)[11] CEL | Indust. CER VIH, f=fMAX Com'l. Standby Current (Both Ports CMOS Level)[11] Indust. CEL & CER VCC - 0.2V, f=0 Standby Current (One Port CMOS Level)[11] CEL | CER VIH, f=fMAX Com'l. Indust.
ISB2
ISB3
ISB4
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 10 10
Note: 11. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH).
5
PRELIMINARY
AC Test Loads
3.3V
CY7C09079V/89V/99V CY7C09179V/89V/99V
3.3V R1 = 590 OUTPUT C = 30 pF R2 = 435 VTH = 1.4V OUTPUT C = 30 pF RTH = 250 R1 = 590 OUTPUT C = 5 pF R2 = 435
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1)
(c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig)
AC Test Loads (Applicable to -6 and -7 only)[12]
OUTPUT C
Z0 = 50
R = 50 3.0V GND VTH = 1.4V 10% 3 ns
ALL INPUT PULSES
90% 90% 10% 3 ns
(a) Load 1 (-6 and -7 only)
0. 60
0. 50
(ns) for all -7 access times
0. 40
0. 30
0. 20
0. 1 0
0. 00 10 15 20 25 30 35
Capacitance (pF)
(b) Load Derating Curve
Note: 12. Test Conditions: C = 10 pF.
6
PRELIMINARY
Switching Characteristics Over the Operating Range
CY7C09079V/89V/99V CY7C09179V/89V/99V
CY7C09079V/89V/99V CY7C09179V/89V/99V -6[1, 2] Max. Min. Parameter fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ[13,14] tOHZ[13,14] tCD1 tCD2 tDC tCKHZ tCKLZ
[13,14] [13,14]
-7 [2] Max. Min.
-9 Max. Min.
-12 Max. 33 50 30 20 12 12 8 8 3 3 3 3 4 1 4 1 4 1 4 1 4 1 5 1 4 1 10 12 2 7 20 9 1 7 25 12 2 9 2 2 40 15 40 15 9 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min.
Description fMax Flow-Through fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-Up Time Address Hold Time Chip Enable Set-Up Time Chip Enable Hold Time R/W Set-Up Time R/W Hold Time Input Data Set-Up Time Input Data Hold Time ADS Set-Up Time ADS Hold Time CNTEN Set-Up Time CNTEN Hold Time CNTRST Set-Up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Write Port Clock HIGH to Read Data Delay Clock to Clock Set-Up Time 2 2 2 2 1
53 100 19 10 6.5 6.5 4 4 3 3 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 8 2 7 15 6.5 2 9 2 2 30 9 1 4 0 4 0 4 0 4 0 4 0 4.5 0 4 0 22 12 7.5 7.5 5 5
45 83 25 15 12 12 6 6 3 3 4 1 4 1 4 1 4 1 4 1 5 1 4 1 9 2 7 18 7.5 2 9 2 2 35 10 1
40 67
Port to Port Delays tCWDD tCCS
Notes: 13. Test conditions used are Load 2. 14. This parameter is guaranteed by design, but it is not production tested.
7
PRELIMINARY
Switching Waveforms (continued)
Read Cycle for Flow-Through Output (FT/PIPE = V IL)[15, 16, 17, 18]
tCH1 CLK tCYC1 tCL1
CY7C09079V/89V/99V CY7C09179V/89V/99V
CE0 tSC CE1 tHC tSC tHC
R/W tSW tSA ADDRESS DATAOUT tCKLZ tOHZ OE tOE tOLZ An tCD1 tHW tHA An+1 tDC Qn Qn+1 An+2 An+3 tCKHZ Qn+2 tDC
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[15, 16, 17, 18]
tCH2 CLK tCYC2 tCL2
CE0 tSC CE1 tHC tSC tHC
R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE
tOE Notes: 15. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 16. ADS = VIL, CNTEN and CNTRST = VIH. 17. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 18. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
An+2 tDC Qn+1 tOHZ
An+3
Qn+2 tOLZ
8
PRELIMINARY
Switching Waveforms (continued)
Bank Select Pipelined Read[19, 20]
-
CY7C09079V/89V/99V CY7C09179V/89V/99V
tCH2 CLKL tSA ADDRESS(B1) tSC CE0(B1) A0
tCYC2
tCL2
tHA A1 tHC A2 A3 A4 A5
tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE0(B2) tSC DATAOUT(B2) tHC
tSC D0
tHC
tCD2 D1
tCKHZ
tCD2 D3
tCKHZ
tDC A2 tHC
tDC A3 A4
tCKLZ A5
tCD2 D2 tCKLZ
tCKHZ
tCD2 D4 tCKLZ
Left Port Write to Flow-Through Right Port Read[21, 22, 23, 24]
CLKL tSW R/WL tSA ADDRESSL tSD DATAINL CLKR R/WR ADDRESSR tSW tSA tHW tHA NO MATCH tCWDD DATAOUTR tDC VALID tDC tCD1 VALID VALID tCCS tCD1 MATCH tHD tHA NO MATCH tHW
MATCH
Notes: 19. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 20. OE and ADS = VIL ; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 21. The same waveforms apply for a right port write to flow-through left port read. 22. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 23. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 24. It t CCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. t CWDD does not apply in this case.
9
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[18, 25, 26, 27]
tCH2 CLK tCYC2 tCL2
CY7C09079V/89V/99V CY7C09179V/89V/99V
CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ NO OPERATION
[18, 25, 26, 27]
tHC
tHW
tHW An+1 An+2 An+2 tSD tHD tCKHZ Dn+2 tCKLZ tCD2 Qn+3 WRITE READ An+3 An+4
DATAOUT
Pipelined Read-to-Write-to-Read (OE Controlled)
tCH2 CLK tCYC2 tCL2
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW An
tHW An+1 tHA An+2 tSD tHD Dn+2 tCD2 Dn+3 tCKLZ Qn tOHZ tCD2 Qn+4 An+3 An+4 An+5
ADDRESS tSA DATAIN
DATAOUT
OE READ WRITE READ
Notes: 25. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 26. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 27. During "No Operation", data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
10
PRELIMINARY
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[16, 18, 25, 26, 27]
tCH1 CLK tCYC1 tCL1
CY7C09079V/89V/99V CY7C09179V/89V/99V
CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN tCD1 Qn tDC READ An tHA tCD1 Qn+1 tCKHZ NO OPERATION tCKLZ WRITE tHW An+1 An+2 tSD Dn+2 tCD1 Qn+3 tDC READ tCD1 An+2 tHD An+3 An+4 tHW tHC
DATAOUT
Flow-Through Read-to-Write-to-Read (OE Controlled)[16, 19, 25, 26, 27]
tCH1 CLK tCYC1 tCL1
CE0 tSC CE1 tSW R/W tSW An ADDRESS tSA DATAIN tCD1 Qn tOHZ tCKLZ tHA tDC tSD Dn+2 tHD Dn+3 tOE tCD1 Qn+4 tDC tCD1 tHW An+1 An+2 An+3 An+4 An+5 tHW tHC
DATAOUT
OE READ WRITE READ
11
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[28]
tCYC2 tCL2
CY7C09079V/89V/99V CY7C09179V/89V/99V
tCH2 CLK tSA ADDRESS tSAD ADS An
tHA
tHAD
tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC READ WITH COUNTER tCD2 Qn tSCN Qn+1
tHAD
tHCN Qn+2 Qn+3
COUNTER HOLD
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[28]
tCYC1 tCL1
tCH1 CLK tSA ADDRESS tSAD ADS An
tHA
tHAD tSAD tHAD
CNTEN tSCN tHCN tCD1 Qx tDC READ EXTERNAL ADDRESS Qn Qn+1 tSCN tHCN
DATAOUT
Qn+2 READ WITH COUNTER
Qn+3
READ WITH COUNTER
COUNTER HOLD
Note: 28. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
12
PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[29, 30]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
CY7C09079V/89V/99V CY7C09179V/89V/99V
INTERNAL ADDRESS tSAD ADS tHAD
An
An+1
An+2
An+3
An+4
CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4
WRITE COUNTER HOLD
WRITE WITH COUNTER
Notes: 29. CE0 and R/W = VIL ; CE1 and CNTRST = VIH. 30. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
13
PRELIMINARY
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[18, 25, 31, 32]
tCYC2 tCL2
CY7C09079V/89V/99V CY7C09179V/89V/99V
tCH2 CLK
tSA ADDRESS INTERNAL ADDRESS AX tSW tHW 0 1 An
tHA An+1 An An+1
R/W tSAD ADS tSCN CNTEN tSRST CNTRST DATAIN tHRST tSD D0 Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 READ ADDRESS n Qn tHD tHCN tHAD
DATAOUT
Notes: 31. CE0 = VIL; CE1 = VIH. 32. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
14
PRELIMINARY
Read/Write and Enable Operation[33, 34, 35]
Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs I/O0-I/O9 High-Z High-Z DIN D OUT High-Z
CY7C09079V/89V/99V CY7C09179V/89V/99V
Operation Deselected
[36]
Deselected[36] Write Read[36] Outputs Disabled
Address Counter Control Operation[33, 37, 38, 39]
Address X An X X Previous Address X X An An CLK ADS X L H H CNTEN X X H L CNTRST L H H H I/O Dout(0) Dout(n) Dout(n) Dout(n+1) Mode Reset Load Hold Increment Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked--Counter Disabled Counter Enabled--Internal Address Generation
Notes: 33. "X" = "don't care", "H" = VIH, "L" = VIL. 34. ADS, CNTEN, CNTRST = "don't care". 35. OE is an asynchronous input signal. 36. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 37. CE0 and OE = VIL; CE1 and R/W = VIH. 38. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 39. Counter operation is independent of CE0 and CE1.
15
PRELIMINARY
Ordering Information
32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 12 Ordering Code CY7C09079V-6AC CY7C09079V-7AC CY7C09079V-9AC CY7C09079V-9AI CY7C09079V-12AC Package Name A100 A100 A100 A100 A100
CY7C09079V/89V/99V CY7C09179V/89V/99V
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
OperatingRange Commercial Commercial Commercial Industrial Commercial
64K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 12 Ordering Code CY7C09089V-6AC CY7C09089V-7AC CY7C09089V-9AC CY7C09089V-9AI CY7C09089V-12AC Package Name A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Industrial Commercial
128K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5
[1, 2]
Ordering Code CY7C09099V-6AC CY7C09099V-7AC CY7C09099V-9AC CY7C09099V-9AI CY7C09099V-12AC
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Commercial Industrial Commercial
7.5[2] 9 12
32K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5
[1, 2]
Ordering Code CY7C09179V-6AC CY7C09179V-7AC CY7C09179V-9C CY7C09179V-9AI CY7C09179V-12AC
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Commercial Industrial Commercial
7.5[2] 9 12
64K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 12 Ordering Code CY7C09189V-6AC CY7C09189V-7AC CY7C09189V-9AC CY7C09189V-9AI CY7C09189V-12AC Package Name A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Industrial Commercial
128K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 12 Ordering Code CY7C09199V-6AC CY7C09199V-7AC CY7C09199V-9AC CY7C09199V-9AI CY7C09199V-12AC Document #: 38-00667-E 16 Package Name A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Industrial Commercial
PRELIMINARY
Package Diagram
CY7C09079V/89V/99V CY7C09179V/89V/99V
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY7C09089V

	To Download CY7C09089V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .