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LTC1420 12-Bit, 10Msps, Sampling ADC
FEATURES
s s s s s s s s s s s s
DESCRIPTIO
10Msps Sample Rate Single 5V Supply or 5V Supplies Integral Nonlinearity Error <0.35LSB Differential Nonlinearity <0.25LSB 71dB S/(N + D) and 83dB SFDR at Nyquist 100MHz Full-Power Bandwidth Sampling 2.048V, 1.024V and 0.512V Bipolar Input Range Input PGA Out-of-Range Indicator True Differential Inputs with 75dB CMRR Power Dissipation: 250mW 28-Pin Narrow SSOP Package
The LTC(R)1420 is a 10Msps, 12-bit sampling A/D converter that draws only 250mW from either single 5V or dual 5V supplies. This easy-to-use device includes a high dynamic range sample-and-hold, a precision reference and a PGA input circuit. The LTC1420 has a flexible input circuit that allows fullscale input ranges of 2.048V 1.024V and 0.512V. The input common mode voltage is arbitrary, though a 2.5V reference is provided for single supply applications. The input PGA has a digitally selectable 1x or 2x gain. Maximum DC specs include 1LSB INL and 1LSB DNL over temperature. Outstanding AC performance includes 71dB S/(N + D) and 83dB SFDR at the Nyquist input frequency of 5MHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 100MHz bandwidth. The 75dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. A separate output logic supply allows direct connection to 3V components.
APPLICATIO S
s s s s s s
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectral Analysis Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
5V 1F 28 GAIN
5V 1F 7 VDD
5V 1F 23 VDD 22 OVDD OPTIONAL 3V LOGIC SUPPLY
+
VIN
1 +AIN
S/H 2 -AIN 3 VCM
PIPELINED 12-BIT ADC
OF 27 D11 (MSB) 10
INL (LSBs)
-
1F
OUTPUT BUFFERS MODE SELECT DIGITAL CORRECTION LOGIC D0 (LSB) 20 CLK 26
DIGITAL OUTPUT
4 SENSE
2.5V REFERENCE 5 VREF 1F 2.048V
10MHz CLK
VSS 25 1F 0V OR -5V
GND 6
GND 8
GND 24
OGND 21
1420 TA01
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Typical INL Curve
1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 1024 2048 CODE 3072 4096
1420 TA02
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LTC1420
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW +AIN -AIN VCM SENSE VREF GND VDD GND D11 (MSB) 1 2 3 4 5 6 7 8 9 28 GAIN 27 OF 26 CLK 25 VSS 24 GND 23 VDD 22 OVDD 21 OGND 20 D0 19 D1 18 D2 17 D3 16 D4 15 D5
0VDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) ................................ - 6V Total Supply Voltage (VDD to VSS) ........................... 12V Analog Input Voltage (Note 3) ............................. (VSS - 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ............................. (VSS - 0.3V) to (VDD + 0.3V) Digital Output Voltage ........ (VSS - 0.3V) to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1420C ............................................... 0C to 70C LTC1420I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1420CGN LTC1420IGN
D10 10 D9 11 D8 12 D7 13 D6 14
GN PACKAGE 28-LEAD PLASTIC SSOP
TJMAX = 110C, JA = 110C/W
Consult factory for Military grade parts.
CONVERTER CHARACTERISTICS The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. With Internal 4.096V Reference. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco IOUT(REF) = 0 (Note 8)
q
CONDITIONS
q
MIN 12
q q
TYP 0.35 0.25 5 10 15
MAX 1 1 12 16 30
UNITS Bits LSB LSB LSB LSB LSB ppm/C
(Note 7)
A ALOG I PUT
SYMBOL VIN PARAMETER
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
CONDITIONS VREF = 4.096V (SENSE = 0V), GAIN = 5V (1x) VREF = 4.096V (SENSE = 0V), GAIN = 0V (2x) VREF = 2.048V (SENSE = VREF), GAIN = 5V (1x) VREF = 2.048V (SENSE = VREF), GAIN = 0V (2x) External VREF (SENSE = 5V), GAIN = 5V (1x) External VREF (SENSE = 5V), GAIN = 0V (2x) Between Conversions During Conversions
q q q q q q q
MIN
TYP 2.048 1.024 1.024 0.512 VREF/2 VREF/4
MAX
UNITS V V V V V V
Analog Input Range (Note 9) +AIN - (-AIN)
IIN CIN tACQ tAP tjitter CMRR
Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio -2.048V < (-AIN = +AIN) < 2.048V
20 12 6 30 - 250 0.6 75
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A pF pF ns ps ps dB
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LTC1420
DY A IC ACCURACY
SYMBOL S/(N + D) THD SFDR IMD PARAMETER
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 5V, VSS = - 5V, fSAMPLE = 10MHz, VREF = 4.096V. + AIN = - 0.1dBFS single ended input, - AIN = 0V. (Note 6)
CONDITIONS 1MHz Input Signal 5MHz Input Signal 1MHz Input Signal, First 5 Harmonics 5MHz Input Signal, First 5 Harmonics 1MHz Input Signal 5MHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz 2.048V Input Range 1.024V Input Range, 2x Mode (SENSE = GAIN = 0V) 1.5x FS Input to 0 (Settling to 1LSB) Settling to 1LSB
q q q q q q
INTERNAL REFERENCE CHARACTERISTICS
TA = 25C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance VREF Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V - 5.25V VSS -4.75V 0.1mA IOUT 0.1mA SENSE = GND, IOUT = 0 SENSE = VREF, IOUT = 0 SENSE = VDD MIN 2.475 TYP 2.50 15 0.6 0.03 8 4.096 2.048 Drive VREF with External Reference 15 MAX 2.525 UNITS V ppm/C mV/V mV/V V V V ppm/C
VREF Output Tempco
DIGITAL I PUTS A D DIGITAL OUTPUTS The q denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
SYMBOL VIH VIL IIN CIN VOH PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage 0VDD = 4.75V, IO = -10A 0VDD = 4.75V, IO = -200A 0VDD = 2.7V, IO = -10A 0VDD = 2.7V, IO = -200A 0VDD = 4.75V, IO = 160A 0VDD = 4.75V, IO = 1.6mA 0VDD = 2.7V, IO = 160A 0VDD = 2.7V, IO = 1.6mA VOUT = 0V VOUT = VDD
q q q q
VOL
Low Level Output Voltage
ISOURCE ISINK
Output Source Current Output Sink Current
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WU U
MIN 68.5 68
TYP 71.4 71.0 - 84 - 81 - 85 - 83 - 80 100 0.22 0.33 15 15
MAX
UNITS dB dB
Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Full-Power Bandwidth Input Referred Noise Overvoltage Recovery Time Full-Scale Step Acquisition Time
- 77 - 73 - 78.5 - 75
dB dB dB dB dB MHz LSBRMS LSBRMS ns ns
U
CONDITIONS VDD = 5.25V, VSS = 0V VDD = 5.25V, VSS = - 5V VDD = 4.75V, VSS = 0V VDD = 4.75V, VSS = - 5V VIN = 0V to VDD
q q q q q
MIN 2.4 3.5
TYP
MAX
UNITS V V
0.8 1 10 1.8 4.0 2.3 0.05 0.10 0.05 0.10 50 35 0.4 0.4 4.74 4.71 2.6
V V A pF V V V V V V V V mA mA
3
LTC1420
POWER REQUIRE E TS
SYMBOL VDD OVDD VSS IDD ISS PD PARAMETER Positive Supply Voltage Output Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
CONDITIONS (Note 10) (Note 10) Dual Supply Mode Single Supply Mode
q q q
TI I G CHARACTERISTICS
SYMBOL fSAMPLE tCONV tACQ tH tL tAP PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time CLK High Time CLK Low Time Aperature Delay of Sample-and-Hold
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
CONDITIONS
q q q q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. GAIN is not clamped to VDD. When CLK is taken above VDD, it will be clamped by an internal diode. The CLK pin can handle input currents of greater than 100mA above VDD without latchup.
4
UW
MIN 4.75 2.7 - 5.25
TYP
MAX 5.25 5.25 - 4.75
UNITS V V V V mA mA mW
0 48 1.4 250 58 2.5 300
UW
MIN 0.02
TYP 70
MAX 10 90
UNITS MHz ns ns ns ns ps
10 20 20
30 50 50 - 250
Note 5: VDD = 5V, VSS = - 5V or 0V, fSAMPLE = 10MHz, tr = tf = 5ns unless otherwise specified. Note 6: Dynamic specifications are guaranteed for dual supply operation with a single-ended + AIN input and - AIN grounded. For single supply dynamic specifications, refer to the Typical Performance Characteristics. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from -0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions.
LTC1420 TYPICAL PERFOR A CE CHARACTERISTICS
S/(N+D) vs Input Frequency and Amplitude
75 VIN = 0dB 70
65 DUAL SUPPLIES 2.048V RANGE GAIN = 1x
dBc 70 60 50 40 -50 DUAL SUPPLIES 2.048V RANGE GAIN = 1x fIN = 5MHz -40 -30 -20 -10 INPUT AMPLITUDE (dBFS) 0
1420 G03
DISTORTION (dB)
S/(N + D) (dB)
VIN = -6dB
SFDR (dBc AND dBFS)
60
55 VIN = -20dB 50 0.1
10 1 INPUT FREQUENCY (MHz)
S/(N+D) vs Input Frequency and Amplitude
75 VIN = 0dB
100
70
S/(N + D) (dB)
SINGLE SUPPLY 1.024V RANGE GAIN = 2x
SFDR (dBc AND dBFS)
65
VIN = -6dB
80 dBc 70 60 50 SINGLE SUPPLY 1.024V RANGE GAIN = 2x fIN = 5MHz -40 -30 -20 -10 INPUT AMPLITUDE (dBFS) 0
1420 G05
DISTORTION (dB)
60
55 VIN = -20dB 50 0.1 10 1 INPUT FREQUENCY (MHz) 100
1420 G02
SFDR vs Input Frequency, Differential Input
-50 -55 -60 -65 SFDR (dB) SFDR (dB) -70 -75 -80 -85 -90 -95 -100 0.1 10 1 INPUT FREQUENCY (MHz) 100
1420 F07
DUAL SUPPLIES 2.048V RANGE GAIN = 1x AIN = 0dBFS
-75 -80 -85 -90 -95
HITS
UW
1420 G01
Spurious-Free Dynamic Range vs Input Amplitude
100 90 80 dBFS
-50 -55 -60 -65 -70 -75 -80 -85 -90 -95
Distortion vs Input Frequency
DUAL SUPPLIES 2.048V RANGE GAIN = 1x AIN = 0dBFS
THD 3RD 2ND
100
0
1 10 INPUT FREQUENCY (MHz)
100
1420 G04
Spurious-Free Dynamic Range vs Input Amplitude
-50
dBFS 90
Distortion vs Input Frequency
-55 -60 -65 -70 -75 -80 -85 -90 -95 0 1 10 INPUT FREQUENCY (MHz) 100
1420 G06
SINGLE SUPPLY 1.024V RANGE GAIN = 2x AIN = 0dBFS
THD 2ND
3RD
40 -50
SFDR vs Input Frequency, Differential Input
-50 -55 -60 -65 -70 SINGLE SUPPLY 1.024V RANGE GAIN = 2x AIN = 0dBFS
Grounded Input Histogram
VREF = 4.096V GAIN = 1x 410554
-100 0.1 10 1 INPUT FREQUENCY (MHz) 100
1420 F08
1570 N-1 N CODE
1572 N+1
1420 F09
5
LTC1420 TYPICAL PERFOR A CE CHARACTERISTICS
IDD vs Clock Frequency
52 50 48
IDD (mA)
ISS (mA)
10
VREF = 4.096V 46 VREF = 2.048V 44
42 40 0 2 4 6 8 CLOCK FREQUENCY (MHz)
CMRR vs Input Frequency
90 80 70
50 40 30 20
AMPLITUDE (dB)
60
CMRR (dB)
10 0 0.01
0.1 1 INPUT FREQUENCY (MHz)
PIN FUNCTIONS
+ AIN (Pin 1): Positive Analog Input. - AIN (Pin 2): Negative Analog Input. VCM (Pin 3): 2.5V Reference Output.Optional input common mode for single supply operation. Bypass to GND with a 1F to 10F ceramic. SENSE (Pin 4): Reference Programming Pin. Ground selects VREF = 4.096V. Short to VREF for 2.048V. Connect SENSE to VDD to drive VREF with an external reference. VREF (Pin 5): DAC Reference. Bypass to GND with a 1F to 10F ceramic. GND (Pin 6): DAC Reference Ground. VDD (Pin 7): Analog 5V Supply. Bypass to GND with a 1F to 10F ceramic. GND (Pin 8): Analog Power Ground. D11 to D0 (Pins 9 to 20): Data Outputs. The output format is two's complement. OGND (Pin 21): Output Logic Ground. Tie to GND. OVDD (Pin 22): Positive Supply for the Output Logic. Connect to Pin 23 for 5V logic. If not shorted to Pin 23, bypass to GND with a 1F ceramic.
6
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ISS vs Clock Frequency
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 CLOCK FREQUENCY (MHz) 10
1420 G11
1420 G10
LTC1420 Nonaveraged 4096 Point FFT
0 -20 -40 -60 -80 fSAMPLE = 10Msps fIN = 5.048828125MHz SFDR = 83.2dB SINAD = 71dB VIN = 4VP-P 5V SUPPLIES
-100 -120
10
1420 G12
0
1
2 3 FREQUENCY (MHz)
4
5
1420 G13
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LTC1420
PIN FUNCTIONS
VDD (Pin 23): Analog 5V Supply. Bypass to GND with a 1F ceramic. GND (Pin 24): Analog Power Ground. VSS (Pin 25): Negative Supply. Can be - 5V or 0V. If VSS is not shorted to GND, bypass to GND with a 1F ceramic. CLK (Pin 26): Conversion Start Signal. This active high signal starts a conversion on its rising edge. OF (Pin 27): Overflow Output. This signal is high when the digital output is 011111111111 or 100000000000. GAIN (Pin 28): Gain Select for Input PGA. 5V selects an input gain of 1, 0V selects a gain of 2.
FUNCTIONAL BLOCK DIAGRA
GAIN
+AIN
S/H -AIN VCM MODE SELECT SENSE
VREF 2.048V
VSS 0V OR -5V
TI I G DIAGRA
ANALOG INPUT
N tCLOCK tH tL
CLK tCONV tACQ DATA OUTPUT N-3 N-2 N-1 N
1420 TD
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5V VDD (PIN 7) VDD (PIN 23) OVDD
OPTIONAL 3V LOGIC SUPPLY
PIPELINED 12-BIT ADC
OF D11 (MSB) OUTPUT BUFFERS
DIGITAL CORRECTION LOGIC
D0 (LSB) CLK
2.5V REFERENCE
1420 BD
GND (PIN 6)
GND (PIN 8)
GND (PIN 24)
OGND
N+1 N+2 N+3
7
LTC1420
APPLICATIONS INFORMATION
Conversion Details The LTC1420 is a high performance 12-bit A/D converter that operates up to 10Msps. It is a complete solution with an on-chip sample-and-hold, a 12-bit pipelined CMOS ADC, a low drift programmable reference and an input programmable gain amplifier. The digital output is parallel, with a 12-bit two's complement output and an out-ofrange (overflow) bit. The rising edge of the CLK begins a conversion. The differential analog inputs are simultaneously sampled and passed on to the pipelined A/D. After two more conversion starts (plus a 70ns conversion time) the digital outputs are updated with the conversion result and will be ready for capture on the third rising clock edge. Thus, even though a new conversion is begun every time CLK goes high, each result takes three clock cycles to reach the output. The analog signals that are passed from stage to stage in the pipelined A/D are stored on capacitors. The signals on these capacitors will be lost if the delay between conversions is too long. For accurate conversion results, the part should be clocked faster than 20kHz. In some pipelined A/D converters if there is no clock present, dynamic logic on the chip will droop and the power consumption sharply increases. The LTC1420 doesn't have this problem. If the part is not clocked for 500s, an internal timer will refresh the dynamic logic. Thus, the clock can be turned off for long periods of time to save power. Power Supplies The LTC1420 will operate from either a single 5V or dual 5V supply, making it easy to interface the analog input to single or dual supply systems. The digital output drivers have their own power supply pin (OVDD) which can be set from 3V to 5V, allowing direct connection to either 3V or 5V digital systems. For single supply operation, VSS should be connected to analog ground. For dual supply operation, VSS should be connected to - 5V. Both VDD pins should be connected to a clean 5V analog supply. (Don't connect VDD to a noisy system digital supply.) Analog Input Ranges The LTC1420 has a flexible analog input with a wide selection of input ranges. The input range is always differential and is set by the voltages at the VREF and the GAIN pins (Figure 1). The input range of the A/D core is fixed at VREF/2. The reference voltage, VREF, is either set by the on-chip voltage reference or directly driven by an external voltage. The GAIN pin is a digital input that controls the gain of a preamplifier in the sample-and-hold circuit. The gain of this PGA can be set to 1x or 2x. Table 1 gives the input range in terms of VREF and GAIN.
Table 1
GAIN PIN 5V (Logic H) OV (Logic L)
GAIN 1x/2x + VIN - +AIN PGA S/H VREF/2 ADC CORE
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PGA GAIN 1x 2x
INPUT RANGE (VIN = AIN + - AIN -) - VREF/2 < VIN < VREF/2 - VREF/4 < VIN < VREF/4
-AIN
VREF
1420 F01
Figure 1. Analog Input Circuit
Internal Reference Figure 2 shows a simplified schematic of the LTC1420 reference circuitry. An on-chip temperature compensated bandgap reference (VCM) is factory trimmed to 2.500V. The voltage at the VREF pin sets the input span of the ADC to VREF/2. An internal voltage divider converts VCM to 2.048V, which is connected to a reference amplifier. The reference programming pin, SENSE, controls how the reference amplifier drives the VREF pin. If SENSE is tied to ground, the reference amplifier feedback is connected to the R1/R2 voltage divider, thus making VREF = 4.096V. If SENSE is tied to VREF, the reference amplifier feedback is connected to SENSE thus making VREF = 2.048V. If SENSE is tied to VDD, the reference amplifier is disconnected from
LTC1420
APPLICATIONS INFORMATION
VREF and VREF can be driven by an external voltage. With two additional resistors, VREF can be set to any voltage between 2.048V and 4.5V. An external reference or a DAC can be used to drive VREF over a 0V to 5V range (Figures 3a and 3b). The input impedance of the VREF pin is 1k, so a buffer may be required for high accuracy. Driving VREF with a DAC is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. Both the VCM and VREF pins must be bypassed with capacitors to ground. For best performance, 1F or larger ceramic capacitors are recommended. For the case of external circuitry driving VREF, a smaller capacitor can be used at VREF so the input range can be changed quickly. In this case, a 0.05F or larger ceramic capacitor is acceptable. The VCM pin is a low output impedance 2.5V reference that can be used by external circuitry. For single 5V supply applications it is convenient to connect - AIN directly to the VCM pin. Driving the Analog Inputs The differential inputs of the LTC1420 are easy to drive. The inputs may be driven differentially or single-ended (i. e., the - AIN input is held at a fixed value). The - AIN and + AIN inputs are simultaneously sampled and any common mode signal is reduced by the high common mode rejection of the sample-and-hold circuit. Any common mode input value is acceptable as long as the input pins stay between VDD and VSS. During conversion, the analog inputs are high impedance. At the end of conversion, the inputs draw a small current spike while charging the sample-and-hold. For superior dynamic performance in dual supply mode, the LTC1420 should be operated with the analog inputs centered at ground, and in single supply mode the inputs should be centered at 2.5V. If required, the analog inputs can be driven differentially via a transformer. Refer to Table 2 for a summary of the analog input and reference configurations and their relative advantages.
VREF 1F TO ADC
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+
R1 5k
1k
-
SENSE R2 5k LOGIC 2.5V REFERENCE 2.048V VCM 1F
1420 F02
Figure 2. Reference Circuit
5V VIN VOUT LT1019A-2.5 1F VREF LTC1420 SENSE VCM 1F
1420 F03a
5V
Figure 3a. Using the LT1019-2.5 As an External Reference; Input Range = 1.25V
LTC1420 VREF 5k 1F SENSE 5k LTC1450 1F VCM
1420 F03b
+ -
2.048V
Figure 3b. Driving VREF with a DAC
9
LTC1420
APPLICATIONS INFORMATION
Table 2. Comparison of Analog Input Configurations
SUPPLIES 5V 5V 5V 5V 5V 5V 5V COUPLING DC DC DC DC DC AC (Transformer) AC (Transformer) VREF 4.096V 4.096V 2.048V 4.096V 4.096V 4.096V 4.096V GAIN 1x 2x 1x 1x 1x 1x 1x AIN + 2.048 2.5 1.024 2.5 1.024 2.5 2.048 0 to 4.096 1.024 2.5 1.024 AIN - 0 2.5 2.5 2.5 2.048 1.024 2.5 1.024 COMMENTS Best SNR, THD Best SINAD, THD for Single Supply Worse Noise than Above Case Best Single Supply Noise, THD Is Not Optimal Same As Above Very Best SNR, THD Very Best SNR, THD for Single Supply
DC Coupling the Input In most applications the analog input signal can be directly coupled to the LTC1420 inputs. If the input signal is centered around ground, such as when dual supply op amps are used, simply connect - AIN to ground and connect VSS to - 5V (Figure 4). In a single power supply system with the input signal centered around 2.5V, connect - AIN to VCM and VSS to ground (Figure 5). If the input signal is not centered around ground or 2.5V, the voltage for - AIN must be generated externally by a resistor divider or a voltage reference (Figure 6).
5V
4.096V VIN 0V 5V 2.048V +AIN
0V
VIN
+AIN LTC1420 -AIN
VCM 1F
VSS
1420 F04
-5V
Figure 4. DC Coupling a Ground Centered Signal (Dual Supply System)
5V
2.5V
VIN
+AIN LTC1420 -AIN
VCM 1F
VSS
1420 F05
Figure 5. DC Coupling a Signal Centered Around 2.5V (Single Supply System)
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5V
LTC1420 -AIN SENSE VSS
1420 F06
Figure 6. DC Coupling a 0V to 4.096V Signal
AC Coupling the Input The analog inputs to the LTC1420 can also be AC coupled through a capacitor, though in most cases it is simpler to directly couple the input to the ADC. Figure 7 shows an example where the input signal is centered around ground and the ADC operates from a single 5V supply. Note that the performance would improve if the ADC was operated from a dual supply and the input was directly coupled (as in Figure 4). With AC coupling the DC resistance to ground should be roughly matched for + AIN and - AIN to maintain offset accuracy.
5V C 0V VIN +AIN LTC1420 -AIN R R C VCM 1F VSS
1420 F07
Figure 7. AC Coupling to the LTC1420. Note That the Input Signal Can Almost Always Be Directly Coupled with Better Performance
LTC1420
APPLICATIONS INFORMATION
Differential Operation The THD and SFDR performance of the LTC1420 can be improved by using a center tap RF transformer to drive the inputs differentially. Though the signal can no longer be DC coupled, the improvement in dynamic performance makes this an attractive solution for some applications. Typical connections for single and dual supply systems are shown in Figures 8a and 8b. Good choices for transformers are the Mini Circuits T1-1T (1:1 turns ratio) and T4-6T (1:4 turns ratio). For best results, the transformer should be located close to the LTC1420 on the printed circuit board.
5V MINI CIRCUITS T1-1T VIN 15 +AIN 470pF 15 LTC1420 -AIN
VCM 1F
VSS
1420 F08a
Figure 8a. Single Supply Transformer Coupled Input
5V MINI CIRCUITS T1-1T VIN 15 +AIN 470pF 15 LTC1420 -AIN
VCM 1F
VSS
1420 F08b
-5V
Figure 8b. Dual Supply Transformer Coupled Input
Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 100MHz, then the output impedance at 100MHz must be less than 100.
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The second requirement is that the closed-loop bandwidth must be greater than 100MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1420 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1420 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 100MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 9 shows a 470pF capacitor from + AIN to - AIN and a 30 source resistor to limit the input bandwidth to 11.3MHz. The 470pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the amplifier driving VIN from the ADC's small current glitch. In undersampling applications, an input capacitor this large may prohibitively limit the input bandwidth. If this is the case, use as large an input capacitance as possible. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems.
30 VIN 470pF +AIN LTC1420 -AIN
Figure 9. RC Input Filter
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LTC1420
APPLICATIONS INFORMATION
Digital Outputs and Overflow Bit (OF) Figure 10 shows the ideal input/output characteristics for the LTC1420. The output data is two's complement binary for all input ranges and for both single and dual supply operation. One LSB = VREF/4096. To create a straight binary output, invert the MSB (D11). The overflow bit (OF) indicates when the analog input is outside the input range of the converter. OF is high when the output code is 1000 0000 0000 or 0111 1111 1111.
1 OVERFLOW 0 BIT 011...111 011...110 011...101
OUTPUT CODE
100...010 100...001 100...000 -(FS - 1LSB) INPUT VOLTAGE (V)
1420 F10
FS - 1LSB
Figure 10. LTC1420 Transfer Characteristics
Full-Scale and Offset Adjustment In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error should be adjusted before full-scale error. Figure 11 shows a method for error adjustment for a dual supply, 4.096V application. For zero offset error apply - 0.5mV (i. e., - 0.5LSB) at + AIN and adjust R1 until the output code flickers between 0000 0000 0000 and 1111 1111 1111. For full-scale adjustment, apply an input voltage of 2.0465V (FS - 1.5LSBs) at + AIN and adjust R2 until the output code flickers between 0111 1111 1110 and 0111 1111 1111. Digital Output Drivers The LTC1420 output drivers can interface to logic operating from 3V to 5V by setting OVDD to the logic power supply. If 5V output is desired, OVDD can be shorted to VDD and share its decoupling capacitor. Otherwise, OVDD requires its own 1F decoupling capacitor. To prevent digital
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noise from affecting performance, the load capacitance on the digital outputs should be minimized. If large capacitive loads are required (>30pF), external buffers or 100 resistors in series with the digital outputs are suggested.
5V
5V R1 50k -5V 24k
VIN
+AIN LTC1420 -AIN
100
VREF 1F 10k R2 1k 10k -5V SENSE VSS
1420 F11
Figure 11. Offset and Full-Scale Adjust Circuit
Timing The conversion start is controlled by the rising edge of the CLK pin. Once a conversion is started, it cannot be stopped or restarted until the conversion cycle is complete. Output data is updated at the end of conversion, or about 70ns after a conversion is begun. There is an additional two cycle pipeline delay, so the data for a given conversion is output two full clock cycles plus 70ns after the convert start. Thus, output data can be latched on the third CLK rising edge after the rising edge that samples the input. Clock Input The LTC1420 only uses the rising edge of the CLK pin for internal timing, and CLK doesn't necessarily need to have a 50% duty cycle. For optimal AC performance, the rise time of the CLK should be less than 5ns. If the available clock has a rise time slower than 5ns, it can be locally sped up with a logic gate. With single supply operation, the clock can be driven with 5V CMOS, 3V CMOS or TTL logic levels. With dual power supplies, the clock should be driven with 5V CMOS levels. As with all fast ADCs, the noise performance of the LTC1420 is sensitive to clock jitter when high speed inputs
LTC1420
APPLICATIONS INFORMATION
are present. The SNR performance of an ADC when the performance is limited by jitter is given by: SNR = - 20log (2 fIN tJ)dB where fIN is the frequency of an input sine wave and tJ is the root-mean-square jitter due to the clock, the analog input and the A/D aperture jitter. To minimize clock jitter, use a clean clock source such as a crystal oscillator, treat the clock signals as sensitive analog traces and use dedicated packages with good supply bypassing for any clock drivers. Board Layout To obtain the best performance from the LTC1420, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be placed under and around the ADC. Pins 6, 8 and 24 (GND), Pin 21 (OGND) and all other analog grounds should be connected to this ground plane. In single supply mode, Pin 25 (VSS) should also be connected to this ground plane. All bypass capacitors for the LTC1420 should also be connected to this ground plane (Figure 12). The digital system ground should be connected to the analog ground plane at only one point, near the OGND pin. The analog ground plane should be as close to the ADC as possible. Care should be taken to avoid making holes in the analog ground plane under and around the part. To accomplish this, we recommend placing vias for power and signal traces outside the area containing the part and the decoupling capacitors (Figure 13). Supply Bypassing High quality, low series resistance ceramic 1F capacitors should be used at both VDD pins, VCM and VREF. If VSS is connected to - 5V it should also be bypassed to ground with 1F. In single supply operation, VSS should be shorted to the ground plane as close to the part as possible. If OVDD is not shorted to Pin 23 (VDD), it also requires a 1F decoupling capacitor to ground. Surface mount capacitors such as the AVX 0805ZC105KAT provide excellent bypassing in a small board space. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible.
1 470pF ANALOG INPUT CIRCUITRY
+AIN -AIN VCM 3 1F VREF 5 1F GND 6 VDD 7
+ -
2
ANALOG GROUND PLANE
1420 F12
Figure 12. Power Supply Grounding
PLACE NON-GROUND VIAS AWAY FROM GROUND PLANE AND BYPASS CAPACITORS
Figure 13. Cross Section of LTC1420 Printed Circuit Board
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LTC1420 GND 8 1F VDD 23 1F OVDD 22 1F GND 24 VSS 25 1F OGND 21
DIGITAL SYSTEM
LTC1420
BYPASS CAPACITOR ANALOG GROUND PLANE
1420 F13
AVOID BREAKING GROUND PLANE IN THIS AREA
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LTC1420
VCC U2, 74ACT16373DL 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 1 C3 1 JP7 2 3 2 1F 2 R20 0 1 CLOCK R17 51 2 1 48 R18 1 20 2 C6 470pF VCC 1D4 1D3 GND 1D2 1D1 1C 1D5 2 C8 1 0.1F 1D6 GND 1D7 1Q7 GND 1Q6 1Q5 VCC 1Q4 1Q3 GND 1Q2 1Q1 1OE 1D8 1Q8 11 10 9 8 7 6 5 4 3 2 1 2 C7 VCC 0.1F 1 2 5 4 3 U3 NC7S04M5 1 C10 2 0.1F R11 1 R12 1 R21 1 R13 1 R14 1 2 D10 2 D11 2 D11 2 OF 2 CLK 2D1 12 2Q1 2D2 13 2Q2 GND 14 GND 2D3 15 R7 1 R8 1 R9 1 R10 1 2 D6 2 D7 2 D8 2 D9 2Q3 2D4 16 2Q4 VCC VCC 17 1 C11 2 0.1F 2D5 2Q5 18 2 C9 1 0.1F 2D6 2Q6 19 GND GND 20 R3 1 R4 1 R5 1 R6 1 2D7 2Q7 21 2 D2 2 D3 2 D4 2 D5 R2 1 2D8 2Q8 22 2C 2OE 23 100 X 15 PLCS R1 1 2 D0 2 D1 24 VCC 15 16 17 18 19 20 21 22 OVDD GND VDD VDD GND VREF SENSE VCM -AIN +AIN 1 JP1 2 1 2 JP2 3 1 2 JP3 4 1 2 VSS CLK OF GAIN U1, LTC1420 5 GND 6 2 C2 1 1F 7 8 2 C1 1 1F 23 24 25 26 27 28 OGND D0 D11 (MSB) 9 D1 D10 10 D2 D9 11 D3 D8 12 D4 D7 13 D5 D6 14
J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HD2X8-079
E2
APPLICATIONS INFORMATION
E4
E5
1 VDD 1 VSS
2 C5
1 1F
E6
1 AGND
1
E7
1 GAIN
1
JP6
2
1
JP5
2
D1 MBR0520LT1
2
JP4
2
1
J1 (J5) BNC (SMB)
1 +AIN
5432 1 2 R19 0
2
R15 51 OPT
J2 (J6) BNC (SMB)
J3 (J7) BNC (SMB)
1 -AIN
2345
1420 F14
5432
2
R16 51 OPT
Figure 14. LTC1420 Demo Board Schematic
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2 C4
1 1F
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E3
1 OVDD
2 C12
1 1F
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1 OGND
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VCC
E1
1 VCC
LTC1420
APPLICATIONS INFORMATION
Figure 15. Top Silkscreen Layer for LTC1420 Demo Board
Figure 16. Top Layer for LTC1420 Demo Board
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LTC1420
APPLICATIONS INFORMATION
Figure 17. Ground Plane Layer for LTC1420 Demo Board
Figure 18. Power Plane Layer for LTC1420 Demo Board
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LTC1420
APPLICATIONS INFORMATION
Figure 19. Bottom Layer for LTC1420 Demo Board
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LTC1420
TYPICAL APPLICATIONS
Single Supply, 10Msps, 12-Bit ADC with 3V Logic Outputs
LTC1420 ANALOG INPUT (2.5V 1.024V) 30 470pF NPO 1F 1 2 3 4 5 1F 6 7 1F 8 9 10 11 12 13 14 +AIN -AIN VCM SENSE VREF GND VDD GND D11 D10 D9 D8 D7 D6 GAIN OF CLK VSS GND VDD OVDD OGND D0 D1 D2 D3 D4 D5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0V TO 3V 12-BIT PARALLEL DATA PLUS OVERFLOW 1F 1F 3V 5V 10MHz CLOCK
5V
ANALOG INPUT (2.048V)
5V 1F
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1420 TA03
Dual Supply, 10Msps, 12-Bit ADC with 71dB SINAD
LTC1420 30 470pF, NPO 1 2 3 1F 4 5 1F 6 7 8 9 10 11 12 13 14 +AIN -AIN VCM SENSE VREF GND VDD GND D11 D10 D9 D8 D7 D6 GAIN OF CLK VSS GND VDD OVDD OGND D0 D1 D2 D3 D4 D5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12-BIT PARALLEL DATA PLUS OVERFLOW 1F 5V 1F 10MHz CLOCK -5V 5V
1420 TA04
LTC1420
PACKAGE DESCRIPTION
0.015 0.004 x 45 (0.38 0.10) 0.0075 - 0.0098 (0.191 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Dimensions in inches (millimeters) unless otherwise specified.
GN Package 28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.386 - 0.393* (9.804 - 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615
0.033 (0.838) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.351 - 1.748)
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4
56
7
8
9 10 11 12 13 14 0.004 - 0.009 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.0250 (0.635) BSC
GN28 (SSOP) 1098
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LTC1420
TYPICAL APPLICATION
Single 3.3V Supply, 10Msps, 12-Bit ADC
LTC1420 ANALOG INPUT (2.048VP-P) 15 15 470pF, NPO 1 2 3 1F 4 5 1.4MHz BOOST REGULATOR 4.7H 3.3V 0.1F 15F VIN SHDN SW LT1613 SHDN FB GND 5V 1F 6 7 0.1F 1F 8 9 10 32.4k 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0V TO 3.3V 12-BIT DATA 1F 3.3V 5V TO PIN 7 1F OVERFLOW BIT 10MHz CLOCK
+
100k 15F
4096 Point FFT of Above Circuit with a 1MHz Input. Note That There Are No Spurs From the 1.4MHz Boost Regulator
0 -20
AMPLITUDE (dB)
RELATED PARTS
PART NUMBER LTC1405 LTC1412 LTC1415 LT1019 DESCRIPTION 12-Bit, 5Msps, Sampling ADC with Parallel Output 12-Bit, 3Msps, Sampling ADC with Parallel Output Single 5V, 12-Bit, 1.25Msps with Parallel Output Precision Bandgap Reference COMMENTS Pin Compatible with the LTC1420 Best Dynamic Performance, SINAD = 72dB at Nyquist 55mW Power Dissipation, 72dB SINAD 0.05% Max Initial Accuracy, 5ppm/C Max Drift
1420f LT/TP 1299 4K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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+ -
+AIN -AIN VCM SENSE VREF GND VDD GND D11 D10 D9 D8 D7 D6
GAIN OF CLK VSS GND VDD OVDD OGND D0 D1 D2 D3 D4 D5
+
1420 TA05
fSAMPLE = 10Msps fIN = 1.0083MHz, 2VP-P SFDR = 83dB SINAD = 69.8dB
-40 -60 -80
-100 -120 0 1 2 3 FREQUENCY (MHz) 4 5
1420 TA06
(c) LINEAR TECHNOLOGY CORPORATION 1999

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